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clk: exynos4: Add missing sclk_audio0 clock
This clock is a parent of mout_spdif and sclk_pcm0. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -508,6 +508,8 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
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CLK_SET_RATE_PARENT, 0),
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GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0",
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SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
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GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
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CLK_SET_RATE_PARENT, 0),
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GATE(sclk_audio1, "sclk_audio1", "div_audio1", 0xc354, 0,
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CLK_SET_RATE_PARENT, 0),
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GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
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