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riscv, bpf: Support sign-extension mov insns

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Add support sign-extension mov instructions for RV64.

Signed-off-by: Pu Lehui <pulehui@huawei.com>
Acked-by: Björn Töpel <bjorn@kernel.org>
Link: https://lore.kernel.org/r/20230824095001.3408573-4-pulehui@huaweicloud.com
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
This commit is contained in:
Pu Lehui 2023-08-24 09:49:57 +00:00 committed by Alexei Starovoitov
parent 3d06d8163f
commit 694896ad3c
1 changed files with 13 additions and 1 deletions
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14
arch/riscv/net/bpf_jit_comp64.c
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@ -1047,7 +1047,19 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
emit_zext_32(rd, ctx); emit_zext_32(rd, ctx);
break; break;
} }
emit_mv(rd, rs, ctx); switch (insn->off) {
case 0:
emit_mv(rd, rs, ctx);
break;
case 8:
case 16:
emit_slli(RV_REG_T1, rs, 64 - insn->off, ctx);
emit_srai(rd, RV_REG_T1, 64 - insn->off, ctx);
break;
case 32:
emit_addiw(rd, rs, 0, ctx);
break;
}
if (!is64 && !aux->verifier_zext) if (!is64 && !aux->verifier_zext)
emit_zext_32(rd, ctx); emit_zext_32(rd, ctx);
break; break;