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drm/i915: Protect register macro arguments
Always put parens around macro argument evaluations. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä
Daniel Vetter
parent
699fc401da
commit
68d9753837
@ -429,7 +429,7 @@
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#define ASYNC_FLIP (1<<22)
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#define DISPLAY_PLANE_A (0<<20)
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#define DISPLAY_PLANE_B (1<<20)
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#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
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#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
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#define PIPE_CONTROL_FLUSH_L3 (1<<27)
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#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
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#define PIPE_CONTROL_MMIO_WRITE (1<<23)
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@ -1255,7 +1255,7 @@ enum skl_disp_power_wells {
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#define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
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#define PORT_PLL_DCO_AMP_DEFAULT 15
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#define PORT_PLL_DCO_AMP_MASK 0x3c00
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#define PORT_PLL_DCO_AMP(x) (x<<10)
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#define PORT_PLL_DCO_AMP(x) ((x)<<10)
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#define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \
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_PORT_PLL_0_B, \
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_PORT_PLL_0_C)
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@ -1552,8 +1552,8 @@ enum skl_disp_power_wells {
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#define RENDER_HWS_PGA_GEN7 (0x04080)
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#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
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#define RING_FAULT_GTTSEL_MASK (1<<11)
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#define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
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#define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
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#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
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#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
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#define RING_FAULT_VALID (1<<0)
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#define DONE_REG 0x40b0
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#define GEN8_PRIVATE_PAT_LO 0x40e0
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@ -1641,9 +1641,9 @@ enum skl_disp_power_wells {
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#define ERR_INT_PIPE_CRC_DONE_B (1<<5)
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#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
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#define ERR_INT_PIPE_CRC_DONE_A (1<<2)
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#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
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#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3))
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#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
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#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
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#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
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#define GEN8_FAULT_TLB_DATA0 0x04b10
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#define GEN8_FAULT_TLB_DATA1 0x04b14
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@ -1704,8 +1704,8 @@ enum skl_disp_power_wells {
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#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
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#define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
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#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
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#define GEN9_IZ_HASHING_MASK(slice) (0x3 << (slice * 2))
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#define GEN9_IZ_HASHING(slice, val) ((val) << (slice * 2))
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#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
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#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
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#define GFX_MODE 0x02520
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#define GFX_MODE_GEN7 0x0229c
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@ -2866,21 +2866,21 @@ enum skl_disp_power_wells {
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* doesn't need saving on GT1
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*/
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#define CXT_SIZE 0x21a0
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#define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
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#define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
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#define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
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#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
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#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
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#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
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#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
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#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
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#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
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#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
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#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
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GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
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GEN6_CXT_PIPELINE_SIZE(cxt_reg))
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#define GEN7_CXT_SIZE 0x21a8
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#define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
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#define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
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#define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
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#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
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#define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
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#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
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#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
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#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
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#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
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#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
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#define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
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#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
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#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
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GEN7_CXT_VFSTATE_SIZE(ctx_reg))
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/* Haswell does have the CXT_SIZE register however it does not appear to be
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@ -5223,18 +5223,18 @@ enum skl_disp_power_wells {
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#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
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#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
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#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
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#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
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#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
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#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
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#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
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#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
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#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
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#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
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#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
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#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
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#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
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#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
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#define SPCNTR(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
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#define SPLINOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
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#define SPSTRIDE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
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#define SPPOS(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
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#define SPSIZE(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
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#define SPKEYMINVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
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#define SPKEYMSK(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
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#define SPSURF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
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#define SPKEYMAXVAL(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
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#define SPTILEOFF(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
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#define SPCONSTALPHA(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
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#define SPGAMC(pipe, plane) _PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
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/*
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* CHV pipe B sprite CSC
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@ -5580,7 +5580,7 @@ enum skl_disp_power_wells {
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#define PS_SCALER_MODE_DYN (0 << 28)
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#define PS_SCALER_MODE_HQ (1 << 28)
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#define PS_PLANE_SEL_MASK (7 << 25)
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#define PS_PLANE_SEL(plane) ((plane + 1) << 25)
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#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
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#define PS_FILTER_MASK (3 << 23)
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#define PS_FILTER_MEDIUM (0 << 23)
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#define PS_FILTER_EDGE_ENHANCE (2 << 23)
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@ -5745,7 +5745,7 @@ enum skl_disp_power_wells {
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#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
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#define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
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#define DE_PIPEA_VBLANK_IVB (1<<0)
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#define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
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#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
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#define VLV_MASTER_IER 0x4400c /* Gunit master IER */
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#define MASTER_INTERRUPT_ENABLE (1<<31)
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@ -5769,7 +5769,7 @@ enum skl_disp_power_wells {
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#define GEN8_DE_PIPE_C_IRQ (1<<18)
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#define GEN8_DE_PIPE_B_IRQ (1<<17)
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#define GEN8_DE_PIPE_A_IRQ (1<<16)
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#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe))
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#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe)))
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#define GEN8_GT_VECS_IRQ (1<<6)
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#define GEN8_GT_PM_IRQ (1<<4)
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#define GEN8_GT_VCS2_IRQ (1<<3)
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@ -5813,7 +5813,7 @@ enum skl_disp_power_wells {
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#define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
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#define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
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#define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
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#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + p))
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#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
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#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
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(GEN8_PIPE_CURSOR_FAULT | \
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GEN8_PIPE_SPRITE_FAULT | \
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@ -6072,7 +6072,7 @@ enum skl_disp_power_wells {
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#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
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#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
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#define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
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#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
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#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
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/* digital port hotplug */
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#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
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@ -6183,9 +6183,9 @@ enum skl_disp_power_wells {
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#define PCH_SSC4_AUX_PARMS 0xc6214
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#define PCH_DPLL_SEL 0xc7000
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#define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
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#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
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#define TRANS_DPLLA_SEL(pipe) 0
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#define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
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#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
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/* transcoder */
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@ -7348,7 +7348,7 @@ enum skl_disp_power_wells {
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#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
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/* For each transcoder, we need to select the corresponding port clock */
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#define TRANS_CLK_SEL_DISABLED (0x0<<29)
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#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
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#define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29)
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#define TRANSA_MSA_MISC 0x60410
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#define TRANSB_MSA_MISC 0x61410
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@ -7421,10 +7421,10 @@ enum skl_disp_power_wells {
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/* DPLL control2 */
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#define DPLL_CTRL2 0x6C05C
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#define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15))
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#define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15))
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#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
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#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
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#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1))
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#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1))
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#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
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/* DPLL Status */
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@ -7437,23 +7437,23 @@ enum skl_disp_power_wells {
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#define DPLL3_CFGCR1 0x6C050
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#define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
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#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
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#define DPLL_CFGCR1_DCO_FRACTION(x) (x<<9)
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#define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9)
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#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
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#define DPLL1_CFGCR2 0x6C044
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#define DPLL2_CFGCR2 0x6C04C
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#define DPLL3_CFGCR2 0x6C054
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#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
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#define DPLL_CFGCR2_QDIV_RATIO(x) (x<<8)
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#define DPLL_CFGCR2_QDIV_MODE(x) (x<<7)
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#define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8)
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#define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7)
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#define DPLL_CFGCR2_KDIV_MASK (3<<5)
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#define DPLL_CFGCR2_KDIV(x) (x<<5)
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#define DPLL_CFGCR2_KDIV(x) ((x)<<5)
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#define DPLL_CFGCR2_KDIV_5 (0<<5)
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#define DPLL_CFGCR2_KDIV_2 (1<<5)
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#define DPLL_CFGCR2_KDIV_3 (2<<5)
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#define DPLL_CFGCR2_KDIV_1 (3<<5)
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#define DPLL_CFGCR2_PDIV_MASK (7<<2)
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#define DPLL_CFGCR2_PDIV(x) (x<<2)
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#define DPLL_CFGCR2_PDIV(x) ((x)<<2)
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#define DPLL_CFGCR2_PDIV_1 (0<<2)
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#define DPLL_CFGCR2_PDIV_2 (1<<2)
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#define DPLL_CFGCR2_PDIV_3 (2<<2)
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