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MIPS: ath79: add common SPI controller device
Several boards are using the built-in SPI controller of the AR71XX/AR724X/AR913X SoCs. This patch adds common platform_device and helper code to register it. Additionally, the patch registers the SPI bus on the PB44 board. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Cc: Imre Kaloz <kaloz@openwrt.org> Cc: Luis R. Rodriguez <lrodriguez@atheros.com> Cc: Cliff Holden <Cliff.Holden@Atheros.com> Cc: Kathy Giori <Kathy.Giori@Atheros.com> Patchwork: https://patchwork.linux-mips.org/patch/1956/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -7,6 +7,7 @@ config ATH79_MACH_PB44
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select SOC_AR71XX
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select ATH79_DEV_GPIO_BUTTONS
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select ATH79_DEV_LEDS_GPIO
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select ATH79_DEV_SPI
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help
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Say 'Y' here if you want your kernel to support the
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Atheros PB44 reference board.
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@ -28,4 +29,7 @@ config ATH79_DEV_GPIO_BUTTONS
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config ATH79_DEV_LEDS_GPIO
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def_bool n
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config ATH79_DEV_SPI
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def_bool n
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endif
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@ -18,6 +18,7 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-y += dev-common.o
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obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
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obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
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obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
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#
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# Machines
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38
arch/mips/ath79/dev-spi.c
Normal file
38
arch/mips/ath79/dev-spi.c
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@ -0,0 +1,38 @@
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/*
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* Atheros AR71XX/AR724X/AR913X SPI controller device
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*
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* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/platform_device.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "dev-spi.h"
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static struct resource ath79_spi_resources[] = {
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{
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.start = AR71XX_SPI_BASE,
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.end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device ath79_spi_device = {
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.name = "ath79-spi",
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.id = -1,
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.resource = ath79_spi_resources,
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.num_resources = ARRAY_SIZE(ath79_spi_resources),
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};
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void __init ath79_register_spi(struct ath79_spi_platform_data *pdata,
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struct spi_board_info const *info,
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unsigned n)
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{
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spi_register_board_info(info, n);
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ath79_spi_device.dev.platform_data = pdata;
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platform_device_register(&ath79_spi_device);
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}
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22
arch/mips/ath79/dev-spi.h
Normal file
22
arch/mips/ath79/dev-spi.h
Normal file
@ -0,0 +1,22 @@
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/*
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* Atheros AR71XX/AR724X/AR913X SPI controller device
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*
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* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _ATH79_DEV_SPI_H
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#define _ATH79_DEV_SPI_H
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#include <linux/spi/spi.h>
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#include <asm/mach-ath79/ath79_spi_platform.h>
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void ath79_register_spi(struct ath79_spi_platform_data *pdata,
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struct spi_board_info const *info,
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unsigned n);
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#endif /* _ATH79_DEV_SPI_H */
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@ -17,6 +17,7 @@
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#include "machtypes.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-spi.h"
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#define PB44_GPIO_I2C_SCL 0
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#define PB44_GPIO_I2C_SDA 1
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@ -84,6 +85,20 @@ static struct gpio_keys_button pb44_gpio_keys[] __initdata = {
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}
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};
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static struct spi_board_info pb44_spi_info[] = {
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{
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.bus_num = 0,
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.chip_select = 0,
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.max_speed_hz = 25000000,
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.modalias = "m25p64",
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},
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};
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static struct ath79_spi_platform_data pb44_spi_data = {
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.bus_num = 0,
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.num_chipselect = 1,
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};
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static void __init pb44_init(void)
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{
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i2c_register_board_info(0, pb44_i2c_board_info,
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@ -95,6 +110,8 @@ static void __init pb44_init(void)
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ath79_register_gpio_keys_polled(-1, PB44_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(pb44_gpio_keys),
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pb44_gpio_keys);
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ath79_register_spi(&pb44_spi_data, pb44_spi_info,
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ARRAY_SIZE(pb44_spi_info));
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}
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MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
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@ -20,6 +20,8 @@
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#include <linux/bitops.h>
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#define AR71XX_APB_BASE 0x18000000
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#define AR71XX_SPI_BASE 0x1f000000
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#define AR71XX_SPI_SIZE 0x01000000
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#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
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#define AR71XX_DDR_CTRL_SIZE 0x100
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