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clk: qcom: Add support for controlling Fabia PLL
Fabia PLL is a Digital Frequency Locked Loop (DFLL) clock
generator which has a wide range of frequency output. It
supports dynamic updating of the output frequency
("frequency slewing") without need to turn off the PLL
before configuration. Add support for initial configuration
and programming sequence to control fabia PLLs.
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
[sboyd: Shorten code a little]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Amit Nischal
Stephen Boyd
parent
bdc3bbdd40
commit
687d7a0caa
@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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@ -58,6 +58,8 @@
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#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
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#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
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#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
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#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
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#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
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const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
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[CLK_ALPHA_PLL_TYPE_DEFAULT] = {
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@ -90,6 +92,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
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[PLL_OFF_TEST_CTL] = 0x1c,
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[PLL_OFF_STATUS] = 0x24,
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},
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[CLK_ALPHA_PLL_TYPE_FABIA] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_USER_CTL] = 0x0c,
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[PLL_OFF_USER_CTL_U] = 0x10,
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[PLL_OFF_CONFIG_CTL] = 0x14,
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[PLL_OFF_CONFIG_CTL_U] = 0x18,
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[PLL_OFF_TEST_CTL] = 0x1c,
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[PLL_OFF_TEST_CTL_U] = 0x20,
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[PLL_OFF_STATUS] = 0x24,
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[PLL_OFF_OPMODE] = 0x2c,
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[PLL_OFF_FRAC] = 0x38,
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},
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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@ -108,6 +122,12 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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#define PLL_HUAYRA_N_MASK 0xff
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#define PLL_HUAYRA_ALPHA_WIDTH 16
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#define FABIA_OPMODE_STANDBY 0x0
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#define FABIA_OPMODE_RUN 0x1
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#define FABIA_PLL_OUT_MASK 0x7
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#define FABIA_PLL_RATE_MARGIN 500
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#define pll_alpha_width(p) \
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((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
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ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
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@ -441,16 +461,12 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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return alpha_pll_calc_rate(prate, l, a, alpha_width);
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}
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static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
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int (*is_enabled)(struct clk_hw *))
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static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
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{
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int ret;
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u32 mode;
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if (!is_enabled(&pll->clkr.hw) ||
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!(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
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return 0;
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regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
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/* Latch the input to the PLL */
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@ -489,6 +505,16 @@ static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
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return 0;
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}
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static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
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int (*is_enabled)(struct clk_hw *))
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{
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if (!is_enabled(&pll->clkr.hw) ||
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!(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
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return 0;
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return __clk_alpha_pll_update_latch(pll);
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}
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static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long prate,
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int (*is_enabled)(struct clk_hw *))
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@ -832,3 +858,264 @@ const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
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.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
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void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config)
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{
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u32 val, mask;
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if (config->l)
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regmap_write(regmap, PLL_L_VAL(pll), config->l);
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if (config->alpha)
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regmap_write(regmap, PLL_FRAC(pll), config->alpha);
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if (config->config_ctl_val)
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regmap_write(regmap, PLL_CONFIG_CTL(pll),
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config->config_ctl_val);
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if (config->post_div_mask) {
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mask = config->post_div_mask;
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val = config->post_div_val;
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regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
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}
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regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
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PLL_UPDATE_BYPASS);
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regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
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}
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static int alpha_pll_fabia_enable(struct clk_hw *hw)
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{
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int ret;
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 val, opmode_val;
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struct regmap *regmap = pll->clkr.regmap;
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ret = regmap_read(regmap, PLL_MODE(pll), &val);
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if (ret)
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return ret;
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/* If in FSM mode, just vote for it */
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if (val & PLL_VOTE_FSM_ENA) {
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ret = clk_enable_regmap(hw);
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if (ret)
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return ret;
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return wait_for_pll_enable_active(pll);
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}
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ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
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if (ret)
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return ret;
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/* Skip If PLL is already running */
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if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL))
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return 0;
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ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
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if (ret)
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return ret;
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ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
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if (ret)
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return ret;
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ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
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PLL_RESET_N);
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if (ret)
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return ret;
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ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN);
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if (ret)
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return ret;
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ret = wait_for_pll_enable_lock(pll);
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if (ret)
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return ret;
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ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
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FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK);
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if (ret)
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return ret;
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return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
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PLL_OUTCTRL);
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}
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static void alpha_pll_fabia_disable(struct clk_hw *hw)
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{
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int ret;
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 val;
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struct regmap *regmap = pll->clkr.regmap;
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ret = regmap_read(regmap, PLL_MODE(pll), &val);
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if (ret)
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return;
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/* If in FSM mode, just unvote it */
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if (val & PLL_FSM_ENA) {
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clk_disable_regmap(hw);
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return;
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}
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ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
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if (ret)
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return;
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/* Disable main outputs */
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ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK,
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0);
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if (ret)
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return;
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/* Place the PLL in STANDBY */
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regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
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}
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static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 l, frac, alpha_width = pll_alpha_width(pll);
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regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
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regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
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return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
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}
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static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long prate)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 val, l, alpha_width = pll_alpha_width(pll);
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u64 a;
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unsigned long rrate;
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int ret = 0;
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ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
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if (ret)
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return ret;
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rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
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/*
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* Due to limited number of bits for fractional rate programming, the
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* rounded up rate could be marginally higher than the requested rate.
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*/
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if (rrate > (rate + FABIA_PLL_RATE_MARGIN) || rrate < rate) {
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pr_err("Call set rate on the PLL with rounded rates!\n");
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return -EINVAL;
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}
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regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
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regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
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return __clk_alpha_pll_update_latch(pll);
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}
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const struct clk_ops clk_alpha_pll_fabia_ops = {
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.enable = alpha_pll_fabia_enable,
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.disable = alpha_pll_fabia_disable,
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.is_enabled = clk_alpha_pll_is_enabled,
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.set_rate = alpha_pll_fabia_set_rate,
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.recalc_rate = alpha_pll_fabia_recalc_rate,
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.round_rate = clk_alpha_pll_round_rate,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
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const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
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.enable = alpha_pll_fabia_enable,
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.disable = alpha_pll_fabia_disable,
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.is_enabled = clk_alpha_pll_is_enabled,
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.recalc_rate = alpha_pll_fabia_recalc_rate,
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.round_rate = clk_alpha_pll_round_rate,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
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static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
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u32 i, div = 1, val;
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int ret;
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if (!pll->post_div_table) {
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pr_err("Missing the post_div_table for the PLL\n");
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return -EINVAL;
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}
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ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
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if (ret)
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return ret;
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val >>= pll->post_div_shift;
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val &= BIT(pll->width) - 1;
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for (i = 0; i < pll->num_post_div; i++) {
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if (pll->post_div_table[i].val == val) {
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div = pll->post_div_table[i].div;
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break;
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}
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}
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return (parent_rate / div);
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}
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static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long *prate)
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{
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struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
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if (!pll->post_div_table) {
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pr_err("Missing the post_div_table for the PLL\n");
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return -EINVAL;
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}
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return divider_round_rate(hw, rate, prate, pll->post_div_table,
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pll->width, CLK_DIVIDER_ROUND_CLOSEST);
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}
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static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate)
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{
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struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
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int i, val = 0, div, ret;
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/*
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* If the PLL is in FSM mode, then treat set_rate callback as a
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* no-operation.
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*/
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ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
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if (ret)
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return ret;
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if (val & PLL_VOTE_FSM_ENA)
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return 0;
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if (!pll->post_div_table) {
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pr_err("Missing the post_div_table for the PLL\n");
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return -EINVAL;
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}
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div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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for (i = 0; i < pll->num_post_div; i++) {
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if (pll->post_div_table[i].div == div) {
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val = pll->post_div_table[i].val;
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break;
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}
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}
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return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
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(BIT(pll->width) - 1) << pll->post_div_shift,
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val << pll->post_div_shift);
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}
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const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
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.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
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.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
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.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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@ -22,6 +22,7 @@ enum {
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CLK_ALPHA_PLL_TYPE_DEFAULT,
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CLK_ALPHA_PLL_TYPE_HUAYRA,
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CLK_ALPHA_PLL_TYPE_BRAMMO,
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CLK_ALPHA_PLL_TYPE_FABIA,
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CLK_ALPHA_PLL_TYPE_MAX,
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};
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@ -36,6 +37,8 @@ enum {
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PLL_OFF_TEST_CTL,
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PLL_OFF_TEST_CTL_U,
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PLL_OFF_STATUS,
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PLL_OFF_OPMODE,
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PLL_OFF_FRAC,
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PLL_OFF_MAX_REGS
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};
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@ -73,6 +76,10 @@ struct clk_alpha_pll {
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* @offset: base address of registers
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* @regs: alpha pll register map (see @clk_alpha_pll_regs)
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* @width: width of post-divider
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* @post_div_shift: shift to differentiate between odd & even post-divider
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* @post_div_table: table with PLL odd and even post-divider settings
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* @num_post_div: Number of PLL post-divider settings
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*
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* @clkr: regmap clock handle
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*/
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struct clk_alpha_pll_postdiv {
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@ -81,6 +88,9 @@ struct clk_alpha_pll_postdiv {
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const u8 *regs;
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struct clk_regmap clkr;
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int post_div_shift;
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const struct clk_div_table *post_div_table;
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size_t num_post_div;
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};
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struct alpha_pll_config {
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@ -109,7 +119,13 @@ extern const struct clk_ops clk_alpha_pll_postdiv_ops;
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extern const struct clk_ops clk_alpha_pll_huayra_ops;
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extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
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extern const struct clk_ops clk_alpha_pll_fabia_ops;
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extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
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extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
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void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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#endif
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