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riscv: dts: sophgo: add initial CV1812H SoC device tree

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Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Acked-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Inochi Amaoto 2023-10-19 07:18:53 +08:00 committed by Conor Dooley
parent dd791b45c8
commit 681ec684a7
1 changed files with 24 additions and 0 deletions
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arch/riscv/boot/dts/sophgo/cv1812h.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "cv18xx.dtsi"
/ {
compatible = "sophgo,cv1812h";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
};
&plic {
compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
};
&clint {
compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
};