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mtd: nand: add OMAP2/OMAP3 NAND driver
This driver is present in the OMAP tree, now pushing it to MTD.
Original author(s):
Jian Zhang <jzhang@ti.com>
Signed-off-by: Vimal Singh <vimalsingh@ti.com>
Cc: Jian Zhang <jzhang@ti.com>
Cc: Artem Bityutskiy <dedekind@infradead.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Vimal Singh
David Woodhouse
parent
4938c88c92
commit
67ce04bf27
@ -74,6 +74,12 @@ config MTD_NAND_AMS_DELTA
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help
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Support for NAND flash on Amstrad E3 (Delta).
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config MTD_NAND_OMAP2
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tristate "NAND Flash device on OMAP2 and OMAP3"
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depends on ARM && MTD_NAND && (ARCH_OMAP2 || ARCH_OMAP3)
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help
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Support for NAND flash on Texas Instruments OMAP2 and OMAP3 platforms.
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config MTD_NAND_TS7250
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tristate "NAND Flash device on TS-7250 board"
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depends on MACH_TS72XX
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@ -25,6 +25,7 @@ obj-$(CONFIG_MTD_NAND_CS553X) += cs553x_nand.o
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obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o
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obj-$(CONFIG_MTD_NAND_ATMEL) += atmel_nand.o
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obj-$(CONFIG_MTD_NAND_GPIO) += gpio.o
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obj-$(CONFIG_MTD_NAND_OMAP2) += omap2.o
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obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o
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obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o
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obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o
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776
drivers/mtd/nand/omap2.c
Normal file
776
drivers/mtd/nand/omap2.c
Normal file
@ -0,0 +1,776 @@
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/*
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* Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
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* Copyright © 2004 Micron Technology Inc.
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* Copyright © 2004 David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/io.h>
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#include <asm/dma.h>
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#include <mach/gpmc.h>
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#include <mach/nand.h>
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#define GPMC_IRQ_STATUS 0x18
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#define GPMC_ECC_CONFIG 0x1F4
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#define GPMC_ECC_CONTROL 0x1F8
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#define GPMC_ECC_SIZE_CONFIG 0x1FC
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#define GPMC_ECC1_RESULT 0x200
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#define DRIVER_NAME "omap2-nand"
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/* size (4 KiB) for IO mapping */
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#define NAND_IO_SIZE SZ_4K
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#define NAND_WP_OFF 0
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#define NAND_WP_BIT 0x00000010
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#define WR_RD_PIN_MONITORING 0x00600000
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#define GPMC_BUF_FULL 0x00000001
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#define GPMC_BUF_EMPTY 0x00000000
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#define NAND_Ecc_P1e (1 << 0)
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#define NAND_Ecc_P2e (1 << 1)
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#define NAND_Ecc_P4e (1 << 2)
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#define NAND_Ecc_P8e (1 << 3)
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#define NAND_Ecc_P16e (1 << 4)
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#define NAND_Ecc_P32e (1 << 5)
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#define NAND_Ecc_P64e (1 << 6)
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#define NAND_Ecc_P128e (1 << 7)
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#define NAND_Ecc_P256e (1 << 8)
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#define NAND_Ecc_P512e (1 << 9)
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#define NAND_Ecc_P1024e (1 << 10)
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#define NAND_Ecc_P2048e (1 << 11)
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#define NAND_Ecc_P1o (1 << 16)
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#define NAND_Ecc_P2o (1 << 17)
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#define NAND_Ecc_P4o (1 << 18)
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#define NAND_Ecc_P8o (1 << 19)
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#define NAND_Ecc_P16o (1 << 20)
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#define NAND_Ecc_P32o (1 << 21)
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#define NAND_Ecc_P64o (1 << 22)
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#define NAND_Ecc_P128o (1 << 23)
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#define NAND_Ecc_P256o (1 << 24)
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#define NAND_Ecc_P512o (1 << 25)
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#define NAND_Ecc_P1024o (1 << 26)
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#define NAND_Ecc_P2048o (1 << 27)
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#define TF(value) (value ? 1 : 0)
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#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
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#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
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#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
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#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
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#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
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#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
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#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
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#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
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#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
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#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
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#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
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#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
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#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
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#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
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#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
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#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
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#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
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#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
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#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
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#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
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#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
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#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
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#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
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#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
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#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
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#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
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#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
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#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
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#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
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#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
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#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
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#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
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#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
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#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
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#ifdef CONFIG_MTD_PARTITIONS
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static const char *part_probes[] = { "cmdlinepart", NULL };
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#endif
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struct omap_nand_info {
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struct nand_hw_control controller;
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struct omap_nand_platform_data *pdata;
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struct mtd_info mtd;
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struct mtd_partition *parts;
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struct nand_chip nand;
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struct platform_device *pdev;
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int gpmc_cs;
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unsigned long phys_base;
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void __iomem *gpmc_cs_baseaddr;
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void __iomem *gpmc_baseaddr;
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};
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/**
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* omap_nand_wp - This function enable or disable the Write Protect feature
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* @mtd: MTD device structure
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* @mode: WP ON/OFF
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*/
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static void omap_nand_wp(struct mtd_info *mtd, int mode)
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{
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struct omap_nand_info *info = container_of(mtd,
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struct omap_nand_info, mtd);
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unsigned long config = __raw_readl(info->gpmc_baseaddr + GPMC_CONFIG);
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if (mode)
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config &= ~(NAND_WP_BIT); /* WP is ON */
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else
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config |= (NAND_WP_BIT); /* WP is OFF */
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__raw_writel(config, (info->gpmc_baseaddr + GPMC_CONFIG));
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}
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/**
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* omap_hwcontrol - hardware specific access to control-lines
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* @mtd: MTD device structure
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* @cmd: command to device
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* @ctrl:
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* NAND_NCE: bit 0 -> don't care
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* NAND_CLE: bit 1 -> Command Latch
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* NAND_ALE: bit 2 -> Address Latch
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*
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* NOTE: boards may use different bits for these!!
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*/
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static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct omap_nand_info *info = container_of(mtd,
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struct omap_nand_info, mtd);
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switch (ctrl) {
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case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
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info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
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GPMC_CS_NAND_COMMAND;
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info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
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GPMC_CS_NAND_DATA;
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break;
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case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
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info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
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GPMC_CS_NAND_ADDRESS;
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info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
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GPMC_CS_NAND_DATA;
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break;
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case NAND_CTRL_CHANGE | NAND_NCE:
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info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr +
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GPMC_CS_NAND_DATA;
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info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr +
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GPMC_CS_NAND_DATA;
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break;
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}
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if (cmd != NAND_CMD_NONE)
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__raw_writeb(cmd, info->nand.IO_ADDR_W);
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}
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/**
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* omap_read_buf16 - read data from NAND controller into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store date
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* @len: number of bytes to read
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*/
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static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct nand_chip *nand = mtd->priv;
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__raw_readsw(nand->IO_ADDR_R, buf, len / 2);
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}
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/**
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* omap_write_buf16 - write buffer to NAND controller
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*/
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static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
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{
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struct omap_nand_info *info = container_of(mtd,
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struct omap_nand_info, mtd);
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u16 *p = (u16 *) buf;
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/* FIXME try bursts of writesw() or DMA ... */
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len >>= 1;
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while (len--) {
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writew(*p++, info->nand.IO_ADDR_W);
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while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr +
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GPMC_STATUS) & GPMC_BUF_FULL))
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;
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}
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}
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/**
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* omap_verify_buf - Verify chip data against buffer
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* @mtd: MTD device structure
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* @buf: buffer containing the data to compare
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* @len: number of bytes to compare
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*/
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static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
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{
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struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
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mtd);
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u16 *p = (u16 *) buf;
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len >>= 1;
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while (len--) {
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if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
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return -EFAULT;
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}
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return 0;
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}
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#ifdef CONFIG_MTD_NAND_OMAP_HWECC
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/**
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* omap_hwecc_init - Initialize the HW ECC for NAND flash in GPMC controller
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* @mtd: MTD device structure
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*/
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static void omap_hwecc_init(struct mtd_info *mtd)
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{
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struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
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mtd);
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struct nand_chip *chip = mtd->priv;
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unsigned long val = 0x0;
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/* Read from ECC Control Register */
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val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONTROL);
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/* Clear all ECC | Enable Reg1 */
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val = ((0x00000001<<8) | 0x00000001);
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__raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
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/* Read from ECC Size Config Register */
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val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
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/* ECCSIZE1=512 | Select eccResultsize[0-3] */
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val = ((((chip->ecc.size >> 1) - 1) << 22) | (0x0000000F));
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__raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG);
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}
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/**
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* gen_true_ecc - This function will generate true ECC value
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* @ecc_buf: buffer to store ecc code
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*
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* This generated true ECC value can be used when correcting
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* data read from NAND flash memory core
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*/
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static void gen_true_ecc(u8 *ecc_buf)
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{
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u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
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((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
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ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
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P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
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ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
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P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
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ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
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P1e(tmp) | P2048o(tmp) | P2048e(tmp));
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}
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/**
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* omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
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* @ecc_data1: ecc code from nand spare area
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* @ecc_data2: ecc code from hardware register obtained from hardware ecc
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* @page_data: page data
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*
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* This function compares two ECC's and indicates if there is an error.
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* If the error can be corrected it will be corrected to the buffer.
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*/
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static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
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u8 *ecc_data2, /* read from register */
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u8 *page_data)
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{
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uint i;
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u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
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u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
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u8 ecc_bit[24];
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u8 ecc_sum = 0;
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u8 find_bit = 0;
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uint find_byte = 0;
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int isEccFF;
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isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
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gen_true_ecc(ecc_data1);
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gen_true_ecc(ecc_data2);
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for (i = 0; i <= 2; i++) {
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*(ecc_data1 + i) = ~(*(ecc_data1 + i));
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*(ecc_data2 + i) = ~(*(ecc_data2 + i));
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}
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for (i = 0; i < 8; i++) {
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tmp0_bit[i] = *ecc_data1 % 2;
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*ecc_data1 = *ecc_data1 / 2;
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}
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for (i = 0; i < 8; i++) {
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tmp1_bit[i] = *(ecc_data1 + 1) % 2;
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*(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
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}
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for (i = 0; i < 8; i++) {
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tmp2_bit[i] = *(ecc_data1 + 2) % 2;
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*(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
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}
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for (i = 0; i < 8; i++) {
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comp0_bit[i] = *ecc_data2 % 2;
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*ecc_data2 = *ecc_data2 / 2;
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}
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for (i = 0; i < 8; i++) {
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comp1_bit[i] = *(ecc_data2 + 1) % 2;
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*(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
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}
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for (i = 0; i < 8; i++) {
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comp2_bit[i] = *(ecc_data2 + 2) % 2;
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*(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
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}
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for (i = 0; i < 6; i++)
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ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
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for (i = 0; i < 8; i++)
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ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
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|
||||
for (i = 0; i < 8; i++)
|
||||
ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
|
||||
|
||||
ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
|
||||
ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
|
||||
|
||||
for (i = 0; i < 24; i++)
|
||||
ecc_sum += ecc_bit[i];
|
||||
|
||||
switch (ecc_sum) {
|
||||
case 0:
|
||||
/* Not reached because this function is not called if
|
||||
* ECC values are equal
|
||||
*/
|
||||
return 0;
|
||||
|
||||
case 1:
|
||||
/* Uncorrectable error */
|
||||
DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
|
||||
return -1;
|
||||
|
||||
case 11:
|
||||
/* UN-Correctable error */
|
||||
DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR B\n");
|
||||
return -1;
|
||||
|
||||
case 12:
|
||||
/* Correctable error */
|
||||
find_byte = (ecc_bit[23] << 8) +
|
||||
(ecc_bit[21] << 7) +
|
||||
(ecc_bit[19] << 6) +
|
||||
(ecc_bit[17] << 5) +
|
||||
(ecc_bit[15] << 4) +
|
||||
(ecc_bit[13] << 3) +
|
||||
(ecc_bit[11] << 2) +
|
||||
(ecc_bit[9] << 1) +
|
||||
ecc_bit[7];
|
||||
|
||||
find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
|
||||
|
||||
DEBUG(MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at "
|
||||
"offset: %d, bit: %d\n", find_byte, find_bit);
|
||||
|
||||
page_data[find_byte] ^= (1 << find_bit);
|
||||
|
||||
return 0;
|
||||
default:
|
||||
if (isEccFF) {
|
||||
if (ecc_data2[0] == 0 &&
|
||||
ecc_data2[1] == 0 &&
|
||||
ecc_data2[2] == 0)
|
||||
return 0;
|
||||
}
|
||||
DEBUG(MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_correct_data - Compares the ECC read with HW generated ECC
|
||||
* @mtd: MTD device structure
|
||||
* @dat: page data
|
||||
* @read_ecc: ecc read from nand flash
|
||||
* @calc_ecc: ecc read from HW ECC registers
|
||||
*
|
||||
* Compares the ecc read from nand spare area with ECC registers values
|
||||
* and if ECC's mismached, it will call 'omap_compare_ecc' for error detection
|
||||
* and correction.
|
||||
*/
|
||||
static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
|
||||
u_char *read_ecc, u_char *calc_ecc)
|
||||
{
|
||||
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
|
||||
mtd);
|
||||
int blockCnt = 0, i = 0, ret = 0;
|
||||
|
||||
/* Ex NAND_ECC_HW12_2048 */
|
||||
if ((info->nand.ecc.mode == NAND_ECC_HW) &&
|
||||
(info->nand.ecc.size == 2048))
|
||||
blockCnt = 4;
|
||||
else
|
||||
blockCnt = 1;
|
||||
|
||||
for (i = 0; i < blockCnt; i++) {
|
||||
if (memcmp(read_ecc, calc_ecc, 3) != 0) {
|
||||
ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
read_ecc += 3;
|
||||
calc_ecc += 3;
|
||||
dat += 512;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_calcuate_ecc - Generate non-inverted ECC bytes.
|
||||
* @mtd: MTD device structure
|
||||
* @dat: The pointer to data on which ecc is computed
|
||||
* @ecc_code: The ecc_code buffer
|
||||
*
|
||||
* Using noninverted ECC can be considered ugly since writing a blank
|
||||
* page ie. padding will clear the ECC bytes. This is no problem as long
|
||||
* nobody is trying to write data on the seemingly unused page. Reading
|
||||
* an erased page will produce an ECC mismatch between generated and read
|
||||
* ECC bytes that has to be dealt with separately.
|
||||
*/
|
||||
static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
|
||||
u_char *ecc_code)
|
||||
{
|
||||
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
|
||||
mtd);
|
||||
unsigned long val = 0x0;
|
||||
unsigned long reg;
|
||||
|
||||
/* Start Reading from HW ECC1_Result = 0x200 */
|
||||
reg = (unsigned long)(info->gpmc_baseaddr + GPMC_ECC1_RESULT);
|
||||
val = __raw_readl(reg);
|
||||
*ecc_code++ = val; /* P128e, ..., P1e */
|
||||
*ecc_code++ = val >> 16; /* P128o, ..., P1o */
|
||||
/* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
|
||||
*ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
|
||||
reg += 4;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_enable_hwecc - This function enables the hardware ecc functionality
|
||||
* @mtd: MTD device structure
|
||||
* @mode: Read/Write mode
|
||||
*/
|
||||
static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
|
||||
{
|
||||
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
|
||||
mtd);
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
|
||||
unsigned long val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONFIG);
|
||||
|
||||
switch (mode) {
|
||||
case NAND_ECC_READ:
|
||||
__raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
|
||||
/* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
|
||||
val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
|
||||
break;
|
||||
case NAND_ECC_READSYN:
|
||||
__raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
|
||||
/* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
|
||||
val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
|
||||
break;
|
||||
case NAND_ECC_WRITE:
|
||||
__raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL);
|
||||
/* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
|
||||
val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
|
||||
break;
|
||||
default:
|
||||
DEBUG(MTD_DEBUG_LEVEL0, "Error: Unrecognized Mode[%d]!\n",
|
||||
mode);
|
||||
break;
|
||||
}
|
||||
|
||||
__raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONFIG);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* omap_wait - wait until the command is done
|
||||
* @mtd: MTD device structure
|
||||
* @chip: NAND Chip structure
|
||||
*
|
||||
* Wait function is called during Program and erase operations and
|
||||
* the way it is called from MTD layer, we should wait till the NAND
|
||||
* chip is ready after the programming/erase operation has completed.
|
||||
*
|
||||
* Erase can take up to 400ms and program up to 20ms according to
|
||||
* general NAND and SmartMedia specs
|
||||
*/
|
||||
static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
|
||||
mtd);
|
||||
unsigned long timeo = jiffies;
|
||||
int status, state = this->state;
|
||||
|
||||
if (state == FL_ERASING)
|
||||
timeo += (HZ * 400) / 1000;
|
||||
else
|
||||
timeo += (HZ * 20) / 1000;
|
||||
|
||||
this->IO_ADDR_W = (void *) info->gpmc_cs_baseaddr +
|
||||
GPMC_CS_NAND_COMMAND;
|
||||
this->IO_ADDR_R = (void *) info->gpmc_cs_baseaddr + GPMC_CS_NAND_DATA;
|
||||
|
||||
__raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W);
|
||||
|
||||
while (time_before(jiffies, timeo)) {
|
||||
status = __raw_readb(this->IO_ADDR_R);
|
||||
if (!(status & 0x40))
|
||||
break;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap_dev_ready - calls the platform specific dev_ready function
|
||||
* @mtd: MTD device structure
|
||||
*/
|
||||
static int omap_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
|
||||
mtd);
|
||||
unsigned int val = __raw_readl(info->gpmc_baseaddr + GPMC_IRQ_STATUS);
|
||||
|
||||
if ((val & 0x100) == 0x100) {
|
||||
/* Clear IRQ Interrupt */
|
||||
val |= 0x100;
|
||||
val &= ~(0x0);
|
||||
__raw_writel(val, info->gpmc_baseaddr + GPMC_IRQ_STATUS);
|
||||
} else {
|
||||
unsigned int cnt = 0;
|
||||
while (cnt++ < 0x1FF) {
|
||||
if ((val & 0x100) == 0x100)
|
||||
return 0;
|
||||
val = __raw_readl(info->gpmc_baseaddr +
|
||||
GPMC_IRQ_STATUS);
|
||||
}
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int __devinit omap_nand_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct omap_nand_info *info;
|
||||
struct omap_nand_platform_data *pdata;
|
||||
int err;
|
||||
unsigned long val;
|
||||
|
||||
|
||||
pdata = pdev->dev.platform_data;
|
||||
if (pdata == NULL) {
|
||||
dev_err(&pdev->dev, "platform data missing\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
|
||||
if (!info)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, info);
|
||||
|
||||
spin_lock_init(&info->controller.lock);
|
||||
init_waitqueue_head(&info->controller.wq);
|
||||
|
||||
info->pdev = pdev;
|
||||
|
||||
info->gpmc_cs = pdata->cs;
|
||||
info->gpmc_baseaddr = pdata->gpmc_baseaddr;
|
||||
info->gpmc_cs_baseaddr = pdata->gpmc_cs_baseaddr;
|
||||
|
||||
info->mtd.priv = &info->nand;
|
||||
info->mtd.name = dev_name(&pdev->dev);
|
||||
info->mtd.owner = THIS_MODULE;
|
||||
|
||||
err = gpmc_cs_request(info->gpmc_cs, NAND_IO_SIZE, &info->phys_base);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "Cannot request GPMC CS\n");
|
||||
goto out_free_info;
|
||||
}
|
||||
|
||||
/* Enable RD PIN Monitoring Reg */
|
||||
if (pdata->dev_ready) {
|
||||
val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1);
|
||||
val |= WR_RD_PIN_MONITORING;
|
||||
gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val);
|
||||
}
|
||||
|
||||
val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7);
|
||||
val &= ~(0xf << 8);
|
||||
val |= (0xc & 0xf) << 8;
|
||||
gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val);
|
||||
|
||||
/* NAND write protect off */
|
||||
omap_nand_wp(&info->mtd, NAND_WP_OFF);
|
||||
|
||||
if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
|
||||
pdev->dev.driver->name)) {
|
||||
err = -EBUSY;
|
||||
goto out_free_cs;
|
||||
}
|
||||
|
||||
info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
|
||||
if (!info->nand.IO_ADDR_R) {
|
||||
err = -ENOMEM;
|
||||
goto out_release_mem_region;
|
||||
}
|
||||
info->nand.controller = &info->controller;
|
||||
|
||||
info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
|
||||
info->nand.cmd_ctrl = omap_hwcontrol;
|
||||
|
||||
/* REVISIT: only supports 16-bit NAND flash */
|
||||
|
||||
info->nand.read_buf = omap_read_buf16;
|
||||
info->nand.write_buf = omap_write_buf16;
|
||||
info->nand.verify_buf = omap_verify_buf;
|
||||
|
||||
/*
|
||||
* If RDY/BSY line is connected to OMAP then use the omap ready
|
||||
* funcrtion and the generic nand_wait function which reads the status
|
||||
* register after monitoring the RDY/BSY line.Otherwise use a standard
|
||||
* chip delay which is slightly more than tR (AC Timing) of the NAND
|
||||
* device and read status register until you get a failure or success
|
||||
*/
|
||||
if (pdata->dev_ready) {
|
||||
info->nand.dev_ready = omap_dev_ready;
|
||||
info->nand.chip_delay = 0;
|
||||
} else {
|
||||
info->nand.waitfunc = omap_wait;
|
||||
info->nand.chip_delay = 50;
|
||||
}
|
||||
|
||||
info->nand.options |= NAND_SKIP_BBTSCAN;
|
||||
if ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000)
|
||||
== 0x1000)
|
||||
info->nand.options |= NAND_BUSWIDTH_16;
|
||||
|
||||
#ifdef CONFIG_MTD_NAND_OMAP_HWECC
|
||||
info->nand.ecc.bytes = 3;
|
||||
info->nand.ecc.size = 512;
|
||||
info->nand.ecc.calculate = omap_calculate_ecc;
|
||||
info->nand.ecc.hwctl = omap_enable_hwecc;
|
||||
info->nand.ecc.correct = omap_correct_data;
|
||||
info->nand.ecc.mode = NAND_ECC_HW;
|
||||
|
||||
/* init HW ECC */
|
||||
omap_hwecc_init(&info->mtd);
|
||||
#else
|
||||
info->nand.ecc.mode = NAND_ECC_SOFT;
|
||||
#endif
|
||||
|
||||
/* DIP switches on some boards change between 8 and 16 bit
|
||||
* bus widths for flash. Try the other width if the first try fails.
|
||||
*/
|
||||
if (nand_scan(&info->mtd, 1)) {
|
||||
info->nand.options ^= NAND_BUSWIDTH_16;
|
||||
if (nand_scan(&info->mtd, 1)) {
|
||||
err = -ENXIO;
|
||||
goto out_release_mem_region;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MTD_PARTITIONS
|
||||
err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
|
||||
if (err > 0)
|
||||
add_mtd_partitions(&info->mtd, info->parts, err);
|
||||
else if (pdata->parts)
|
||||
add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
|
||||
else
|
||||
#endif
|
||||
add_mtd_device(&info->mtd);
|
||||
|
||||
platform_set_drvdata(pdev, &info->mtd);
|
||||
|
||||
return 0;
|
||||
|
||||
out_release_mem_region:
|
||||
release_mem_region(info->phys_base, NAND_IO_SIZE);
|
||||
out_free_cs:
|
||||
gpmc_cs_free(info->gpmc_cs);
|
||||
out_free_info:
|
||||
kfree(info);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int omap_nand_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mtd_info *mtd = platform_get_drvdata(pdev);
|
||||
struct omap_nand_info *info = mtd->priv;
|
||||
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
/* Release NAND device, its internal structures and partitions */
|
||||
nand_release(&info->mtd);
|
||||
iounmap(info->nand.IO_ADDR_R);
|
||||
kfree(&info->mtd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver omap_nand_driver = {
|
||||
.probe = omap_nand_probe,
|
||||
.remove = omap_nand_remove,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init omap_nand_init(void)
|
||||
{
|
||||
printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME);
|
||||
return platform_driver_register(&omap_nand_driver);
|
||||
}
|
||||
|
||||
static void __exit omap_nand_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&omap_nand_driver);
|
||||
}
|
||||
|
||||
module_init(omap_nand_init);
|
||||
module_exit(omap_nand_exit);
|
||||
|
||||
MODULE_ALIAS(DRIVER_NAME);
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");
|
||||
Loading…
Reference in New Issue
Block a user