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dt-bindings: arm: Convert cpu binding to json-schema
Convert ARM CPU binding to DT schema format using json-schema. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Rob Herring
parent
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commit
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=================
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ARM CPUs bindings
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=================
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The device tree allows to describe the layout of CPUs in a system through
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the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
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defining properties for every cpu.
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Bindings for CPU nodes follow the Devicetree Specification, available from:
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https://www.devicetree.org/specifications/
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with updates for 32-bit and 64-bit ARM systems provided in this document.
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================================
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Convention used in this document
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================================
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This document follows the conventions described in the Devicetree
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Specification, with the addition:
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- square brackets define bitfields, eg reg[7:0] value of the bitfield in
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the reg property contained in bits 7 down to 0
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=====================================
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cpus and cpu node bindings definition
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=====================================
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The ARM architecture, in accordance with the Devicetree Specification,
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requires the cpus and cpu nodes to be present and contain the properties
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described below.
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- cpus node
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Description: Container of cpu nodes
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The node name must be "cpus".
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A cpus node must define the following properties:
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- #address-cells
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Usage: required
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Value type: <u32>
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Definition depends on ARM architecture version and
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configuration:
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# On uniprocessor ARM architectures previous to v7
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value must be 1, to enable a simple enumeration
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scheme for processors that do not have a HW CPU
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identification register.
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# On 32-bit ARM 11 MPcore, ARM v7 or later systems
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value must be 1, that corresponds to CPUID/MPIDR
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registers sizes.
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# On ARM v8 64-bit systems value should be set to 2,
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that corresponds to the MPIDR_EL1 register size.
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If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
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in the system, #address-cells can be set to 1, since
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MPIDR_EL1[63:32] bits are not used for CPUs
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identification.
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- #size-cells
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Usage: required
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Value type: <u32>
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Definition: must be set to 0
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- cpu node
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Description: Describes a CPU in an ARM based system
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PROPERTIES
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- device_type
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Usage: required
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Value type: <string>
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Definition: must be "cpu"
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- reg
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Usage and definition depend on ARM architecture version and
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configuration:
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# On uniprocessor ARM architectures previous to v7
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this property is required and must be set to 0.
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# On ARM 11 MPcore based systems this property is
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required and matches the CPUID[11:0] register bits.
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Bits [11:0] in the reg cell must be set to
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bits [11:0] in CPU ID register.
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All other bits in the reg cell must be set to 0.
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# On 32-bit ARM v7 or later systems this property is
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required and matches the CPU MPIDR[23:0] register
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bits.
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Bits [23:0] in the reg cell must be set to
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bits [23:0] in MPIDR.
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All other bits in the reg cell must be set to 0.
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# On ARM v8 64-bit systems this property is required
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and matches the MPIDR_EL1 register affinity bits.
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* If cpus node's #address-cells property is set to 2
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The first reg cell bits [7:0] must be set to
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bits [39:32] of MPIDR_EL1.
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The second reg cell bits [23:0] must be set to
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bits [23:0] of MPIDR_EL1.
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* If cpus node's #address-cells property is set to 1
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The reg cell bits [23:0] must be set to bits [23:0]
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of MPIDR_EL1.
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All other bits in the reg cells must be set to 0.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: should be one of:
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"arm,arm710t"
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"arm,arm720t"
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"arm,arm740t"
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"arm,arm7ej-s"
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"arm,arm7tdmi"
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"arm,arm7tdmi-s"
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"arm,arm9es"
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"arm,arm9ej-s"
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"arm,arm920t"
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"arm,arm922t"
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"arm,arm925"
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"arm,arm926e-s"
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"arm,arm926ej-s"
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"arm,arm940t"
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"arm,arm946e-s"
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"arm,arm966e-s"
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"arm,arm968e-s"
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"arm,arm9tdmi"
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"arm,arm1020e"
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"arm,arm1020t"
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"arm,arm1022e"
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"arm,arm1026ej-s"
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"arm,arm1136j-s"
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"arm,arm1136jf-s"
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"arm,arm1156t2-s"
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"arm,arm1156t2f-s"
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"arm,arm1176jzf"
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"arm,arm1176jz-s"
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"arm,arm1176jzf-s"
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"arm,arm11mpcore"
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"arm,cortex-a5"
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"arm,cortex-a7"
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"arm,cortex-a8"
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"arm,cortex-a9"
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"arm,cortex-a12"
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"arm,cortex-a15"
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"arm,cortex-a17"
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"arm,cortex-a53"
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"arm,cortex-a57"
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"arm,cortex-a72"
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"arm,cortex-a73"
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"arm,cortex-m0"
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"arm,cortex-m0+"
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"arm,cortex-m1"
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"arm,cortex-m3"
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"arm,cortex-m4"
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"arm,cortex-r4"
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"arm,cortex-r5"
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"arm,cortex-r7"
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"brcm,brahma-b15"
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"brcm,brahma-b53"
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"brcm,vulcan"
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"cavium,thunder"
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"cavium,thunder2"
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"faraday,fa526"
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"intel,sa110"
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"intel,sa1100"
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"marvell,feroceon"
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"marvell,mohawk"
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"marvell,pj4a"
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"marvell,pj4b"
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"marvell,sheeva-v5"
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"nvidia,tegra132-denver"
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"nvidia,tegra186-denver"
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"nvidia,tegra194-carmel"
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"qcom,krait"
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"qcom,kryo"
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"qcom,kryo385"
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"qcom,scorpion"
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- enable-method
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Value type: <stringlist>
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Usage and definition depend on ARM architecture version.
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# On ARM v8 64-bit this property is required and must
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be one of:
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"psci"
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"spin-table"
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# On ARM 32-bit systems this property is optional and
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can be one of:
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"actions,s500-smp"
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"allwinner,sun6i-a31"
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"allwinner,sun8i-a23"
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"allwinner,sun9i-a80-smp"
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"amlogic,meson8-smp"
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"amlogic,meson8b-smp"
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"arm,realview-smp"
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"brcm,bcm11351-cpu-method"
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"brcm,bcm23550"
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"brcm,bcm2836-smp"
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"brcm,bcm-nsp-smp"
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"brcm,brahma-b15"
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"marvell,armada-375-smp"
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"marvell,armada-380-smp"
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"marvell,armada-390-smp"
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"marvell,armada-xp-smp"
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"marvell,98dx3236-smp"
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"mediatek,mt6589-smp"
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"mediatek,mt81xx-tz-smp"
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"qcom,gcc-msm8660"
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"qcom,kpss-acc-v1"
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"qcom,kpss-acc-v2"
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"renesas,apmu"
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"renesas,r9a06g032-smp"
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"rockchip,rk3036-smp"
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"rockchip,rk3066-smp"
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"ste,dbx500-smp"
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- cpu-release-addr
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Usage: required for systems that have an "enable-method"
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property value of "spin-table".
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Value type: <prop-encoded-array>
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Definition:
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# On ARM v8 64-bit systems must be a two cell
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property identifying a 64-bit zero-initialised
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memory location.
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- qcom,saw
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Usage: required for systems that have an "enable-method"
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property value of "qcom,kpss-acc-v1" or
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"qcom,kpss-acc-v2"
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Value type: <phandle>
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Definition: Specifies the SAW[1] node associated with this CPU.
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- qcom,acc
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Usage: required for systems that have an "enable-method"
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property value of "qcom,kpss-acc-v1" or
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"qcom,kpss-acc-v2"
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Value type: <phandle>
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Definition: Specifies the ACC[2] node associated with this CPU.
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- cpu-idle-states
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Usage: Optional
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Value type: <prop-encoded-array>
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Definition:
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# List of phandles to idle state nodes supported
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by this cpu [3].
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- capacity-dmips-mhz
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Usage: Optional
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Value type: <u32>
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Definition:
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# u32 value representing CPU capacity [4] in
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DMIPS/MHz, relative to highest capacity-dmips-mhz
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in the system.
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- rockchip,pmu
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Usage: optional for systems that have an "enable-method"
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property value of "rockchip,rk3066-smp"
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While optional, it is the preferred way to get access to
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the cpu-core power-domains.
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Value type: <phandle>
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Definition: Specifies the syscon node controlling the cpu core
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power domains.
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- dynamic-power-coefficient
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: A u32 value that represents the running time dynamic
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power coefficient in units of uW/MHz/V^2. The
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coefficient can either be calculated from power
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measurements or derived by analysis.
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The dynamic power consumption of the CPU is
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proportional to the square of the Voltage (V) and
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the clock frequency (f). The coefficient is used to
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calculate the dynamic power as below -
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Pdyn = dynamic-power-coefficient * V^2 * f
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where voltage is in V, frequency is in MHz.
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Example 1 (dual-cluster big.LITTLE system 32-bit):
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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};
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};
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Example 2 (Cortex-A8 uniprocessor 32-bit system):
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a8";
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reg = <0x0>;
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};
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};
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Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,arm926ej-s";
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reg = <0x0>;
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};
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};
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Example 4 (ARM Cortex-A57 64-bit system):
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cpus {
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#size-cells = <0>;
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#address-cells = <2>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x1>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x101>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@10000 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10000>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@10001 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10001>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@10100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@10101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x10101>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100000000 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100000001 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x1>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100000100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100000101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x101>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100010000 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x10000>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100010001 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x10001>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100010100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x10100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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cpu@100010101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1 0x10101>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x20000000>;
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};
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};
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--
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[1] arm/msm/qcom,saw2.txt
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[2] arm/msm/qcom,kpss-acc.txt
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[3] ARM Linux kernel documentation - idle states bindings
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Documentation/devicetree/bindings/arm/idle-states.txt
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[4] ARM Linux kernel documentation - cpu capacity bindings
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Documentation/devicetree/bindings/arm/cpu-capacity.txt
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507
Documentation/devicetree/bindings/arm/cpus.yaml
Normal file
507
Documentation/devicetree/bindings/arm/cpus.yaml
Normal file
@ -0,0 +1,507 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/cpus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ARM CPUs bindings
|
||||
|
||||
maintainers:
|
||||
- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
|
||||
description: |+
|
||||
The device tree allows to describe the layout of CPUs in a system through
|
||||
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
|
||||
defining properties for every cpu.
|
||||
|
||||
Bindings for CPU nodes follow the Devicetree Specification, available from:
|
||||
|
||||
https://www.devicetree.org/specifications/
|
||||
|
||||
with updates for 32-bit and 64-bit ARM systems provided in this document.
|
||||
|
||||
================================
|
||||
Convention used in this document
|
||||
================================
|
||||
|
||||
This document follows the conventions described in the Devicetree
|
||||
Specification, with the addition:
|
||||
|
||||
- square brackets define bitfields, eg reg[7:0] value of the bitfield in
|
||||
the reg property contained in bits 7 down to 0
|
||||
|
||||
=====================================
|
||||
cpus and cpu node bindings definition
|
||||
=====================================
|
||||
|
||||
The ARM architecture, in accordance with the Devicetree Specification,
|
||||
requires the cpus and cpu nodes to be present and contain the properties
|
||||
described below.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: cpus
|
||||
description: Container of cpu nodes
|
||||
|
||||
'#address-cells':
|
||||
enum: [1, 2]
|
||||
description: |
|
||||
Definition depends on ARM architecture version and configuration:
|
||||
|
||||
On uniprocessor ARM architectures previous to v7
|
||||
value must be 1, to enable a simple enumeration
|
||||
scheme for processors that do not have a HW CPU
|
||||
identification register.
|
||||
On 32-bit ARM 11 MPcore, ARM v7 or later systems
|
||||
value must be 1, that corresponds to CPUID/MPIDR
|
||||
registers sizes.
|
||||
On ARM v8 64-bit systems value should be set to 2,
|
||||
that corresponds to the MPIDR_EL1 register size.
|
||||
If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
|
||||
in the system, #address-cells can be set to 1, since
|
||||
MPIDR_EL1[63:32] bits are not used for CPUs
|
||||
identification.
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
'^cpu@[0-9a-f]+$':
|
||||
properties:
|
||||
device_type:
|
||||
const: cpu
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: |
|
||||
Usage and definition depend on ARM architecture version and
|
||||
configuration:
|
||||
|
||||
On uniprocessor ARM architectures previous to v7
|
||||
this property is required and must be set to 0.
|
||||
|
||||
On ARM 11 MPcore based systems this property is
|
||||
required and matches the CPUID[11:0] register bits.
|
||||
|
||||
Bits [11:0] in the reg cell must be set to
|
||||
bits [11:0] in CPU ID register.
|
||||
|
||||
All other bits in the reg cell must be set to 0.
|
||||
|
||||
On 32-bit ARM v7 or later systems this property is
|
||||
required and matches the CPU MPIDR[23:0] register
|
||||
bits.
|
||||
|
||||
Bits [23:0] in the reg cell must be set to
|
||||
bits [23:0] in MPIDR.
|
||||
|
||||
All other bits in the reg cell must be set to 0.
|
||||
|
||||
On ARM v8 64-bit systems this property is required
|
||||
and matches the MPIDR_EL1 register affinity bits.
|
||||
|
||||
* If cpus node's #address-cells property is set to 2
|
||||
|
||||
The first reg cell bits [7:0] must be set to
|
||||
bits [39:32] of MPIDR_EL1.
|
||||
|
||||
The second reg cell bits [23:0] must be set to
|
||||
bits [23:0] of MPIDR_EL1.
|
||||
|
||||
* If cpus node's #address-cells property is set to 1
|
||||
|
||||
The reg cell bits [23:0] must be set to bits [23:0]
|
||||
of MPIDR_EL1.
|
||||
|
||||
All other bits in the reg cells must be set to 0.
|
||||
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- arm,arm710t
|
||||
- arm,arm720t
|
||||
- arm,arm740t
|
||||
- arm,arm7ej-s
|
||||
- arm,arm7tdmi
|
||||
- arm,arm7tdmi-s
|
||||
- arm,arm9es
|
||||
- arm,arm9ej-s
|
||||
- arm,arm920t
|
||||
- arm,arm922t
|
||||
- arm,arm925
|
||||
- arm,arm926e-s
|
||||
- arm,arm926ej-s
|
||||
- arm,arm940t
|
||||
- arm,arm946e-s
|
||||
- arm,arm966e-s
|
||||
- arm,arm968e-s
|
||||
- arm,arm9tdmi
|
||||
- arm,arm1020e
|
||||
- arm,arm1020t
|
||||
- arm,arm1022e
|
||||
- arm,arm1026ej-s
|
||||
- arm,arm1136j-s
|
||||
- arm,arm1136jf-s
|
||||
- arm,arm1156t2-s
|
||||
- arm,arm1156t2f-s
|
||||
- arm,arm1176jzf
|
||||
- arm,arm1176jz-s
|
||||
- arm,arm1176jzf-s
|
||||
- arm,arm11mpcore
|
||||
- arm,armv8 # Only for s/w models
|
||||
- arm,cortex-a5
|
||||
- arm,cortex-a7
|
||||
- arm,cortex-a8
|
||||
- arm,cortex-a9
|
||||
- arm,cortex-a12
|
||||
- arm,cortex-a15
|
||||
- arm,cortex-a17
|
||||
- arm,cortex-a53
|
||||
- arm,cortex-a57
|
||||
- arm,cortex-a72
|
||||
- arm,cortex-a73
|
||||
- arm,cortex-m0
|
||||
- arm,cortex-m0+
|
||||
- arm,cortex-m1
|
||||
- arm,cortex-m3
|
||||
- arm,cortex-m4
|
||||
- arm,cortex-r4
|
||||
- arm,cortex-r5
|
||||
- arm,cortex-r7
|
||||
- brcm,brahma-b15
|
||||
- brcm,brahma-b53
|
||||
- brcm,vulcan
|
||||
- cavium,thunder
|
||||
- cavium,thunder2
|
||||
- faraday,fa526
|
||||
- intel,sa110
|
||||
- intel,sa1100
|
||||
- marvell,feroceon
|
||||
- marvell,mohawk
|
||||
- marvell,pj4a
|
||||
- marvell,pj4b
|
||||
- marvell,sheeva-v5
|
||||
- marvell,sheeva-v7
|
||||
- nvidia,tegra132-denver
|
||||
- nvidia,tegra186-denver
|
||||
- nvidia,tegra194-carmel
|
||||
- qcom,krait
|
||||
- qcom,kryo
|
||||
- qcom,kryo385
|
||||
- qcom,scorpion
|
||||
|
||||
enable-method:
|
||||
allOf:
|
||||
- $ref: '/schemas/types.yaml#/definitions/string'
|
||||
- oneOf:
|
||||
# On ARM v8 64-bit this property is required
|
||||
- enum:
|
||||
- psci
|
||||
- spin-table
|
||||
# On ARM 32-bit systems this property is optional
|
||||
- enum:
|
||||
- actions,s500-smp
|
||||
- allwinner,sun6i-a31
|
||||
- allwinner,sun8i-a23
|
||||
- allwinner,sun9i-a80-smp
|
||||
- allwinner,sun8i-a83t-smp
|
||||
- amlogic,meson8-smp
|
||||
- amlogic,meson8b-smp
|
||||
- arm,realview-smp
|
||||
- brcm,bcm11351-cpu-method
|
||||
- brcm,bcm23550
|
||||
- brcm,bcm2836-smp
|
||||
- brcm,bcm63138
|
||||
- brcm,bcm-nsp-smp
|
||||
- brcm,brahma-b15
|
||||
- marvell,armada-375-smp
|
||||
- marvell,armada-380-smp
|
||||
- marvell,armada-390-smp
|
||||
- marvell,armada-xp-smp
|
||||
- marvell,98dx3236-smp
|
||||
- mediatek,mt6589-smp
|
||||
- mediatek,mt81xx-tz-smp
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,kpss-acc-v1
|
||||
- qcom,kpss-acc-v2
|
||||
- renesas,apmu
|
||||
- renesas,r9a06g032-smp
|
||||
- rockchip,rk3036-smp
|
||||
- rockchip,rk3066-smp
|
||||
- ste,dbx500-smp
|
||||
|
||||
cpu-release-addr:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint64'
|
||||
|
||||
description:
|
||||
Required for systems that have an "enable-method"
|
||||
property value of "spin-table".
|
||||
On ARM v8 64-bit systems must be a two cell
|
||||
property identifying a 64-bit zero-initialised
|
||||
memory location.
|
||||
|
||||
cpu-idle-states:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle-array'
|
||||
description: |
|
||||
List of phandles to idle state nodes supported
|
||||
by this cpu (see ./idle-states.txt).
|
||||
|
||||
capacity-dmips-mhz:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description:
|
||||
u32 value representing CPU capacity (see ./cpu-capacity.txt) in
|
||||
DMIPS/MHz, relative to highest capacity-dmips-mhz
|
||||
in the system.
|
||||
|
||||
dynamic-power-coefficient:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint32'
|
||||
description:
|
||||
A u32 value that represents the running time dynamic
|
||||
power coefficient in units of uW/MHz/V^2. The
|
||||
coefficient can either be calculated from power
|
||||
measurements or derived by analysis.
|
||||
|
||||
The dynamic power consumption of the CPU is
|
||||
proportional to the square of the Voltage (V) and
|
||||
the clock frequency (f). The coefficient is used to
|
||||
calculate the dynamic power as below -
|
||||
|
||||
Pdyn = dynamic-power-coefficient * V^2 * f
|
||||
|
||||
where voltage is in V, frequency is in MHz.
|
||||
|
||||
qcom,saw:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: |
|
||||
Specifies the SAW* node associated with this CPU.
|
||||
|
||||
Required for systems that have an "enable-method" property
|
||||
value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
|
||||
|
||||
* arm/msm/qcom,saw2.txt
|
||||
|
||||
qcom,acc:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: |
|
||||
Specifies the ACC* node associated with this CPU.
|
||||
|
||||
Required for systems that have an "enable-method" property
|
||||
value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
|
||||
|
||||
* arm/msm/qcom,kpss-acc.txt
|
||||
|
||||
rockchip,pmu:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: |
|
||||
Specifies the syscon node controlling the cpu core power domains.
|
||||
|
||||
Optional for systems that have an "enable-method"
|
||||
property value of "rockchip,rk3066-smp"
|
||||
While optional, it is the preferred way to get access to
|
||||
the cpu-core power-domains.
|
||||
|
||||
required:
|
||||
- device_type
|
||||
- reg
|
||||
- compatible
|
||||
|
||||
dependencies:
|
||||
cpu-release-addr: [enable-method]
|
||||
rockchip,pmu: [enable-method]
|
||||
|
||||
required:
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x101>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// Example 2 (Cortex-A8 uniprocessor 32-bit system):
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a8";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,arm926ej-s";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
// Example 4 (ARM Cortex-A57 64-bit system):
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <2>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10000>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10001>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@10101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0 0x10101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x0>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x1>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100000101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010000 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10000>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010001 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10001>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10100>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
|
||||
cpu@100010101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1 0x10101>;
|
||||
enable-method = "spin-table";
|
||||
cpu-release-addr = <0 0x20000000>;
|
||||
};
|
||||
};
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user