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drm/radeon: avivo chips have no separate int bit for display

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display interrupts are not enabled via this register, the
DISPLAY_INT bit is a status only to show that other regs
need to be read.

Noticed by Alex Deucher

Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2009-09-18 14:31:48 +10:00
parent b15591f312
commit 65cb15a686
1 changed files with 0 additions and 2 deletions
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2
drivers/gpu/drm/radeon/rs600.c
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@ -272,11 +272,9 @@ int rs600_irq_set(struct radeon_device *rdev)
tmp |= RADEON_SW_INT_ENABLE; tmp |= RADEON_SW_INT_ENABLE;
} }
if (rdev->irq.crtc_vblank_int[0]) { if (rdev->irq.crtc_vblank_int[0]) {
tmp |= AVIVO_DISPLAY_INT_STATUS;
mode_int |= AVIVO_D1MODE_INT_MASK; mode_int |= AVIVO_D1MODE_INT_MASK;
} }
if (rdev->irq.crtc_vblank_int[1]) { if (rdev->irq.crtc_vblank_int[1]) {
tmp |= AVIVO_DISPLAY_INT_STATUS;
mode_int |= AVIVO_D2MODE_INT_MASK; mode_int |= AVIVO_D2MODE_INT_MASK;
} }
WREG32(RADEON_GEN_INT_CNTL, tmp); WREG32(RADEON_GEN_INT_CNTL, tmp);