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drm/nouveau/fifo: add engine_id hook

Browse Source 
Will be used by common code in subsequent commits to replace arrays
indexed by subdev index.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2021-02-06 18:41:07 +10:00
parent ab0db2bd85
commit 64f7c698be
15 changed files with 125 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c
View File

@ -44,26 +44,6 @@ g84_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type,
return -EINVAL;
}
static int
g84_fifo_chan_engine(struct nvkm_engine *engine)
{
switch (engine->subdev.index) {
case NVKM_ENGINE_GR : return 0;
case NVKM_ENGINE_MPEG :
case NVKM_ENGINE_MSPPP : return 1;
case NVKM_ENGINE_CE0 : return 2;
case NVKM_ENGINE_VP :
case NVKM_ENGINE_MSPDEC: return 3;
case NVKM_ENGINE_CIPHER:
case NVKM_ENGINE_SEC : return 4;
case NVKM_ENGINE_BSP :
case NVKM_ENGINE_MSVLD : return 5;
default:
WARN_ON(1);
return 0;
}
}
static int
g84_fifo_chan_engine_addr(struct nvkm_engine *engine)
{
@ -102,7 +82,7 @@ g84_fifo_chan_engine_fini(struct nvkm_fifo_chan *base,
if (offset < 0)
return 0;
engn = g84_fifo_chan_engine(engine);
engn = fifo->base.func->engine_id(&fifo->base, engine);
save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn);
nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12);
done = nvkm_msec(device, 2000,

9
drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h
View File

@ -12,7 +12,14 @@ struct gf100_fifo_chan {
struct list_head head;
bool killed;
struct {
#define GF100_FIFO_ENGN_GR 0
#define GF100_FIFO_ENGN_MSPDEC 1
#define GF100_FIFO_ENGN_MSPPP 2
#define GF100_FIFO_ENGN_MSVLD 3
#define GF100_FIFO_ENGN_CE0 4
#define GF100_FIFO_ENGN_CE1 5
#define GF100_FIFO_ENGN_SW 15
struct gf100_fifo_engn {
struct nvkm_gpuobj *inst;
struct nvkm_vma *vma;
} engn[NVKM_SUBDEV_NR];

3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h
View File

@ -16,7 +16,8 @@ struct gk104_fifo_chan {
struct nvkm_memory *mthd;
struct {
#define GK104_FIFO_ENGN_SW 15
struct gk104_fifo_engn {
struct nvkm_gpuobj *inst;
struct nvkm_vma *vma;
} engn[NVKM_SUBDEV_NR];

4
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h
View File

@ -9,6 +9,10 @@ struct nv04_fifo_chan {
struct nvkm_fifo_chan base;
struct nv04_fifo *fifo;
u32 ramfc;
#define NV04_FIFO_ENGN_SW 0
#define NV04_FIFO_ENGN_GR 1
#define NV04_FIFO_ENGN_MPEG 2
#define NV04_FIFO_ENGN_DMA 3
struct nvkm_gpuobj *engn[NVKM_SUBDEV_NR];
};

19
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h
View File

@ -15,6 +15,25 @@ struct nv50_fifo_chan {
struct nvkm_gpuobj *pgd;
struct nvkm_ramht *ramht;
#define NV50_FIFO_ENGN_SW 0
#define NV50_FIFO_ENGN_GR 1
#define NV50_FIFO_ENGN_MPEG 2
#define NV50_FIFO_ENGN_DMA 3
#define G84_FIFO_ENGN_SW 0
#define G84_FIFO_ENGN_GR 1
#define G84_FIFO_ENGN_MPEG 2
#define G84_FIFO_ENGN_MSPPP 2
#define G84_FIFO_ENGN_ME 3
#define G84_FIFO_ENGN_CE0 3
#define G84_FIFO_ENGN_VP 4
#define G84_FIFO_ENGN_MSPDEC 4
#define G84_FIFO_ENGN_CIPHER 5
#define G84_FIFO_ENGN_SEC 5
#define G84_FIFO_ENGN_VIC 5
#define G84_FIFO_ENGN_BSP 6
#define G84_FIFO_ENGN_MSVLD 6
#define G84_FIFO_ENGN_DMA 7
struct nvkm_gpuobj *engn[NVKM_SUBDEV_NR];
};

23
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
View File

@ -38,12 +38,35 @@ g84_fifo_uevent_init(struct nvkm_fifo *fifo)
nvkm_mask(device, 0x002140, 0x40000000, 0x40000000);
}
static int
g84_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine)
{
switch (engine->subdev.type) {
case NVKM_ENGINE_SW : return G84_FIFO_ENGN_SW;
case NVKM_ENGINE_GR : return G84_FIFO_ENGN_GR;
case NVKM_ENGINE_MPEG :
case NVKM_ENGINE_MSPPP : return G84_FIFO_ENGN_MPEG;
case NVKM_ENGINE_CE : return G84_FIFO_ENGN_CE0;
case NVKM_ENGINE_VP :
case NVKM_ENGINE_MSPDEC: return G84_FIFO_ENGN_VP;
case NVKM_ENGINE_CIPHER:
case NVKM_ENGINE_SEC : return G84_FIFO_ENGN_CIPHER;
case NVKM_ENGINE_BSP :
case NVKM_ENGINE_MSVLD : return G84_FIFO_ENGN_BSP;
case NVKM_ENGINE_DMAOBJ: return G84_FIFO_ENGN_DMA;
default:
WARN_ON(1);
return -1;
}
}
static const struct nvkm_fifo_func
g84_fifo = {
.dtor = nv50_fifo_dtor,
.oneinit = nv50_fifo_oneinit,
.init = nv50_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = g84_fifo_engine_id,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.uevent_init = g84_fifo_uevent_init,

41
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
View File

@ -105,23 +105,6 @@ gf100_fifo_runlist_insert(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan)
mutex_unlock(&fifo->base.mutex);
}
static inline int
gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn)
{
switch (engn) {
case NVKM_ENGINE_GR : engn = 0; break;
case NVKM_ENGINE_MSVLD : engn = 1; break;
case NVKM_ENGINE_MSPPP : engn = 2; break;
case NVKM_ENGINE_MSPDEC: engn = 3; break;
case NVKM_ENGINE_CE0 : engn = 4; break;
case NVKM_ENGINE_CE1 : engn = 5; break;
default:
return -1;
}
return engn;
}
static inline struct nvkm_engine *
gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn)
{
@ -141,6 +124,22 @@ gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn)
return nvkm_device_engine(device, engn, 0);
}
static int
gf100_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine)
{
switch (engine->subdev.type) {
case NVKM_ENGINE_GR : return GF100_FIFO_ENGN_GR;
case NVKM_ENGINE_MSPDEC: return GF100_FIFO_ENGN_MSPDEC;
case NVKM_ENGINE_MSPPP : return GF100_FIFO_ENGN_MSPPP;
case NVKM_ENGINE_MSVLD : return GF100_FIFO_ENGN_MSVLD;
case NVKM_ENGINE_CE : return GF100_FIFO_ENGN_CE0 + engine->subdev.inst;
case NVKM_ENGINE_SW : return GF100_FIFO_ENGN_SW;
default:
WARN_ON(1);
return -1;
}
}
static void
gf100_fifo_recover_work(struct work_struct *w)
{
@ -156,8 +155,11 @@ gf100_fifo_recover_work(struct work_struct *w)
fifo->recover.mask = 0ULL;
spin_unlock_irqrestore(&fifo->base.lock, flags);
for (todo = mask; engn = __ffs64(todo), todo; todo &= ~BIT_ULL(engn))
engm |= 1 << gf100_fifo_engidx(fifo, engn);
for (todo = mask; engn = __ffs64(todo), todo; todo &= ~BIT_ULL(engn)) {
if (!(engine = nvkm_device_engine(device, engn, 0)))
continue;
engm |= 1 << gf100_fifo_engine_id(&fifo->base, engine);
}
nvkm_mask(device, 0x002630, engm, engm);
for (todo = mask; engn = __ffs64(todo), todo; todo &= ~BIT_ULL(engn)) {
@ -673,6 +675,7 @@ gf100_fifo = {
.fini = gf100_fifo_fini,
.intr = gf100_fifo_intr,
.fault = gf100_fifo_fault,
.engine_id = gf100_fifo_engine_id,
.uevent_init = gf100_fifo_uevent_init,
.uevent_fini = gf100_fifo_uevent_fini,
.chan = {

27
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
View File

@ -258,6 +258,24 @@ gk104_fifo_pbdma = {
.init = gk104_fifo_pbdma_init,
};
int
gk104_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine)
{
struct gk104_fifo *fifo = gk104_fifo(base);
int engn;
if (engine->subdev.type == NVKM_ENGINE_SW)
return GK104_FIFO_ENGN_SW;
for (engn = 0; engn < fifo->engine_nr && engine; engn++) {
if (fifo->engine[engn].engine == engine)
return engn;
}
WARN_ON(1);
return -1;
}
static void
gk104_fifo_recover_work(struct work_struct *w)
{
@ -459,7 +477,6 @@ gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info)
struct nvkm_fifo_chan *chan;
unsigned long flags;
char ct[8] = "HUB/", en[16] = "";
int engn;
er = nvkm_enum_find(fifo->func->fault.reason, info->reason);
ee = nvkm_enum_find(fifo->func->fault.engine, info->engine);
@ -522,11 +539,10 @@ gk104_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info)
* correct engine(s), but just in case we can't find the channel
* information...
*/
for (engn = 0; engn < fifo->engine_nr && engine; engn++) {
if (fifo->engine[engn].engine == engine) {
if (engine) {
int engn = fifo->base.func->engine_id(&fifo->base, engine);
if (engn >= 0 && engn != GK104_FIFO_ENGN_SW)
gk104_fifo_recover_engn(fifo, engn);
break;
}
}
spin_unlock_irqrestore(&fifo->base.lock, flags);
@ -1020,6 +1036,7 @@ gk104_fifo_ = {
.fini = gk104_fifo_fini,
.intr = gk104_fifo_intr,
.fault = gk104_fifo_fault,
.engine_id = gk104_fifo_engine_id,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk104_fifo_uevent_fini,
.recover_chan = gk104_fifo_recover_chan,

15
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
View File

@ -94,6 +94,20 @@ __releases(fifo->base.lock)
spin_unlock_irqrestore(&fifo->base.lock, flags);
}
int
nv04_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine)
{
switch (engine->subdev.type) {
case NVKM_ENGINE_SW : return NV04_FIFO_ENGN_SW;
case NVKM_ENGINE_GR : return NV04_FIFO_ENGN_GR;
case NVKM_ENGINE_MPEG : return NV04_FIFO_ENGN_MPEG;
case NVKM_ENGINE_DMAOBJ: return NV04_FIFO_ENGN_DMA;
default:
WARN_ON(1);
return 0;
}
}
static const char *
nv_dma_state_err(u32 state)
{
@ -349,6 +363,7 @@ static const struct nvkm_fifo_func
nv04_fifo = {
.init = nv04_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.chan = {

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
View File

@ -43,6 +43,7 @@ static const struct nvkm_fifo_func
nv10_fifo = {
.init = nv04_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.chan = {

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
View File

@ -81,6 +81,7 @@ static const struct nvkm_fifo_func
nv17_fifo = {
.init = nv17_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.chan = {

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
View File

@ -112,6 +112,7 @@ static const struct nvkm_fifo_func
nv40_fifo = {
.init = nv40_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.chan = {

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
View File

@ -131,6 +131,7 @@ nv50_fifo = {
.oneinit = nv50_fifo_oneinit,
.init = nv50_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.chan = {

4
drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h
View File

@ -23,6 +23,7 @@ struct nvkm_fifo_func {
void (*fini)(struct nvkm_fifo *);
void (*intr)(struct nvkm_fifo *);
void (*fault)(struct nvkm_fifo *, struct nvkm_fault_data *);
int (*engine_id)(struct nvkm_fifo *, struct nvkm_engine *);
void (*pause)(struct nvkm_fifo *, unsigned long *);
void (*start)(struct nvkm_fifo *, unsigned long *);
void (*uevent_init)(struct nvkm_fifo *);
@ -35,8 +36,11 @@ struct nvkm_fifo_func {
};
void nv04_fifo_intr(struct nvkm_fifo *);
int nv04_fifo_engine_id(struct nvkm_fifo *, struct nvkm_engine *);
void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *);
void nv04_fifo_start(struct nvkm_fifo *, unsigned long *);
void gf100_fifo_intr_fault(struct nvkm_fifo *, int);
int gk104_fifo_engine_id(struct nvkm_fifo *, struct nvkm_engine *);
#endif

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c
View File

@ -456,6 +456,7 @@ tu102_fifo_ = {
.fini = gk104_fifo_fini,
.intr = tu102_fifo_intr,
.fault = tu102_fifo_fault,
.engine_id = gk104_fifo_engine_id,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk104_fifo_uevent_fini,
.recover_chan = tu102_fifo_recover_chan,