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pinctrl-sx150x: Replace sx150x_*_cfg by means of regmap API
The difference between 8 and 16 pin GPIO expanders can be accomodated by the means of regmap API without resorting to using driver-specific read/write accessors. This change, IMHO, brings the following benefits: - Replaces driver's idiosyncratic way of dealing with mult-register fields with regmap API, which, hopefuly, makes the code a bit easier for a new reader to understand - Removes various multi-read for-loop register read logic from various places in the code and puts it in a signle place - Removes ad-hoc IRQ register caching code in sx150x_irq_bus_sync_unlock, since that functionality is provided by regmap Besided aforementioned benefits this change also implements necessary RegSense byte swap necessary for SX1503 and SX1506 variants of the chip. Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Andrey Smirnov
Linus Walleij
parent
0db0f26c2c
commit
6489677f86
@ -106,11 +106,8 @@ struct sx150x_pinctrl {
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struct irq_chip irq_chip;
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struct regmap *regmap;
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struct {
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int update;
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u32 sense;
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u32 masked;
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u32 dev_sense;
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u32 dev_masked;
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} irq;
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struct mutex lock;
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const struct sx150x_device_data *data;
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@ -171,16 +168,16 @@ static const struct sx150x_device_data sx1508q_device_data = {
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static const struct sx150x_device_data sx1509q_device_data = {
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.model = SX150X_789,
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.reg_pullup = 0x07,
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.reg_pulldn = 0x09,
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.reg_dir = 0x0f,
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.reg_data = 0x11,
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.reg_irq_mask = 0x13,
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.reg_irq_src = 0x19,
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.reg_sense = 0x17,
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.reg_pullup = 0x06,
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.reg_pulldn = 0x08,
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.reg_dir = 0x0e,
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.reg_data = 0x10,
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.reg_irq_mask = 0x12,
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.reg_irq_src = 0x18,
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.reg_sense = 0x14,
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.pri.x789 = {
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.reg_drain = 0x0b,
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.reg_polarity = 0x0d,
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.reg_drain = 0x0a,
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.reg_polarity = 0x0c,
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.reg_clock = 0x1e,
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.reg_misc = 0x1f,
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.reg_reset = 0x7d,
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@ -192,20 +189,20 @@ static const struct sx150x_device_data sx1509q_device_data = {
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static const struct sx150x_device_data sx1506q_device_data = {
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.model = SX150X_456,
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.reg_pullup = 0x05,
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.reg_pulldn = 0x07,
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.reg_dir = 0x03,
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.reg_data = 0x01,
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.reg_irq_mask = 0x09,
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.reg_irq_src = 0x0f,
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.reg_sense = 0x0d,
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.reg_pullup = 0x04,
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.reg_pulldn = 0x06,
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.reg_dir = 0x02,
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.reg_data = 0x00,
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.reg_irq_mask = 0x08,
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.reg_irq_src = 0x0e,
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.reg_sense = 0x0a,
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.pri.x456 = {
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.reg_pld_mode = 0x21,
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.reg_pld_table0 = 0x23,
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.reg_pld_table1 = 0x25,
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.reg_pld_table2 = 0x27,
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.reg_pld_table3 = 0x29,
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.reg_pld_table4 = 0x2b,
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.reg_pld_mode = 0x20,
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.reg_pld_table0 = 0x22,
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.reg_pld_table1 = 0x24,
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.reg_pld_table2 = 0x26,
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.reg_pld_table3 = 0x28,
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.reg_pld_table4 = 0x2a,
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.reg_advance = 0xad,
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},
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.ngpios = 16,
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@ -238,20 +235,20 @@ static const struct sx150x_device_data sx1502q_device_data = {
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static const struct sx150x_device_data sx1503q_device_data = {
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.model = SX150X_123,
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.reg_pullup = 0x05,
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.reg_pulldn = 0x07,
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.reg_dir = 0x03,
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.reg_data = 0x01,
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.reg_irq_mask = 0x09,
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.reg_irq_src = 0x0f,
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.reg_sense = 0x07,
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.reg_pullup = 0x04,
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.reg_pulldn = 0x06,
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.reg_dir = 0x02,
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.reg_data = 0x00,
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.reg_irq_mask = 0x08,
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.reg_irq_src = 0x0e,
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.reg_sense = 0x0a,
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.pri.x123 = {
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.reg_pld_mode = 0x10,
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.reg_pld_table0 = 0x11,
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.reg_pld_table1 = 0x12,
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.reg_pld_table2 = 0x13,
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.reg_pld_table3 = 0x14,
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.reg_pld_table4 = 0x15,
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.reg_pld_mode = 0x20,
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.reg_pld_table0 = 0x22,
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.reg_pld_table1 = 0x24,
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.reg_pld_table2 = 0x26,
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.reg_pld_table3 = 0x28,
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.reg_pld_table4 = 0x2a,
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.reg_advance = 0xad,
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},
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.ngpios = 16,
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@ -259,70 +256,6 @@ static const struct sx150x_device_data sx1503q_device_data = {
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.npins = 16, /* oscio not available */
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};
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/*
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* These utility functions solve the common problem of locating and setting
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* configuration bits. Configuration bits are grouped into registers
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* whose indexes increase downwards. For example, with eight-bit registers,
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* sixteen gpios would have their config bits grouped in the following order:
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* REGISTER N-1 [ f e d c b a 9 8 ]
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* N [ 7 6 5 4 3 2 1 0 ]
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*
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* For multi-bit configurations, the pattern gets wider:
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* REGISTER N-3 [ f f e e d d c c ]
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* N-2 [ b b a a 9 9 8 8 ]
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* N-1 [ 7 7 6 6 5 5 4 4 ]
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* N [ 3 3 2 2 1 1 0 0 ]
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*
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* Given the address of the starting register 'N', the index of the gpio
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* whose configuration we seek to change, and the width in bits of that
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* configuration, these functions allow us to locate the correct
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* register and mask the correct bits.
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*/
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static inline void sx150x_find_cfg(u8 offset, u8 width,
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u8 *reg, u8 *mask, u8 *shift)
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{
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*reg -= offset * width / 8;
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*mask = (1 << width) - 1;
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*shift = (offset * width) % 8;
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*mask <<= *shift;
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}
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static int sx150x_write_cfg(struct i2c_client *client,
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u8 offset, u8 width, u8 reg, u8 val)
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{
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u8 mask;
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unsigned int data;
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u8 shift;
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int err;
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struct sx150x_pinctrl *pctl = i2c_get_clientdata(client);
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sx150x_find_cfg(offset, width, ®, &mask, &shift);
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err = regmap_read(pctl->regmap, reg, &data);
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if (err < 0)
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return err;
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data &= ~mask;
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data |= (val << shift) & mask;
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return regmap_write(pctl->regmap, reg, data);
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}
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static int sx150x_read_cfg(struct i2c_client *client,
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u8 offset, u8 width, u8 reg)
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{
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u8 mask;
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unsigned int data;
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u8 shift;
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int err;
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struct sx150x_pinctrl *pctl = i2c_get_clientdata(client);
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sx150x_find_cfg(offset, width, ®, &mask, &shift);
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err = regmap_read(pctl->regmap, reg, &data);
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if (err < 0)
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return err;
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return (data & mask);
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}
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static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
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{
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return 0;
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@ -368,31 +301,33 @@ static int sx150x_gpio_get_direction(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
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int status;
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unsigned int value;
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int ret;
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if (sx150x_pin_is_oscio(pctl, offset))
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return false;
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status = sx150x_read_cfg(pctl->client, offset, 1, pctl->data->reg_dir);
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if (status >= 0)
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status = !!status;
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ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
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if (ret < 0)
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return ret;
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return status;
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return !!(value & BIT(offset));
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}
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static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
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int status;
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unsigned int value;
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int ret;
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if (sx150x_pin_is_oscio(pctl, offset))
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return -EINVAL;
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status = sx150x_read_cfg(pctl->client, offset, 1, pctl->data->reg_data);
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if (status >= 0)
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status = !!status;
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ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value);
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if (ret < 0)
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return ret;
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return status;
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return !!(value & BIT(offset));
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}
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static int sx150x_gpio_set_single_ended(struct gpio_chip *chip,
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@ -409,9 +344,9 @@ static int sx150x_gpio_set_single_ended(struct gpio_chip *chip,
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return 0;
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mutex_lock(&pctl->lock);
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ret = sx150x_write_cfg(pctl->client, offset, 1,
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pctl->data->pri.x789.reg_drain,
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0);
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ret = regmap_write_bits(pctl->regmap,
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pctl->data->pri.x789.reg_drain,
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BIT(offset), 0);
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mutex_unlock(&pctl->lock);
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if (ret < 0)
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return ret;
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@ -423,9 +358,9 @@ static int sx150x_gpio_set_single_ended(struct gpio_chip *chip,
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return -ENOTSUPP;
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mutex_lock(&pctl->lock);
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ret = sx150x_write_cfg(pctl->client, offset, 1,
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pctl->data->pri.x789.reg_drain,
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1);
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ret = regmap_write_bits(pctl->regmap,
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pctl->data->pri.x789.reg_drain,
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BIT(offset), BIT(offset));
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mutex_unlock(&pctl->lock);
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if (ret < 0)
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return ret;
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@ -438,6 +373,13 @@ static int sx150x_gpio_set_single_ended(struct gpio_chip *chip,
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return 0;
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}
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static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset,
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int value)
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{
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return regmap_write_bits(pctl->regmap, pctl->data->reg_data,
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BIT(offset), value ? BIT(offset) : 0);
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}
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static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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@ -451,9 +393,7 @@ static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
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mutex_unlock(&pctl->lock);
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} else {
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mutex_lock(&pctl->lock);
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sx150x_write_cfg(pctl->client, offset, 1,
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pctl->data->reg_data,
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(value ? 1 : 0));
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__sx150x_gpio_set(pctl, offset, value);
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mutex_unlock(&pctl->lock);
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}
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}
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@ -468,8 +408,9 @@ static int sx150x_gpio_direction_input(struct gpio_chip *chip,
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return -EINVAL;
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mutex_lock(&pctl->lock);
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ret = sx150x_write_cfg(pctl->client, offset, 1,
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pctl->data->reg_dir, 1);
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ret = regmap_write_bits(pctl->regmap,
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pctl->data->reg_dir,
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BIT(offset), BIT(offset));
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mutex_unlock(&pctl->lock);
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return ret;
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@ -487,12 +428,11 @@ static int sx150x_gpio_direction_output(struct gpio_chip *chip,
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}
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mutex_lock(&pctl->lock);
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status = sx150x_write_cfg(pctl->client, offset, 1,
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pctl->data->reg_data,
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(value ? 1 : 0));
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status = __sx150x_gpio_set(pctl, offset, value);
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if (status >= 0)
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status = sx150x_write_cfg(pctl->client, offset, 1,
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pctl->data->reg_dir, 0);
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status = regmap_write_bits(pctl->regmap,
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pctl->data->reg_dir,
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BIT(offset), 0);
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mutex_unlock(&pctl->lock);
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return status;
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@ -504,8 +444,7 @@ static void sx150x_irq_mask(struct irq_data *d)
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gpiochip_get_data(irq_data_get_irq_chip_data(d));
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unsigned int n = d->hwirq;
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pctl->irq.masked |= (1 << n);
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pctl->irq.update = n;
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pctl->irq.masked |= BIT(n);
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}
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static void sx150x_irq_unmask(struct irq_data *d)
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@ -514,8 +453,7 @@ static void sx150x_irq_unmask(struct irq_data *d)
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gpiochip_get_data(irq_data_get_irq_chip_data(d));
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unsigned int n = d->hwirq;
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pctl->irq.masked &= ~(1 << n);
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pctl->irq.update = n;
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pctl->irq.masked &= ~BIT(n);
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}
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static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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@ -536,7 +474,6 @@ static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
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pctl->irq.sense &= ~(3UL << (n * 2));
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pctl->irq.sense |= val << (n * 2);
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pctl->irq.update = n;
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return 0;
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}
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@ -548,29 +485,20 @@ static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
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unsigned int n;
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s32 err;
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unsigned int val;
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int i;
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for (i = (pctl->data->ngpios / 8) - 1; i >= 0; --i) {
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err = regmap_read(pctl->regmap,
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pctl->data->reg_irq_src - i,
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&val);
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if (err < 0)
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continue;
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err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val);
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if (err < 0)
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return IRQ_NONE;
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err = regmap_write(pctl->regmap,
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pctl->data->reg_irq_src - i,
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val);
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if (err < 0)
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continue;
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err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val);
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if (err < 0)
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return IRQ_NONE;
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for (n = 0; n < 8; ++n) {
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if (val & (1 << n)) {
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sub_irq = irq_find_mapping(
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pctl->gpio.irqdomain,
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(i * 8) + n);
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handle_nested_irq(sub_irq);
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++nhandled;
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}
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for (n = 0; n < pctl->data->ngpios; ++n) {
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if (val & BIT(n)) {
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sub_irq = irq_find_mapping(pctl->gpio.irqdomain, n);
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handle_nested_irq(sub_irq);
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++nhandled;
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}
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}
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@ -589,35 +517,9 @@ static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
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{
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struct sx150x_pinctrl *pctl =
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gpiochip_get_data(irq_data_get_irq_chip_data(d));
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unsigned int n;
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if (pctl->irq.update < 0)
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goto out;
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n = pctl->irq.update;
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pctl->irq.update = -1;
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/* Avoid updates if nothing changed */
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if (pctl->irq.dev_sense == pctl->irq.sense &&
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pctl->irq.dev_masked == pctl->irq.masked)
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goto out;
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pctl->irq.dev_sense = pctl->irq.sense;
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pctl->irq.dev_masked = pctl->irq.masked;
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if (pctl->irq.masked & (1 << n)) {
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sx150x_write_cfg(pctl->client, n, 1,
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pctl->data->reg_irq_mask, 1);
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sx150x_write_cfg(pctl->client, n, 2,
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pctl->data->reg_sense, 0);
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} else {
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sx150x_write_cfg(pctl->client, n, 1,
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pctl->data->reg_irq_mask, 0);
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sx150x_write_cfg(pctl->client, n, 2,
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pctl->data->reg_sense,
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pctl->irq.sense >> (n * 2));
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}
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out:
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regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked);
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regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense);
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mutex_unlock(&pctl->lock);
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}
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@ -628,10 +530,9 @@ static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned int param = pinconf_to_config_param(*config);
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int ret;
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u32 arg;
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unsigned int data;
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if (sx150x_pin_is_oscio(pctl, pin)) {
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unsigned int data;
|
||||
|
||||
switch (param) {
|
||||
case PIN_CONFIG_DRIVE_PUSH_PULL:
|
||||
case PIN_CONFIG_OUTPUT:
|
||||
@ -666,8 +567,10 @@ static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
mutex_lock(&pctl->lock);
|
||||
ret = sx150x_read_cfg(pctl->client, pin, 1,
|
||||
pctl->data->reg_pulldn);
|
||||
ret = regmap_read(pctl->regmap,
|
||||
pctl->data->reg_pulldn,
|
||||
&data);
|
||||
data &= BIT(pin);
|
||||
mutex_unlock(&pctl->lock);
|
||||
|
||||
if (ret < 0)
|
||||
@ -681,8 +584,10 @@ static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
mutex_lock(&pctl->lock);
|
||||
ret = sx150x_read_cfg(pctl->client, pin, 1,
|
||||
pctl->data->reg_pullup);
|
||||
ret = regmap_read(pctl->regmap,
|
||||
pctl->data->reg_pullup,
|
||||
&data);
|
||||
data &= BIT(pin);
|
||||
mutex_unlock(&pctl->lock);
|
||||
|
||||
if (ret < 0)
|
||||
@ -699,14 +604,16 @@ static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
return -ENOTSUPP;
|
||||
|
||||
mutex_lock(&pctl->lock);
|
||||
ret = sx150x_read_cfg(pctl->client, pin, 1,
|
||||
pctl->data->pri.x789.reg_drain);
|
||||
ret = regmap_read(pctl->regmap,
|
||||
pctl->data->pri.x789.reg_drain,
|
||||
&data);
|
||||
data &= BIT(pin);
|
||||
mutex_unlock(&pctl->lock);
|
||||
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (!ret)
|
||||
if (!data)
|
||||
return -EINVAL;
|
||||
|
||||
arg = 1;
|
||||
@ -717,14 +624,16 @@ static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
arg = true;
|
||||
else {
|
||||
mutex_lock(&pctl->lock);
|
||||
ret = sx150x_read_cfg(pctl->client, pin, 1,
|
||||
pctl->data->pri.x789.reg_drain);
|
||||
ret = regmap_read(pctl->regmap,
|
||||
pctl->data->pri.x789.reg_drain,
|
||||
&data);
|
||||
data &= BIT(pin);
|
||||
mutex_unlock(&pctl->lock);
|
||||
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (ret)
|
||||
if (data)
|
||||
return -EINVAL;
|
||||
|
||||
arg = 1;
|
||||
@ -785,15 +694,17 @@ static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
mutex_lock(&pctl->lock);
|
||||
ret = sx150x_write_cfg(pctl->client, pin, 1,
|
||||
pctl->data->reg_pulldn, 0);
|
||||
ret = regmap_write_bits(pctl->regmap,
|
||||
pctl->data->reg_pulldn,
|
||||
BIT(pin), 0);
|
||||
mutex_unlock(&pctl->lock);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
mutex_lock(&pctl->lock);
|
||||
ret = sx150x_write_cfg(pctl->client, pin, 1,
|
||||
pctl->data->reg_pullup, 0);
|
||||
ret = regmap_write_bits(pctl->regmap,
|
||||
pctl->data->reg_pullup,
|
||||
BIT(pin), 0);
|
||||
mutex_unlock(&pctl->lock);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
@ -802,9 +713,9 @@ static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
mutex_lock(&pctl->lock);
|
||||
ret = sx150x_write_cfg(pctl->client, pin, 1,
|
||||
pctl->data->reg_pullup,
|
||||
1);
|
||||
ret = regmap_write_bits(pctl->regmap,
|
||||
pctl->data->reg_pullup,
|
||||
BIT(pin), BIT(pin));
|
||||
mutex_unlock(&pctl->lock);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
@ -813,9 +724,9 @@ static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
mutex_lock(&pctl->lock);
|
||||
ret = sx150x_write_cfg(pctl->client, pin, 1,
|
||||
pctl->data->reg_pulldn,
|
||||
1);
|
||||
ret = regmap_write_bits(pctl->regmap,
|
||||
pctl->data->reg_pulldn,
|
||||
BIT(pin), BIT(pin));
|
||||
mutex_unlock(&pctl->lock);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
@ -878,16 +789,6 @@ static const struct of_device_id sx150x_of_match[] = {
|
||||
{},
|
||||
};
|
||||
|
||||
static int sx150x_init_io(struct sx150x_pinctrl *pctl, u8 base, u16 cfg)
|
||||
{
|
||||
int err = 0;
|
||||
unsigned int n;
|
||||
|
||||
for (n = 0; err >= 0 && n < (pctl->data->ngpios / 8); ++n)
|
||||
err = regmap_write(pctl->regmap, base - n, cfg >> (n * 8));
|
||||
return err;
|
||||
}
|
||||
|
||||
static int sx150x_reset(struct sx150x_pinctrl *pctl)
|
||||
{
|
||||
int err;
|
||||
@ -933,11 +834,16 @@ static int sx150x_init_misc(struct sx150x_pinctrl *pctl)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return i2c_smbus_write_byte_data(pctl->client, reg, value);
|
||||
return regmap_write(pctl->regmap, reg, value);
|
||||
}
|
||||
|
||||
static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
|
||||
{
|
||||
const u8 reg[] = {
|
||||
[SX150X_789] = pctl->data->pri.x789.reg_polarity,
|
||||
[SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
|
||||
[SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
|
||||
};
|
||||
int err;
|
||||
|
||||
if (pctl->data->model == SX150X_789 &&
|
||||
@ -952,27 +858,164 @@ static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
|
||||
return err;
|
||||
|
||||
/* Set all pins to work in normal mode */
|
||||
if (pctl->data->model == SX150X_789) {
|
||||
err = sx150x_init_io(pctl,
|
||||
pctl->data->pri.x789.reg_polarity,
|
||||
0);
|
||||
if (err < 0)
|
||||
return err;
|
||||
} else if (pctl->data->model == SX150X_456) {
|
||||
/* Set all pins to work in normal mode */
|
||||
err = sx150x_init_io(pctl,
|
||||
pctl->data->pri.x456.reg_pld_mode,
|
||||
0);
|
||||
if (err < 0)
|
||||
return err;
|
||||
return regmap_write(pctl->regmap, reg[pctl->data->model], 0);
|
||||
}
|
||||
|
||||
static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl,
|
||||
unsigned int reg)
|
||||
{
|
||||
const struct sx150x_device_data *data = pctl->data;
|
||||
|
||||
if (reg == data->reg_sense) {
|
||||
/*
|
||||
* RegSense packs two bits of configuration per GPIO,
|
||||
* so we'd need to read twice as many bits as there
|
||||
* are GPIO in our chip
|
||||
*/
|
||||
return 2 * data->ngpios;
|
||||
} else if ((data->model == SX150X_789 &&
|
||||
(reg == data->pri.x789.reg_misc ||
|
||||
reg == data->pri.x789.reg_clock ||
|
||||
reg == data->pri.x789.reg_reset))
|
||||
||
|
||||
(data->model == SX150X_123 &&
|
||||
reg == data->pri.x123.reg_advance)
|
||||
||
|
||||
(data->model == SX150X_456 &&
|
||||
reg == data->pri.x456.reg_advance)) {
|
||||
return 8;
|
||||
} else {
|
||||
/* Set all pins to work in normal mode */
|
||||
err = sx150x_init_io(pctl,
|
||||
pctl->data->pri.x123.reg_pld_mode,
|
||||
0);
|
||||
if (err < 0)
|
||||
return err;
|
||||
return data->ngpios;
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl,
|
||||
unsigned int reg, unsigned int val)
|
||||
{
|
||||
unsigned int a, b;
|
||||
const struct sx150x_device_data *data = pctl->data;
|
||||
|
||||
/*
|
||||
* Whereas SX1509 presents RegSense in a simple layout as such:
|
||||
* reg [ f f e e d d c c ]
|
||||
* reg + 1 [ b b a a 9 9 8 8 ]
|
||||
* reg + 2 [ 7 7 6 6 5 5 4 4 ]
|
||||
* reg + 3 [ 3 3 2 2 1 1 0 0 ]
|
||||
*
|
||||
* SX1503 and SX1506 deviate from that data layout, instead storing
|
||||
* thier contents as follows:
|
||||
*
|
||||
* reg [ f f e e d d c c ]
|
||||
* reg + 1 [ 7 7 6 6 5 5 4 4 ]
|
||||
* reg + 2 [ b b a a 9 9 8 8 ]
|
||||
* reg + 3 [ 3 3 2 2 1 1 0 0 ]
|
||||
*
|
||||
* so, taking that into account, we swap two
|
||||
* inner bytes of a 4-byte result
|
||||
*/
|
||||
|
||||
if (reg == data->reg_sense &&
|
||||
data->ngpios == 16 &&
|
||||
(data->model == SX150X_123 ||
|
||||
data->model == SX150X_456)) {
|
||||
a = val & 0x00ff0000;
|
||||
b = val & 0x0000ff00;
|
||||
|
||||
val &= 0xff0000ff;
|
||||
val |= b << 8;
|
||||
val |= a >> 8;
|
||||
}
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
/*
|
||||
* In order to mask the differences between 16 and 8 bit expander
|
||||
* devices we set up a sligthly ficticious regmap that pretends to be
|
||||
* a set of 32-bit (to accomodate RegSenseLow/RegSenseHigh
|
||||
* pair/quartet) registers and transparently reconstructs those
|
||||
* registers via multiple I2C/SMBus reads
|
||||
*
|
||||
* This way the rest of the driver code, interfacing with the chip via
|
||||
* regmap API, can work assuming that each GPIO pin is represented by
|
||||
* a group of bits at an offset proportioan to GPIO number within a
|
||||
* given register.
|
||||
*
|
||||
*/
|
||||
static int sx150x_regmap_reg_read(void *context, unsigned int reg,
|
||||
unsigned int *result)
|
||||
{
|
||||
int ret, n;
|
||||
struct sx150x_pinctrl *pctl = context;
|
||||
struct i2c_client *i2c = pctl->client;
|
||||
const int width = sx150x_regmap_reg_width(pctl, reg);
|
||||
unsigned int idx, val;
|
||||
|
||||
/*
|
||||
* There are four potential cases coverd by this function:
|
||||
*
|
||||
* 1) 8-pin chip, single configuration bit register
|
||||
*
|
||||
* This is trivial the code below just needs to read:
|
||||
* reg [ 7 6 5 4 3 2 1 0 ]
|
||||
*
|
||||
* 2) 8-pin chip, double configuration bit register (RegSense)
|
||||
*
|
||||
* The read will be done as follows:
|
||||
* reg [ 7 7 6 6 5 5 4 4 ]
|
||||
* reg + 1 [ 3 3 2 2 1 1 0 0 ]
|
||||
*
|
||||
* 3) 16-pin chip, single configuration bit register
|
||||
*
|
||||
* The read will be done as follows:
|
||||
* reg [ f e d c b a 9 8 ]
|
||||
* reg + 1 [ 7 6 5 4 3 2 1 0 ]
|
||||
*
|
||||
* 4) 16-pin chip, double configuration bit register (RegSense)
|
||||
*
|
||||
* The read will be done as follows:
|
||||
* reg [ f f e e d d c c ]
|
||||
* reg + 1 [ b b a a 9 9 8 8 ]
|
||||
* reg + 2 [ 7 7 6 6 5 5 4 4 ]
|
||||
* reg + 3 [ 3 3 2 2 1 1 0 0 ]
|
||||
*/
|
||||
|
||||
for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) {
|
||||
val <<= 8;
|
||||
|
||||
ret = i2c_smbus_read_byte_data(i2c, idx);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
val |= ret;
|
||||
}
|
||||
|
||||
*result = sx150x_maybe_swizzle(pctl, reg, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sx150x_regmap_reg_write(void *context, unsigned int reg,
|
||||
unsigned int val)
|
||||
{
|
||||
int ret, n;
|
||||
struct sx150x_pinctrl *pctl = context;
|
||||
struct i2c_client *i2c = pctl->client;
|
||||
const int width = sx150x_regmap_reg_width(pctl, reg);
|
||||
|
||||
val = sx150x_maybe_swizzle(pctl, reg, val);
|
||||
|
||||
n = width - 8;
|
||||
do {
|
||||
const u8 byte = (val >> n) & 0xff;
|
||||
|
||||
ret = i2c_smbus_write_byte_data(i2c, reg, byte);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
reg++;
|
||||
n -= 8;
|
||||
} while (n >= 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -981,18 +1024,18 @@ static bool sx150x_reg_volatile(struct device *dev, unsigned int reg)
|
||||
{
|
||||
struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev));
|
||||
|
||||
return reg == pctl->data->reg_irq_src ||
|
||||
reg == pctl->data->reg_irq_src - 1 ||
|
||||
reg == pctl->data->reg_data ||
|
||||
reg == pctl->data->reg_data - 1;
|
||||
return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
|
||||
}
|
||||
|
||||
const struct regmap_config sx150x_regmap_config = {
|
||||
.reg_bits = 8,
|
||||
.val_bits = 8,
|
||||
.val_bits = 32,
|
||||
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
|
||||
.reg_read = sx150x_regmap_reg_read,
|
||||
.reg_write = sx150x_regmap_reg_write,
|
||||
|
||||
.max_register = SX150X_MAX_REGISTER,
|
||||
.volatile_reg = sx150x_reg_volatile,
|
||||
};
|
||||
@ -1026,7 +1069,8 @@ static int sx150x_probe(struct i2c_client *client,
|
||||
if (!pctl->data)
|
||||
return -EINVAL;
|
||||
|
||||
pctl->regmap = devm_regmap_init_i2c(client, &sx150x_regmap_config);
|
||||
pctl->regmap = devm_regmap_init(dev, NULL, pctl,
|
||||
&sx150x_regmap_config);
|
||||
if (IS_ERR(pctl->regmap)) {
|
||||
ret = PTR_ERR(pctl->regmap);
|
||||
dev_err(dev, "Failed to allocate register map: %d\n",
|
||||
@ -1072,9 +1116,6 @@ static int sx150x_probe(struct i2c_client *client,
|
||||
|
||||
pctl->irq.masked = ~0;
|
||||
pctl->irq.sense = 0;
|
||||
pctl->irq.dev_masked = ~0;
|
||||
pctl->irq.dev_sense = 0;
|
||||
pctl->irq.update = -1;
|
||||
|
||||
ret = gpiochip_irqchip_add(&pctl->gpio,
|
||||
&pctl->irq_chip, 0,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user