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s390/ptrace: PTRACE_TE_ABORT_RAND

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The patch implements a s390 specific ptrace request
PTRACE_TE_ABORT_RAND to modify the randomness of spontaneous
aborts of memory transactions of the transaction execution
facility. The data argument of the ptrace request is used to
specify the levels of randomness, 0 for normal operation, 1 to
abort every transaction at a random instruction, and 2 to abort
a random transaction at a random instruction. The default is 0
for normal operation.

Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Michael Mueller <mimu@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
Michael Mueller 2013-07-02 22:58:26 +02:00 committed by Martin Schwidefsky
parent 47188d39b5
commit 64597f9dae
4 changed files with 51 additions and 14 deletions
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10
arch/s390/include/asm/processor.h
View File

@ -91,7 +91,15 @@ struct thread_struct {
#endif #endif
}; };
#define PER_FLAG_NO_TE 1UL /* Flag to disable transactions. */ /* Flag to disable transactions. */
#define PER_FLAG_NO_TE 1UL
/* Flag to enable random transaction aborts. */
#define PER_FLAG_TE_ABORT_RAND 2UL
/* Flag to specify random transaction abort mode:
* - abort each transaction at a random instruction before TEND if set.
* - abort random transactions at a random instruction if cleared.
*/
#define PER_FLAG_TE_ABORT_RAND_TEND 4UL
typedef struct thread_struct thread_struct; typedef struct thread_struct thread_struct;

4
arch/s390/include/asm/switch_to.h
View File

@ -10,7 +10,7 @@
#include <linux/thread_info.h> #include <linux/thread_info.h>
extern struct task_struct *__switch_to(void *, void *); extern struct task_struct *__switch_to(void *, void *);
extern void update_per_regs(struct task_struct *task); extern void update_cr_regs(struct task_struct *task);
static inline void save_fp_regs(s390_fp_regs *fpregs) static inline void save_fp_regs(s390_fp_regs *fpregs)
{ {
@ -86,7 +86,7 @@ static inline void restore_access_regs(unsigned int *acrs)
restore_fp_regs(&next->thread.fp_regs); \ restore_fp_regs(&next->thread.fp_regs); \
restore_access_regs(&next->thread.acrs[0]); \ restore_access_regs(&next->thread.acrs[0]); \
restore_ri_cb(next->thread.ri_cb, prev->thread.ri_cb); \ restore_ri_cb(next->thread.ri_cb, prev->thread.ri_cb); \
update_per_regs(next); \ update_cr_regs(next); \
} \ } \
prev = __switch_to(prev,next); \ prev = __switch_to(prev,next); \
} while (0) } while (0)

1
arch/s390/include/uapi/asm/ptrace.h
View File

@ -400,6 +400,7 @@ typedef struct
#define PTRACE_POKE_SYSTEM_CALL 0x5008 #define PTRACE_POKE_SYSTEM_CALL 0x5008
#define PTRACE_ENABLE_TE 0x5009 #define PTRACE_ENABLE_TE 0x5009
#define PTRACE_DISABLE_TE 0x5010 #define PTRACE_DISABLE_TE 0x5010
#define PTRACE_TE_ABORT_RAND 0x5011
/* /*
* PT_PROT definition is loosely based on hppa bsd definition in * PT_PROT definition is loosely based on hppa bsd definition in

50
arch/s390/kernel/ptrace.c
View File

@ -47,7 +47,7 @@ enum s390_regset {
REGSET_GENERAL_EXTENDED, REGSET_GENERAL_EXTENDED,
}; };
void update_per_regs(struct task_struct *task) void update_cr_regs(struct task_struct *task)
{ {
struct pt_regs *regs = task_pt_regs(task); struct pt_regs *regs = task_pt_regs(task);
struct thread_struct *thread = &task->thread; struct thread_struct *thread = &task->thread;
@ -56,17 +56,25 @@ void update_per_regs(struct task_struct *task)
#ifdef CONFIG_64BIT #ifdef CONFIG_64BIT
/* Take care of the enable/disable of transactional execution. */ /* Take care of the enable/disable of transactional execution. */
if (MACHINE_HAS_TE) { if (MACHINE_HAS_TE) {
unsigned long cr0, cr0_new; unsigned long cr[3], cr_new[3];
__ctl_store(cr0, 0, 0); __ctl_store(cr, 0, 2);
/* set or clear transaction execution bits 8 and 9. */ cr_new[1] = cr[1];
/* Set or clear transaction execution TXC/PIFO bits 8 and 9. */
if (task->thread.per_flags & PER_FLAG_NO_TE) if (task->thread.per_flags & PER_FLAG_NO_TE)
cr0_new = cr0 & ~(3UL << 54); cr_new[0] = cr[0] & ~(3UL << 54);
else else
cr0_new = cr0 | (3UL << 54); cr_new[0] = cr[0] | (3UL << 54);
/* Only load control register 0 if necessary. */ /* Set or clear transaction execution TDC bits 62 and 63. */
if (cr0 != cr0_new) cr_new[2] = cr[2] & ~3UL;
__ctl_load(cr0_new, 0, 0); if (task->thread.per_flags & PER_FLAG_TE_ABORT_RAND) {
if (task->thread.per_flags & PER_FLAG_TE_ABORT_RAND_TEND)
cr_new[2] |= 1UL;
else
cr_new[2] |= 2UL;
}
if (memcmp(&cr_new, &cr, sizeof(cr)))
__ctl_load(cr_new, 0, 2);
} }
#endif #endif
/* Copy user specified PER registers */ /* Copy user specified PER registers */
@ -100,14 +108,14 @@ void user_enable_single_step(struct task_struct *task)
{ {
set_tsk_thread_flag(task, TIF_SINGLE_STEP); set_tsk_thread_flag(task, TIF_SINGLE_STEP);
if (task == current) if (task == current)
update_per_regs(task); update_cr_regs(task);
} }
void user_disable_single_step(struct task_struct *task) void user_disable_single_step(struct task_struct *task)
{ {
clear_tsk_thread_flag(task, TIF_SINGLE_STEP); clear_tsk_thread_flag(task, TIF_SINGLE_STEP);
if (task == current) if (task == current)
update_per_regs(task); update_cr_regs(task);
} }
/* /*
@ -447,6 +455,26 @@ long arch_ptrace(struct task_struct *child, long request,
if (!MACHINE_HAS_TE) if (!MACHINE_HAS_TE)
return -EIO; return -EIO;
child->thread.per_flags |= PER_FLAG_NO_TE; child->thread.per_flags |= PER_FLAG_NO_TE;
child->thread.per_flags &= ~PER_FLAG_TE_ABORT_RAND;
return 0;
case PTRACE_TE_ABORT_RAND:
if (!MACHINE_HAS_TE || (child->thread.per_flags & PER_FLAG_NO_TE))
return -EIO;
switch (data) {
case 0UL:
child->thread.per_flags &= ~PER_FLAG_TE_ABORT_RAND;
break;
case 1UL:
child->thread.per_flags |= PER_FLAG_TE_ABORT_RAND;
child->thread.per_flags |= PER_FLAG_TE_ABORT_RAND_TEND;
break;
case 2UL:
child->thread.per_flags |= PER_FLAG_TE_ABORT_RAND;
child->thread.per_flags &= ~PER_FLAG_TE_ABORT_RAND_TEND;
break;
default:
return -EINVAL;
}
return 0; return 0;
default: default:
/* Removing high order bit from addr (only for 31 bit). */ /* Removing high order bit from addr (only for 31 bit). */