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tpm: Remove read16/read32/write32 calls from tpm_tis_phy_ops
Only tpm_tis and tpm_tis_synquacer have a dedicated way to access multiple bytes at once, every other driver will just fall back to read_bytes/write_bytes. Therefore, remove the read16/read32/write32 calls and move their logic to read_bytes/write_bytes. Suggested-by: Jarkko Sakkinen <jarkko@kernel.org> Signed-off-by: Johannes Holland <johannes.holland@infineon.com> Reviewed-by: Jarkko Sakkinen <jarkko@kernel.org> Signed-off-by: Jarkko Sakkinen <jarkko@kernel.org>
This commit is contained in:
parent
d0dc1a7100
commit
6422cbd3c5
@ -153,50 +153,46 @@ static int check_acpi_tpm2(struct device *dev)
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#endif
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static int tpm_tcg_read_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
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u8 *result)
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u8 *result, enum tpm_tis_io_mode io_mode)
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{
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struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
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__le16 result_le16;
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__le32 result_le32;
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while (len--)
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*result++ = ioread8(phy->iobase + addr);
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switch (io_mode) {
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case TPM_TIS_PHYS_8:
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while (len--)
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*result++ = ioread8(phy->iobase + addr);
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break;
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case TPM_TIS_PHYS_16:
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result_le16 = cpu_to_le16(ioread16(phy->iobase + addr));
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memcpy(result, &result_le16, sizeof(u16));
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break;
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case TPM_TIS_PHYS_32:
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result_le32 = cpu_to_le32(ioread32(phy->iobase + addr));
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memcpy(result, &result_le32, sizeof(u32));
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break;
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}
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return 0;
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}
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static int tpm_tcg_write_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
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const u8 *value)
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const u8 *value, enum tpm_tis_io_mode io_mode)
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{
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struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
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while (len--)
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iowrite8(*value++, phy->iobase + addr);
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return 0;
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}
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static int tpm_tcg_read16(struct tpm_tis_data *data, u32 addr, u16 *result)
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{
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struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
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*result = ioread16(phy->iobase + addr);
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return 0;
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}
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static int tpm_tcg_read32(struct tpm_tis_data *data, u32 addr, u32 *result)
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{
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struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
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*result = ioread32(phy->iobase + addr);
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return 0;
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}
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static int tpm_tcg_write32(struct tpm_tis_data *data, u32 addr, u32 value)
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{
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struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
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iowrite32(value, phy->iobase + addr);
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switch (io_mode) {
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case TPM_TIS_PHYS_8:
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while (len--)
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iowrite8(*value++, phy->iobase + addr);
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break;
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case TPM_TIS_PHYS_16:
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return -EINVAL;
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case TPM_TIS_PHYS_32:
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iowrite32(le32_to_cpu(*((__le32 *)value)), phy->iobase + addr);
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break;
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}
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return 0;
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}
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@ -204,9 +200,6 @@ static int tpm_tcg_write32(struct tpm_tis_data *data, u32 addr, u32 value)
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static const struct tpm_tis_phy_ops tpm_tcg = {
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.read_bytes = tpm_tcg_read_bytes,
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.write_bytes = tpm_tcg_write_bytes,
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.read16 = tpm_tcg_read16,
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.read32 = tpm_tcg_read32,
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.write32 = tpm_tcg_write32,
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};
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static int tpm_tis_init(struct device *dev, struct tpm_info *tpm_info)
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@ -104,54 +104,88 @@ struct tpm_tis_data {
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unsigned int timeout_max; /* usecs */
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};
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/*
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* IO modes to indicate how many bytes should be read/written at once in the
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* tpm_tis_phy_ops read_bytes/write_bytes calls. Use TPM_TIS_PHYS_8 to
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* receive/transmit byte-wise, TPM_TIS_PHYS_16 for two bytes etc.
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*/
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enum tpm_tis_io_mode {
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TPM_TIS_PHYS_8,
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TPM_TIS_PHYS_16,
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TPM_TIS_PHYS_32,
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};
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struct tpm_tis_phy_ops {
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/* data is passed in little endian */
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int (*read_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
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u8 *result);
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u8 *result, enum tpm_tis_io_mode mode);
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int (*write_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
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const u8 *value);
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int (*read16)(struct tpm_tis_data *data, u32 addr, u16 *result);
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int (*read32)(struct tpm_tis_data *data, u32 addr, u32 *result);
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int (*write32)(struct tpm_tis_data *data, u32 addr, u32 src);
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const u8 *value, enum tpm_tis_io_mode mode);
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};
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static inline int tpm_tis_read_bytes(struct tpm_tis_data *data, u32 addr,
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u16 len, u8 *result)
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{
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return data->phy_ops->read_bytes(data, addr, len, result);
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return data->phy_ops->read_bytes(data, addr, len, result,
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TPM_TIS_PHYS_8);
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}
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static inline int tpm_tis_read8(struct tpm_tis_data *data, u32 addr, u8 *result)
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{
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return data->phy_ops->read_bytes(data, addr, 1, result);
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return data->phy_ops->read_bytes(data, addr, 1, result, TPM_TIS_PHYS_8);
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}
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static inline int tpm_tis_read16(struct tpm_tis_data *data, u32 addr,
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u16 *result)
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{
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return data->phy_ops->read16(data, addr, result);
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__le16 result_le;
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int rc;
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rc = data->phy_ops->read_bytes(data, addr, sizeof(u16),
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(u8 *)&result_le, TPM_TIS_PHYS_16);
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if (!rc)
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*result = le16_to_cpu(result_le);
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return rc;
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}
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static inline int tpm_tis_read32(struct tpm_tis_data *data, u32 addr,
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u32 *result)
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{
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return data->phy_ops->read32(data, addr, result);
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__le32 result_le;
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int rc;
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rc = data->phy_ops->read_bytes(data, addr, sizeof(u32),
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(u8 *)&result_le, TPM_TIS_PHYS_32);
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if (!rc)
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*result = le32_to_cpu(result_le);
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return rc;
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}
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static inline int tpm_tis_write_bytes(struct tpm_tis_data *data, u32 addr,
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u16 len, const u8 *value)
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{
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return data->phy_ops->write_bytes(data, addr, len, value);
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return data->phy_ops->write_bytes(data, addr, len, value,
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TPM_TIS_PHYS_8);
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}
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static inline int tpm_tis_write8(struct tpm_tis_data *data, u32 addr, u8 value)
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{
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return data->phy_ops->write_bytes(data, addr, 1, &value);
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return data->phy_ops->write_bytes(data, addr, 1, &value,
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TPM_TIS_PHYS_8);
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}
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static inline int tpm_tis_write32(struct tpm_tis_data *data, u32 addr,
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u32 value)
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{
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return data->phy_ops->write32(data, addr, value);
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__le32 value_le;
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int rc;
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value_le = cpu_to_le32(value);
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rc = data->phy_ops->write_bytes(data, addr, sizeof(u32),
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(u8 *)&value_le, TPM_TIS_PHYS_32);
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return rc;
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}
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static inline bool is_bsw(void)
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@ -31,10 +31,6 @@ extern int tpm_tis_spi_init(struct spi_device *spi, struct tpm_tis_spi_phy *phy,
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extern int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16 len,
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u8 *in, const u8 *out);
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extern int tpm_tis_spi_read16(struct tpm_tis_data *data, u32 addr, u16 *result);
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extern int tpm_tis_spi_read32(struct tpm_tis_data *data, u32 addr, u32 *result);
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extern int tpm_tis_spi_write32(struct tpm_tis_data *data, u32 addr, u32 value);
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#ifdef CONFIG_TCG_TIS_SPI_CR50
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extern int cr50_spi_probe(struct spi_device *spi);
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#else
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@ -222,13 +222,13 @@ static int tpm_tis_spi_cr50_transfer(struct tpm_tis_data *data, u32 addr, u16 le
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}
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static int tpm_tis_spi_cr50_read_bytes(struct tpm_tis_data *data, u32 addr,
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u16 len, u8 *result)
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u16 len, u8 *result, enum tpm_tis_io_mode io_mode)
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{
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return tpm_tis_spi_cr50_transfer(data, addr, len, result, NULL);
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}
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static int tpm_tis_spi_cr50_write_bytes(struct tpm_tis_data *data, u32 addr,
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u16 len, const u8 *value)
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u16 len, const u8 *value, enum tpm_tis_io_mode io_mode)
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{
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return tpm_tis_spi_cr50_transfer(data, addr, len, NULL, value);
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}
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@ -236,9 +236,6 @@ static int tpm_tis_spi_cr50_write_bytes(struct tpm_tis_data *data, u32 addr,
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static const struct tpm_tis_phy_ops tpm_spi_cr50_phy_ops = {
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.read_bytes = tpm_tis_spi_cr50_read_bytes,
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.write_bytes = tpm_tis_spi_cr50_write_bytes,
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.read16 = tpm_tis_spi_read16,
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.read32 = tpm_tis_spi_read32,
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.write32 = tpm_tis_spi_write32,
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};
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static void cr50_print_fw_version(struct tpm_tis_data *data)
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@ -141,55 +141,17 @@ exit:
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}
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static int tpm_tis_spi_read_bytes(struct tpm_tis_data *data, u32 addr,
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u16 len, u8 *result)
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u16 len, u8 *result, enum tpm_tis_io_mode io_mode)
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{
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return tpm_tis_spi_transfer(data, addr, len, result, NULL);
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}
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static int tpm_tis_spi_write_bytes(struct tpm_tis_data *data, u32 addr,
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u16 len, const u8 *value)
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u16 len, const u8 *value, enum tpm_tis_io_mode io_mode)
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{
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return tpm_tis_spi_transfer(data, addr, len, NULL, value);
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}
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int tpm_tis_spi_read16(struct tpm_tis_data *data, u32 addr, u16 *result)
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{
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__le16 result_le;
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int rc;
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rc = data->phy_ops->read_bytes(data, addr, sizeof(u16),
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(u8 *)&result_le);
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if (!rc)
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*result = le16_to_cpu(result_le);
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return rc;
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}
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int tpm_tis_spi_read32(struct tpm_tis_data *data, u32 addr, u32 *result)
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{
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__le32 result_le;
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int rc;
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rc = data->phy_ops->read_bytes(data, addr, sizeof(u32),
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(u8 *)&result_le);
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if (!rc)
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*result = le32_to_cpu(result_le);
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return rc;
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}
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int tpm_tis_spi_write32(struct tpm_tis_data *data, u32 addr, u32 value)
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{
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__le32 value_le;
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int rc;
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value_le = cpu_to_le32(value);
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rc = data->phy_ops->write_bytes(data, addr, sizeof(u32),
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(u8 *)&value_le);
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return rc;
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}
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int tpm_tis_spi_init(struct spi_device *spi, struct tpm_tis_spi_phy *phy,
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int irq, const struct tpm_tis_phy_ops *phy_ops)
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{
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@ -205,9 +167,6 @@ int tpm_tis_spi_init(struct spi_device *spi, struct tpm_tis_spi_phy *phy,
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static const struct tpm_tis_phy_ops tpm_spi_phy_ops = {
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.read_bytes = tpm_tis_spi_read_bytes,
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.write_bytes = tpm_tis_spi_write_bytes,
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.read16 = tpm_tis_spi_read16,
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.read32 = tpm_tis_spi_read32,
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.write32 = tpm_tis_spi_write32,
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};
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static int tpm_tis_spi_probe(struct spi_device *dev)
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@ -35,72 +35,53 @@ static inline struct tpm_tis_synquacer_phy *to_tpm_tis_tcg_phy(struct tpm_tis_da
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}
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static int tpm_tis_synquacer_read_bytes(struct tpm_tis_data *data, u32 addr,
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u16 len, u8 *result)
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u16 len, u8 *result,
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enum tpm_tis_io_mode io_mode)
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{
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struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data);
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while (len--)
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*result++ = ioread8(phy->iobase + addr);
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switch (io_mode) {
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case TPM_TIS_PHYS_8:
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while (len--)
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*result++ = ioread8(phy->iobase + addr);
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break;
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case TPM_TIS_PHYS_16:
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result[1] = ioread8(phy->iobase + addr + 1);
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result[0] = ioread8(phy->iobase + addr);
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break;
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case TPM_TIS_PHYS_32:
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result[3] = ioread8(phy->iobase + addr + 3);
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result[2] = ioread8(phy->iobase + addr + 2);
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result[1] = ioread8(phy->iobase + addr + 1);
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result[0] = ioread8(phy->iobase + addr);
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break;
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}
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return 0;
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}
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static int tpm_tis_synquacer_write_bytes(struct tpm_tis_data *data, u32 addr,
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u16 len, const u8 *value)
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u16 len, const u8 *value,
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enum tpm_tis_io_mode io_mode)
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{
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struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data);
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while (len--)
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iowrite8(*value++, phy->iobase + addr);
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return 0;
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}
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static int tpm_tis_synquacer_read16_bw(struct tpm_tis_data *data,
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u32 addr, u16 *result)
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{
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struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data);
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/*
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* Due to the limitation of SPI controller on SynQuacer,
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* 16/32 bits access must be done in byte-wise and descending order.
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*/
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*result = (ioread8(phy->iobase + addr + 1) << 8) |
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(ioread8(phy->iobase + addr));
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return 0;
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}
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static int tpm_tis_synquacer_read32_bw(struct tpm_tis_data *data,
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u32 addr, u32 *result)
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{
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struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data);
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/*
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* Due to the limitation of SPI controller on SynQuacer,
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* 16/32 bits access must be done in byte-wise and descending order.
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*/
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*result = (ioread8(phy->iobase + addr + 3) << 24) |
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(ioread8(phy->iobase + addr + 2) << 16) |
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(ioread8(phy->iobase + addr + 1) << 8) |
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(ioread8(phy->iobase + addr));
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return 0;
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}
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static int tpm_tis_synquacer_write32_bw(struct tpm_tis_data *data,
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u32 addr, u32 value)
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{
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struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data);
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/*
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* Due to the limitation of SPI controller on SynQuacer,
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* 16/32 bits access must be done in byte-wise and descending order.
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*/
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iowrite8(value >> 24, phy->iobase + addr + 3);
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iowrite8(value >> 16, phy->iobase + addr + 2);
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iowrite8(value >> 8, phy->iobase + addr + 1);
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iowrite8(value, phy->iobase + addr);
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switch (io_mode) {
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case TPM_TIS_PHYS_8:
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while (len--)
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iowrite8(*value++, phy->iobase + addr);
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break;
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case TPM_TIS_PHYS_16:
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return -EINVAL;
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case TPM_TIS_PHYS_32:
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/*
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* Due to the limitation of SPI controller on SynQuacer,
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* 16/32 bits access must be done in byte-wise and descending order.
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*/
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iowrite8(value[3], phy->iobase + addr + 3);
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iowrite8(value[2], phy->iobase + addr + 2);
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iowrite8(value[1], phy->iobase + addr + 1);
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iowrite8(value[0], phy->iobase + addr);
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break;
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}
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return 0;
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}
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@ -108,9 +89,6 @@ static int tpm_tis_synquacer_write32_bw(struct tpm_tis_data *data,
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static const struct tpm_tis_phy_ops tpm_tcg_bw = {
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.read_bytes = tpm_tis_synquacer_read_bytes,
|
||||
.write_bytes = tpm_tis_synquacer_write_bytes,
|
||||
.read16 = tpm_tis_synquacer_read16_bw,
|
||||
.read32 = tpm_tis_synquacer_read32_bw,
|
||||
.write32 = tpm_tis_synquacer_write32_bw,
|
||||
};
|
||||
|
||||
static int tpm_tis_synquacer_init(struct device *dev,
|
||||
|
Loading…
Reference in New Issue
Block a user