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[ARM] Use new get_irqnr_preamble

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Use the new get_irqnr_preamble macro to move the address of the IRQ
controller outside the IRQ handling loop.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2007-05-12 15:25:50 +01:00 committed by Russell King
parent 3b938be69e
commit 641e79129a
8 changed files with 42 additions and 32 deletions
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8
include/asm-arm/arch-cl7500/entry-macro.S
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@ -1,6 +1,14 @@
#include <asm/hardware.h>
#include <asm/hardware/entry-macro-iomd.S>
.equ ioc_base_high, IOC_BASE & 0xff000000
.equ ioc_base_low, IOC_BASE & 0x00ff0000
.macro get_irqnr_preamble, base, tmp
mov \base, #ioc_base_high @ point at IOC
.if ioc_base_low
orr \base, \base, #ioc_base_low
.endif
.endm
.macro arch_ret_to_user, tmp1, tmp2

2
include/asm-arm/arch-ebsa110/entry-macro.S
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@ -16,13 +16,13 @@
.endm
.macro get_irqnr_preamble, base, tmp
mov \base, #IRQ_STAT
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, stat, base, tmp
mov \base, #IRQ_STAT
ldrb \stat, [\base] @ get interrupts
mov \irqnr, #0
tst \stat, #15

16
include/asm-arm/arch-ebsa285/entry-macro.S
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@ -11,24 +11,24 @@
#include <asm/arch/irqs.h>
#include <asm/hardware/dec21285.h>
.equ dc21285_high, ARMCSR_BASE & 0xff000000
.equ dc21285_low, ARMCSR_BASE & 0x00ffffff
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
mov \base, #dc21285_high
.if dc21285_low
orr \base, \base, #dc21285_low
.endif
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.equ dc21285_high, ARMCSR_BASE & 0xff000000
.equ dc21285_low, ARMCSR_BASE & 0x00ffffff
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #dc21285_high
.if dc21285_low
orr r4, r4, #dc21285_low
.endif
ldr \irqstat, [r4, #0x180] @ get interrupts
ldr \irqstat, [\base, #0x180] @ get interrupts
mov \irqnr, #IRQ_SDRAMPARITY
tst \irqstat, #IRQ_MASK_SDRAMPARITY

2
include/asm-arm/arch-realview/entry-macro.S
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@ -14,6 +14,7 @@
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE)
.endm
.macro arch_ret_to_user, tmp1, tmp2
@ -40,7 +41,6 @@
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE)
ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
ldr \tmp, =1021

8
include/asm-arm/arch-rpc/entry-macro.S
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@ -1,6 +1,14 @@
#include <asm/hardware.h>
#include <asm/hardware/entry-macro-iomd.S>
.equ ioc_base_high, IOC_BASE & 0xff000000
.equ ioc_base_low, IOC_BASE & 0x00ff0000
.macro get_irqnr_preamble, base, tmp
mov \base, #ioc_base_high @ point at IOC
.if ioc_base_low
orr \base, \base, #ioc_base_low
.endif
.endm
.macro arch_ret_to_user, tmp1, tmp2

8
include/asm-arm/arch-sa1100/entry-macro.S
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@ -12,16 +12,16 @@
.endm
.macro get_irqnr_preamble, base, tmp
mov \base, #0xfa000000 @ ICIP = 0xfa050000
add \base, \base, #0x00050000
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #0xfa000000 @ ICIP = 0xfa050000
add r4, r4, #0x00050000
ldr \irqstat, [r4] @ get irqs
ldr \irqnr, [r4, #4] @ ICMR = 0xfa050004
ldr \irqstat, [\base] @ get irqs
ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004
ands \irqstat, \irqstat, \irqnr
mov \irqnr, #0
beq 1001f

2
include/asm-arm/arch-versatile/entry-macro.S
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@ -14,13 +14,13 @@
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE)
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE)
ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
mov \irqnr, #0
teq \irqstat, #0

28
include/asm-arm/hardware/entry-macro-iomd.S
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@ -11,8 +11,6 @@
/* IOC / IOMD based hardware */
#include <asm/hardware/iomd.h>
.equ ioc_base_high, IOC_BASE & 0xff000000
.equ ioc_base_low, IOC_BASE & 0x00ff0000
.macro disable_fiq
mov r12, #ioc_base_high
.if ioc_base_low
@ -22,33 +20,29 @@
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #ioc_base_high @ point at IOC
.if ioc_base_low
orr r4, r4, #ioc_base_low
.endif
ldrb \irqstat, [r4, #IOMD_IRQREQB] @ get high priority first
ldr \base, =irq_prio_h
ldrb \irqstat, [\base, #IOMD_IRQREQB] @ get high priority first
ldr \tmp, =irq_prio_h
teq \irqstat, #0
#ifdef IOMD_BASE
ldreqb \irqstat, [r4, #IOMD_DMAREQ] @ get dma
addeq \base, \base, #256 @ irq_prio_h table size
ldreqb \irqstat, [\base, #IOMD_DMAREQ] @ get dma
addeq \tmp, \tmp, #256 @ irq_prio_h table size
teqeq \irqstat, #0
bne 2406f
#endif
ldreqb \irqstat, [r4, #IOMD_IRQREQA] @ get low priority
addeq \base, \base, #256 @ irq_prio_d table size
ldreqb \irqstat, [\base, #IOMD_IRQREQA] @ get low priority
addeq \tmp, \tmp, #256 @ irq_prio_d table size
teqeq \irqstat, #0
#ifdef IOMD_IRQREQC
ldreqb \irqstat, [r4, #IOMD_IRQREQC]
addeq \base, \base, #256 @ irq_prio_l table size
ldreqb \irqstat, [\base, #IOMD_IRQREQC]
addeq \tmp, \tmp, #256 @ irq_prio_l table size
teqeq \irqstat, #0
#endif
#ifdef IOMD_IRQREQD
ldreqb \irqstat, [r4, #IOMD_IRQREQD]
addeq \base, \base, #256 @ irq_prio_lc table size
ldreqb \irqstat, [\base, #IOMD_IRQREQD]
addeq \tmp, \tmp, #256 @ irq_prio_lc table size
teqeq \irqstat, #0
#endif
2406: ldrneb \irqnr, [\base, \irqstat] @ get IRQ number
2406: ldrneb \irqnr, [\tmp, \irqstat] @ get IRQ number
.endm
/*