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synced 2024-11-14 15:54:15 +08:00
[SUNGEM]: PHY updates & pause fixes (#2)
This patch adds support for a few more PHYs used by Apple and fixes advertising and detecting of Pause (we were missing setting the bit in MII_ADVERTISE and weren't testing in LPA for all PHYs). Note that I currently only advertise pause, not asymetric pause. I don't know for sure the details there, I suppose I should read a bit more 802.3 references, and I don't now what sungem is capable of, but I noticed the PCS code (originated from you) does the same. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Benjamin Herrenschmidt
David S. Miller
parent
7f18ba6248
commit
63ea998a26
@ -90,7 +90,8 @@
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#define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
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SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
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SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
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SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
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SUPPORTED_Pause | SUPPORTED_Autoneg)
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#define DRV_NAME "sungem"
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#define DRV_VERSION "0.98"
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@ -3,10 +3,9 @@
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*
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* This file could be shared with other drivers.
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*
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* (c) 2002, Benjamin Herrenscmidt (benh@kernel.crashing.org)
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* (c) 2002-2007, Benjamin Herrenscmidt (benh@kernel.crashing.org)
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*
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* TODO:
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* - Implement WOL
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* - Add support for PHYs that provide an IRQ line
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* - Eventually moved the entire polling state machine in
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* there (out of the eth driver), so that it can easily be
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@ -152,6 +151,44 @@ static int bcm5221_suspend(struct mii_phy* phy)
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return 0;
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}
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static int bcm5241_init(struct mii_phy* phy)
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{
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u16 data;
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data = phy_read(phy, MII_BCM5221_TEST);
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phy_write(phy, MII_BCM5221_TEST,
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data | MII_BCM5221_TEST_ENABLE_SHADOWS);
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data = phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
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phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
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data | MII_BCM5221_SHDOW_AUX_STAT2_APD);
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data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
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phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
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data & ~MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR);
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data = phy_read(phy, MII_BCM5221_TEST);
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phy_write(phy, MII_BCM5221_TEST,
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data & ~MII_BCM5221_TEST_ENABLE_SHADOWS);
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return 0;
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}
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static int bcm5241_suspend(struct mii_phy* phy)
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{
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u16 data;
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data = phy_read(phy, MII_BCM5221_TEST);
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phy_write(phy, MII_BCM5221_TEST,
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data | MII_BCM5221_TEST_ENABLE_SHADOWS);
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data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
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phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
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data | MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR);
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return 0;
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}
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static int bcm5400_init(struct mii_phy* phy)
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{
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u16 data;
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@ -373,6 +410,10 @@ static int bcm54xx_setup_aneg(struct mii_phy *phy, u32 advertise)
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adv |= ADVERTISE_100HALF;
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if (advertise & ADVERTISED_100baseT_Full)
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adv |= ADVERTISE_100FULL;
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if (advertise & ADVERTISED_Pause)
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adv |= ADVERTISE_PAUSE_CAP;
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if (advertise & ADVERTISED_Asym_Pause)
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adv |= ADVERTISE_PAUSE_ASYM;
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phy_write(phy, MII_ADVERTISE, adv);
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/* Setup 1000BT advertise */
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@ -436,12 +477,15 @@ static int bcm54xx_read_link(struct mii_phy *phy)
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val = phy_read(phy, MII_BCM5400_AUXSTATUS);
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link_mode = ((val & MII_BCM5400_AUXSTATUS_LINKMODE_MASK) >>
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MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT);
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phy->duplex = phy_BCM5400_link_table[link_mode][0] ? DUPLEX_FULL : DUPLEX_HALF;
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phy->duplex = phy_BCM5400_link_table[link_mode][0] ?
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DUPLEX_FULL : DUPLEX_HALF;
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phy->speed = phy_BCM5400_link_table[link_mode][2] ?
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SPEED_1000 :
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(phy_BCM5400_link_table[link_mode][1] ? SPEED_100 : SPEED_10);
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(phy_BCM5400_link_table[link_mode][1] ?
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SPEED_100 : SPEED_10);
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val = phy_read(phy, MII_LPA);
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phy->pause = ((val & LPA_PAUSE) != 0);
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phy->pause = (phy->duplex == DUPLEX_FULL) &&
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((val & LPA_PAUSE) != 0);
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}
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/* On non-aneg, we assume what we put in BMCR is the speed,
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* though magic-aneg shouldn't prevent this case from occurring
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@ -450,6 +494,28 @@ static int bcm54xx_read_link(struct mii_phy *phy)
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return 0;
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}
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static int marvell88e1111_init(struct mii_phy* phy)
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{
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u16 rev;
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/* magic init sequence for rev 0 */
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rev = phy_read(phy, MII_PHYSID2) & 0x000f;
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if (rev == 0) {
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phy_write(phy, 0x1d, 0x000a);
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phy_write(phy, 0x1e, 0x0821);
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phy_write(phy, 0x1d, 0x0006);
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phy_write(phy, 0x1e, 0x8600);
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phy_write(phy, 0x1d, 0x000b);
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phy_write(phy, 0x1e, 0x0100);
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phy_write(phy, 0x1d, 0x0004);
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phy_write(phy, 0x1e, 0x4850);
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}
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return 0;
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}
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static int marvell_setup_aneg(struct mii_phy *phy, u32 advertise)
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{
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u16 ctl, adv;
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@ -471,6 +537,10 @@ static int marvell_setup_aneg(struct mii_phy *phy, u32 advertise)
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adv |= ADVERTISE_100HALF;
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if (advertise & ADVERTISED_100baseT_Full)
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adv |= ADVERTISE_100FULL;
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if (advertise & ADVERTISED_Pause)
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adv |= ADVERTISE_PAUSE_CAP;
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if (advertise & ADVERTISED_Asym_Pause)
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adv |= ADVERTISE_PAUSE_ASYM;
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phy_write(phy, MII_ADVERTISE, adv);
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/* Setup 1000BT advertise & enable crossover detect
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@ -549,7 +619,7 @@ static int marvell_setup_forced(struct mii_phy *phy, int speed, int fd)
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static int marvell_read_link(struct mii_phy *phy)
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{
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u16 status;
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u16 status, pmask;
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if (phy->autoneg) {
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status = phy_read(phy, MII_M1011_PHY_SPEC_STATUS);
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@ -565,7 +635,9 @@ static int marvell_read_link(struct mii_phy *phy)
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phy->duplex = DUPLEX_FULL;
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else
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phy->duplex = DUPLEX_HALF;
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phy->pause = 0; /* XXX Check against spec ! */
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pmask = MII_M1011_PHY_SPEC_STATUS_TX_PAUSE |
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MII_M1011_PHY_SPEC_STATUS_RX_PAUSE;
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phy->pause = (status & pmask) == pmask;
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}
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/* On non-aneg, we assume what we put in BMCR is the speed,
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* though magic-aneg shouldn't prevent this case from occurring
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@ -595,6 +667,10 @@ static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
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adv |= ADVERTISE_100HALF;
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if (advertise & ADVERTISED_100baseT_Full)
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adv |= ADVERTISE_100FULL;
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if (advertise & ADVERTISED_Pause)
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adv |= ADVERTISE_PAUSE_CAP;
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if (advertise & ADVERTISED_Asym_Pause)
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adv |= ADVERTISE_PAUSE_ASYM;
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phy_write(phy, MII_ADVERTISE, adv);
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/* Start/Restart aneg */
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@ -666,7 +742,8 @@ static int genmii_read_link(struct mii_phy *phy)
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phy->speed = SPEED_100;
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else
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phy->speed = SPEED_10;
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phy->pause = 0;
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phy->pause = (phy->duplex == DUPLEX_FULL) &&
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((lpa & LPA_PAUSE) != 0);
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}
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/* On non-aneg, we assume what we put in BMCR is the speed,
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* though magic-aneg shouldn't prevent this case from occurring
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@ -676,11 +753,19 @@ static int genmii_read_link(struct mii_phy *phy)
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}
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#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
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SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
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SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII)
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#define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
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SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
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#define MII_BASIC_FEATURES \
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(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
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SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
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SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII | \
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SUPPORTED_Pause)
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/* On gigabit capable PHYs, we advertise Pause support but not asym pause
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* support for now as I'm not sure it's supported and Darwin doesn't do
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* it neither. --BenH.
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*/
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#define MII_GBIT_FEATURES \
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(MII_BASIC_FEATURES | \
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SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
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/* Broadcom BCM 5201 */
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static struct mii_phy_ops bcm5201_phy_ops = {
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@ -720,6 +805,24 @@ static struct mii_phy_def bcm5221_phy_def = {
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.ops = &bcm5221_phy_ops
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};
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/* Broadcom BCM 5241 */
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static struct mii_phy_ops bcm5241_phy_ops = {
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.suspend = bcm5241_suspend,
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.init = bcm5241_init,
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.setup_aneg = genmii_setup_aneg,
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.setup_forced = genmii_setup_forced,
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.poll_link = genmii_poll_link,
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.read_link = genmii_read_link,
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};
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static struct mii_phy_def bcm5241_phy_def = {
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.phy_id = 0x0143bc30,
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.phy_id_mask = 0xfffffff0,
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.name = "BCM5241",
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.features = MII_BASIC_FEATURES,
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.magic_aneg = 1,
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.ops = &bcm5241_phy_ops
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};
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/* Broadcom BCM 5400 */
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static struct mii_phy_ops bcm5400_phy_ops = {
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.init = bcm5400_init,
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@ -854,11 +957,8 @@ static struct mii_phy_def bcm5462V_phy_def = {
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.ops = &bcm5462V_phy_ops
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};
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/* Marvell 88E1101 (Apple seem to deal with 2 different revs,
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* I masked out the 8 last bits to get both, but some specs
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* would be useful here) --BenH.
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*/
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static struct mii_phy_ops marvell_phy_ops = {
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/* Marvell 88E1101 amd 88E1111 */
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static struct mii_phy_ops marvell88e1101_phy_ops = {
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.suspend = generic_suspend,
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.setup_aneg = marvell_setup_aneg,
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.setup_forced = marvell_setup_forced,
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@ -866,13 +966,41 @@ static struct mii_phy_ops marvell_phy_ops = {
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.read_link = marvell_read_link
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};
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static struct mii_phy_def marvell_phy_def = {
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.phy_id = 0x01410c00,
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.phy_id_mask = 0xffffff00,
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.name = "Marvell 88E1101",
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static struct mii_phy_ops marvell88e1111_phy_ops = {
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.init = marvell88e1111_init,
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.suspend = generic_suspend,
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.setup_aneg = marvell_setup_aneg,
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.setup_forced = marvell_setup_forced,
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.poll_link = genmii_poll_link,
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.read_link = marvell_read_link
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};
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/* two revs in darwin for the 88e1101 ... I could use a datasheet
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* to get the proper names...
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*/
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static struct mii_phy_def marvell88e1101v1_phy_def = {
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.phy_id = 0x01410c20,
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.phy_id_mask = 0xfffffff0,
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.name = "Marvell 88E1101v1",
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.features = MII_GBIT_FEATURES,
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.magic_aneg = 1,
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.ops = &marvell_phy_ops
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.ops = &marvell88e1101_phy_ops
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};
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static struct mii_phy_def marvell88e1101v2_phy_def = {
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.phy_id = 0x01410c60,
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.phy_id_mask = 0xfffffff0,
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.name = "Marvell 88E1101v2",
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.features = MII_GBIT_FEATURES,
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.magic_aneg = 1,
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.ops = &marvell88e1101_phy_ops
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};
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static struct mii_phy_def marvell88e1111_phy_def = {
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.phy_id = 0x01410cc0,
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.phy_id_mask = 0xfffffff0,
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.name = "Marvell 88E1111",
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.features = MII_GBIT_FEATURES,
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.magic_aneg = 1,
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.ops = &marvell88e1111_phy_ops
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};
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/* Generic implementation for most 10/100 PHYs */
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@ -895,6 +1023,7 @@ static struct mii_phy_def genmii_phy_def = {
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static struct mii_phy_def* mii_phy_table[] = {
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&bcm5201_phy_def,
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&bcm5221_phy_def,
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&bcm5241_phy_def,
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&bcm5400_phy_def,
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&bcm5401_phy_def,
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&bcm5411_phy_def,
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@ -902,7 +1031,9 @@ static struct mii_phy_def* mii_phy_table[] = {
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&bcm5421k2_phy_def,
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&bcm5461_phy_def,
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&bcm5462V_phy_def,
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&marvell_phy_def,
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&marvell88e1101v1_phy_def,
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&marvell88e1101v2_phy_def,
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&marvell88e1111_phy_def,
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&genmii_phy_def,
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NULL
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};
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@ -30,7 +30,7 @@ struct mii_phy_def
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struct mii_phy
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{
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struct mii_phy_def* def;
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int advertising;
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u32 advertising;
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int mii_id;
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/* 1: autoneg enabled, 0: disabled */
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@ -85,6 +85,9 @@ extern int mii_phy_probe(struct mii_phy *phy, int mii_id);
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#define MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE 0x0001
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#define MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR 0x0004
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/* MII BCM5241 Additional registers */
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#define MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR 0x0008
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/* MII BCM5400 1000-BASET Control register */
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#define MII_BCM5400_GB_CONTROL 0x09
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#define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200
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@ -115,5 +118,7 @@ extern int mii_phy_probe(struct mii_phy *phy, int mii_id);
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#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
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#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
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#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
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#define MII_M1011_PHY_SPEC_STATUS_TX_PAUSE 0x0008
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#define MII_M1011_PHY_SPEC_STATUS_RX_PAUSE 0x0004
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#endif /* __SUNGEM_PHY_H__ */
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