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net: sparx5: fix compiletime_assert for GCC 4.9

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Stephen reports sparx5 broke GCC 4.9 build.
Move the compiletime_assert() out of the static function.
Compile-tested only, no object code changes.

Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Fixes: f3cad2611a ("net: sparx5: add hostmode with phylink support")
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jakub Kicinski 2021-07-31 07:39:17 -07:00 committed by David S. Miller
parent 7fe74dfd41
commit 6387f65e2a
1 changed files with 13 additions and 6 deletions
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19
drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c
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@ -13,7 +13,19 @@
*/
#define VSTAX 73
static void ifh_encode_bitfield(void *ifh, u64 value, u32 pos, u32 width)
#define ifh_encode_bitfield(ifh, value, pos, _width) \
({ \
u32 width = (_width); \
\
/* Max width is 5 bytes - 40 bits. In worst case this will
* spread over 6 bytes - 48 bits
*/ \
compiletime_assert(width <= 40, \
"Unsupported width, must be <= 40"); \
__ifh_encode_bitfield((ifh), (value), (pos), width); \
})
static void __ifh_encode_bitfield(void *ifh, u64 value, u32 pos, u32 width)
{
u8 *ifh_hdr = ifh;
/* Calculate the Start IFH byte position of this IFH bit position */
@ -22,11 +34,6 @@ static void ifh_encode_bitfield(void *ifh, u64 value, u32 pos, u32 width)
u32 bit = (pos % 8);
u64 encode = GENMASK(bit + width - 1, bit) & (value << bit);
/* Max width is 5 bytes - 40 bits. In worst case this will
* spread over 6 bytes - 48 bits
*/
compiletime_assert(width <= 40, "Unsupported width, must be <= 40");
/* The b0-b7 goes into the start IFH byte */
if (encode & 0xFF)
ifh_hdr[byte] |= (u8)((encode & 0xFF));