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RDMA/mlx5: Use mlx5_umr_post_send_wait() to update xlt
Move mlx5_ib_update_mr_pas logic to umr.c, and use mlx5_umr_post_send_wait() instead of mlx5_ib_post_send_wait(). Since it is the last use of mlx5_ib_post_send_wait(), remove it. Link: https://lore.kernel.org/r/55a4972f156aba3592a2fc9bcb33e2059acf295f.1649747695.git.leonro@nvidia.com Signed-off-by: Aharon Landau <aharonl@nvidia.com> Reviewed-by: Michael Guralnik <michaelgur@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Aharon Landau
Jason Gunthorpe
parent
b3d47ebd49
commit
636bdbfc99
@ -1287,8 +1287,6 @@ int mlx5_ib_advise_mr(struct ib_pd *pd,
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struct uverbs_attr_bundle *attrs);
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int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
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int mlx5_ib_dealloc_mw(struct ib_mw *mw);
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int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
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int page_shift, int flags);
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struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
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int access_flags);
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void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
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@ -122,11 +122,6 @@ mlx5_ib_create_mkey_cb(struct mlx5_ib_dev *dev,
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static int mr_cache_max_order(struct mlx5_ib_dev *dev);
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static void queue_adjust_cache_locked(struct mlx5_cache_ent *ent);
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static bool umr_can_use_indirect_mkey(struct mlx5_ib_dev *dev)
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{
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return !MLX5_CAP_GEN(dev->mdev, umr_indirect_mkey_disabled);
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}
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static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
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{
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WARN_ON(xa_load(&dev->odp_mkeys, mlx5_base_mkey(mr->mmkey.key)));
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@ -839,49 +834,6 @@ static int mr_cache_max_order(struct mlx5_ib_dev *dev)
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return MLX5_MAX_UMR_SHIFT;
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}
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static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc)
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{
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struct mlx5_ib_umr_context *context =
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container_of(wc->wr_cqe, struct mlx5_ib_umr_context, cqe);
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context->status = wc->status;
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complete(&context->done);
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}
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static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context)
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{
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context->cqe.done = mlx5_ib_umr_done;
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context->status = -1;
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init_completion(&context->done);
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}
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static int mlx5_ib_post_send_wait(struct mlx5_ib_dev *dev,
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struct mlx5_umr_wr *umrwr)
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{
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struct umr_common *umrc = &dev->umrc;
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const struct ib_send_wr *bad;
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int err;
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struct mlx5_ib_umr_context umr_context;
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mlx5_ib_init_umr_context(&umr_context);
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umrwr->wr.wr_cqe = &umr_context.cqe;
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down(&umrc->sem);
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err = ib_post_send(umrc->qp, &umrwr->wr, &bad);
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if (err) {
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mlx5_ib_warn(dev, "UMR post send failed, err %d\n", err);
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} else {
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wait_for_completion(&umr_context.done);
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if (umr_context.status != IB_WC_SUCCESS) {
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mlx5_ib_warn(dev, "reg umr failed (%u)\n",
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umr_context.status);
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err = -EFAULT;
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}
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}
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up(&umrc->sem);
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return err;
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}
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static struct mlx5_cache_ent *mr_cache_ent_from_order(struct mlx5_ib_dev *dev,
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unsigned int order)
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{
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@ -959,129 +911,6 @@ static struct mlx5_ib_mr *alloc_cacheable_mr(struct ib_pd *pd,
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return mr;
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}
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/*
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* Create a MLX5_IB_SEND_UMR_UPDATE_XLT work request and XLT buffer ready for
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* submission.
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*/
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static void *mlx5_ib_create_xlt_wr(struct mlx5_ib_mr *mr,
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struct mlx5_umr_wr *wr, struct ib_sge *sg,
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size_t nents, size_t ent_size,
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unsigned int flags)
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{
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struct mlx5_ib_dev *dev = mr_to_mdev(mr);
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void *xlt;
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xlt = mlx5r_umr_create_xlt(dev, sg, nents, ent_size, flags);
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memset(wr, 0, sizeof(*wr));
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wr->wr.send_flags = MLX5_IB_SEND_UMR_UPDATE_XLT;
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if (!(flags & MLX5_IB_UPD_XLT_ENABLE))
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wr->wr.send_flags |= MLX5_IB_SEND_UMR_FAIL_IF_FREE;
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wr->wr.sg_list = sg;
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wr->wr.num_sge = 1;
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wr->wr.opcode = MLX5_IB_WR_UMR;
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wr->pd = mr->ibmr.pd;
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wr->mkey = mr->mmkey.key;
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wr->length = mr->ibmr.length;
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wr->virt_addr = mr->ibmr.iova;
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wr->access_flags = mr->access_flags;
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wr->page_shift = mr->page_shift;
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wr->xlt_size = sg->length;
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return xlt;
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}
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static unsigned int xlt_wr_final_send_flags(unsigned int flags)
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{
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unsigned int res = 0;
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if (flags & MLX5_IB_UPD_XLT_ENABLE)
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res |= MLX5_IB_SEND_UMR_ENABLE_MR |
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MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS |
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MLX5_IB_SEND_UMR_UPDATE_TRANSLATION;
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if (flags & MLX5_IB_UPD_XLT_PD || flags & MLX5_IB_UPD_XLT_ACCESS)
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res |= MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS;
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if (flags & MLX5_IB_UPD_XLT_ADDR)
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res |= MLX5_IB_SEND_UMR_UPDATE_TRANSLATION;
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return res;
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}
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int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
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int page_shift, int flags)
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{
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struct mlx5_ib_dev *dev = mr_to_mdev(mr);
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struct device *ddev = &dev->mdev->pdev->dev;
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void *xlt;
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struct mlx5_umr_wr wr;
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struct ib_sge sg;
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int err = 0;
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int desc_size = (flags & MLX5_IB_UPD_XLT_INDIRECT)
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? sizeof(struct mlx5_klm)
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: sizeof(struct mlx5_mtt);
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const int page_align = MLX5_UMR_MTT_ALIGNMENT / desc_size;
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const int page_mask = page_align - 1;
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size_t pages_mapped = 0;
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size_t pages_to_map = 0;
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size_t pages_iter;
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size_t size_to_map = 0;
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size_t orig_sg_length;
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if ((flags & MLX5_IB_UPD_XLT_INDIRECT) &&
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!umr_can_use_indirect_mkey(dev))
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return -EPERM;
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if (WARN_ON(!mr->umem->is_odp))
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return -EINVAL;
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/* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes,
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* so we need to align the offset and length accordingly
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*/
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if (idx & page_mask) {
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npages += idx & page_mask;
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idx &= ~page_mask;
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}
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pages_to_map = ALIGN(npages, page_align);
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xlt = mlx5_ib_create_xlt_wr(mr, &wr, &sg, npages, desc_size, flags);
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if (!xlt)
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return -ENOMEM;
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pages_iter = sg.length / desc_size;
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orig_sg_length = sg.length;
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if (!(flags & MLX5_IB_UPD_XLT_INDIRECT)) {
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struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem);
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size_t max_pages = ib_umem_odp_num_pages(odp) - idx;
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pages_to_map = min_t(size_t, pages_to_map, max_pages);
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}
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wr.page_shift = page_shift;
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for (pages_mapped = 0;
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pages_mapped < pages_to_map && !err;
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pages_mapped += pages_iter, idx += pages_iter) {
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npages = min_t(int, pages_iter, pages_to_map - pages_mapped);
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size_to_map = npages * desc_size;
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dma_sync_single_for_cpu(ddev, sg.addr, sg.length,
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DMA_TO_DEVICE);
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mlx5_odp_populate_xlt(xlt, idx, npages, mr, flags);
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dma_sync_single_for_device(ddev, sg.addr, sg.length,
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DMA_TO_DEVICE);
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sg.length = ALIGN(size_to_map, MLX5_UMR_MTT_ALIGNMENT);
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if (pages_mapped + pages_iter >= pages_to_map)
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wr.wr.send_flags |= xlt_wr_final_send_flags(flags);
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wr.offset = idx * desc_size;
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wr.xlt_size = sg.length;
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err = mlx5_ib_post_send_wait(dev, &wr);
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}
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sg.length = orig_sg_length;
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mlx5r_umr_unmap_free_xlt(dev, xlt, &sg);
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return err;
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}
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/*
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* If ibmr is NULL it will be allocated by reg_create.
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* Else, the given ibmr will be used.
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@ -118,7 +118,7 @@ static void populate_klm(struct mlx5_klm *pklm, size_t idx, size_t nentries,
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*
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* xa_store()
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* mutex_lock(umem_mutex)
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* mlx5_ib_update_xlt()
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* mlx5r_umr_update_xlt()
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* mutex_unlock(umem_mutex)
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* destroy lkey
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*
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@ -199,9 +199,9 @@ static void free_implicit_child_mr_work(struct work_struct *work)
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mlx5r_deref_wait_odp_mkey(&mr->mmkey);
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mutex_lock(&odp_imr->umem_mutex);
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mlx5_ib_update_xlt(mr->parent, ib_umem_start(odp) >> MLX5_IMR_MTT_SHIFT,
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1, 0,
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MLX5_IB_UPD_XLT_INDIRECT | MLX5_IB_UPD_XLT_ATOMIC);
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mlx5r_umr_update_xlt(mr->parent,
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ib_umem_start(odp) >> MLX5_IMR_MTT_SHIFT, 1, 0,
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MLX5_IB_UPD_XLT_INDIRECT | MLX5_IB_UPD_XLT_ATOMIC);
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mutex_unlock(&odp_imr->umem_mutex);
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mlx5_ib_dereg_mr(&mr->ibmr, NULL);
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@ -283,19 +283,19 @@ static bool mlx5_ib_invalidate_range(struct mmu_interval_notifier *mni,
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u64 umr_offset = idx & umr_block_mask;
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if (in_block && umr_offset == 0) {
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mlx5_ib_update_xlt(mr, blk_start_idx,
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idx - blk_start_idx, 0,
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MLX5_IB_UPD_XLT_ZAP |
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MLX5_IB_UPD_XLT_ATOMIC);
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mlx5r_umr_update_xlt(mr, blk_start_idx,
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idx - blk_start_idx, 0,
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MLX5_IB_UPD_XLT_ZAP |
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MLX5_IB_UPD_XLT_ATOMIC);
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in_block = 0;
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}
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}
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}
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if (in_block)
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mlx5_ib_update_xlt(mr, blk_start_idx,
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idx - blk_start_idx + 1, 0,
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MLX5_IB_UPD_XLT_ZAP |
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MLX5_IB_UPD_XLT_ATOMIC);
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mlx5r_umr_update_xlt(mr, blk_start_idx,
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idx - blk_start_idx + 1, 0,
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MLX5_IB_UPD_XLT_ZAP |
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MLX5_IB_UPD_XLT_ATOMIC);
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mlx5_update_odp_stats(mr, invalidations, invalidations);
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@ -442,11 +442,11 @@ static struct mlx5_ib_mr *implicit_get_child_mr(struct mlx5_ib_mr *imr,
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*/
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refcount_set(&mr->mmkey.usecount, 2);
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err = mlx5_ib_update_xlt(mr, 0,
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MLX5_IMR_MTT_ENTRIES,
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PAGE_SHIFT,
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MLX5_IB_UPD_XLT_ZAP |
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MLX5_IB_UPD_XLT_ENABLE);
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err = mlx5r_umr_update_xlt(mr, 0,
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MLX5_IMR_MTT_ENTRIES,
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PAGE_SHIFT,
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MLX5_IB_UPD_XLT_ZAP |
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MLX5_IB_UPD_XLT_ENABLE);
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if (err) {
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ret = ERR_PTR(err);
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goto out_mr;
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@ -513,12 +513,12 @@ struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
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imr->is_odp_implicit = true;
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xa_init(&imr->implicit_children);
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err = mlx5_ib_update_xlt(imr, 0,
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mlx5_imr_ksm_entries,
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MLX5_KSM_PAGE_SHIFT,
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MLX5_IB_UPD_XLT_INDIRECT |
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MLX5_IB_UPD_XLT_ZAP |
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MLX5_IB_UPD_XLT_ENABLE);
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err = mlx5r_umr_update_xlt(imr, 0,
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mlx5_imr_ksm_entries,
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MLX5_KSM_PAGE_SHIFT,
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MLX5_IB_UPD_XLT_INDIRECT |
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MLX5_IB_UPD_XLT_ZAP |
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MLX5_IB_UPD_XLT_ENABLE);
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if (err)
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goto out_mr;
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@ -581,7 +581,7 @@ static int pagefault_real_mr(struct mlx5_ib_mr *mr, struct ib_umem_odp *odp,
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* No need to check whether the MTTs really belong to this MR, since
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* ib_umem_odp_map_dma_and_lock already checks this.
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*/
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ret = mlx5_ib_update_xlt(mr, start_idx, np, page_shift, xlt_flags);
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ret = mlx5r_umr_update_xlt(mr, start_idx, np, page_shift, xlt_flags);
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mutex_unlock(&odp->umem_mutex);
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if (ret < 0) {
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@ -679,9 +679,9 @@ out:
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* next pagefault handler will see the new information.
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*/
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mutex_lock(&odp_imr->umem_mutex);
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err = mlx5_ib_update_xlt(imr, upd_start_idx, upd_len, 0,
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MLX5_IB_UPD_XLT_INDIRECT |
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MLX5_IB_UPD_XLT_ATOMIC);
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err = mlx5r_umr_update_xlt(imr, upd_start_idx, upd_len, 0,
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MLX5_IB_UPD_XLT_INDIRECT |
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MLX5_IB_UPD_XLT_ATOMIC);
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mutex_unlock(&odp_imr->umem_mutex);
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if (err) {
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mlx5_ib_err(mr_to_mdev(imr), "Failed to update PAS\n");
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
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/* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. */
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#include <rdma/ib_umem_odp.h>
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#include "mlx5_ib.h"
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#include "umr.h"
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#include "wr.h"
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@ -465,8 +466,8 @@ static void mlx5r_umr_free_xlt(void *xlt, size_t length)
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free_pages((unsigned long)xlt, get_order(length));
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}
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void mlx5r_umr_unmap_free_xlt(struct mlx5_ib_dev *dev, void *xlt,
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struct ib_sge *sg)
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static void mlx5r_umr_unmap_free_xlt(struct mlx5_ib_dev *dev, void *xlt,
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struct ib_sge *sg)
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{
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struct device *ddev = &dev->mdev->pdev->dev;
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@ -477,8 +478,9 @@ void mlx5r_umr_unmap_free_xlt(struct mlx5_ib_dev *dev, void *xlt,
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/*
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* Create an XLT buffer ready for submission.
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*/
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void *mlx5r_umr_create_xlt(struct mlx5_ib_dev *dev, struct ib_sge *sg,
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size_t nents, size_t ent_size, unsigned int flags)
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static void *mlx5r_umr_create_xlt(struct mlx5_ib_dev *dev, struct ib_sge *sg,
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size_t nents, size_t ent_size,
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unsigned int flags)
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{
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struct device *ddev = &dev->mdev->pdev->dev;
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dma_addr_t dma;
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@ -658,3 +660,84 @@ err:
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mlx5r_umr_unmap_free_xlt(dev, mtt, &sg);
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return err;
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}
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static bool umr_can_use_indirect_mkey(struct mlx5_ib_dev *dev)
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{
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return !MLX5_CAP_GEN(dev->mdev, umr_indirect_mkey_disabled);
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}
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int mlx5r_umr_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
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int page_shift, int flags)
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{
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int desc_size = (flags & MLX5_IB_UPD_XLT_INDIRECT)
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? sizeof(struct mlx5_klm)
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: sizeof(struct mlx5_mtt);
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const int page_align = MLX5_UMR_MTT_ALIGNMENT / desc_size;
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struct mlx5_ib_dev *dev = mr_to_mdev(mr);
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struct device *ddev = &dev->mdev->pdev->dev;
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const int page_mask = page_align - 1;
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struct mlx5r_umr_wqe wqe = {};
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size_t pages_mapped = 0;
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size_t pages_to_map = 0;
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size_t size_to_map = 0;
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size_t orig_sg_length;
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size_t pages_iter;
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struct ib_sge sg;
|
||||
int err = 0;
|
||||
void *xlt;
|
||||
|
||||
if ((flags & MLX5_IB_UPD_XLT_INDIRECT) &&
|
||||
!umr_can_use_indirect_mkey(dev))
|
||||
return -EPERM;
|
||||
|
||||
if (WARN_ON(!mr->umem->is_odp))
|
||||
return -EINVAL;
|
||||
|
||||
/* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes,
|
||||
* so we need to align the offset and length accordingly
|
||||
*/
|
||||
if (idx & page_mask) {
|
||||
npages += idx & page_mask;
|
||||
idx &= ~page_mask;
|
||||
}
|
||||
pages_to_map = ALIGN(npages, page_align);
|
||||
|
||||
xlt = mlx5r_umr_create_xlt(dev, &sg, npages, desc_size, flags);
|
||||
if (!xlt)
|
||||
return -ENOMEM;
|
||||
|
||||
pages_iter = sg.length / desc_size;
|
||||
orig_sg_length = sg.length;
|
||||
|
||||
if (!(flags & MLX5_IB_UPD_XLT_INDIRECT)) {
|
||||
struct ib_umem_odp *odp = to_ib_umem_odp(mr->umem);
|
||||
size_t max_pages = ib_umem_odp_num_pages(odp) - idx;
|
||||
|
||||
pages_to_map = min_t(size_t, pages_to_map, max_pages);
|
||||
}
|
||||
|
||||
mlx5r_umr_set_update_xlt_ctrl_seg(&wqe.ctrl_seg, flags, &sg);
|
||||
mlx5r_umr_set_update_xlt_mkey_seg(dev, &wqe.mkey_seg, mr, page_shift);
|
||||
mlx5r_umr_set_update_xlt_data_seg(&wqe.data_seg, &sg);
|
||||
|
||||
for (pages_mapped = 0;
|
||||
pages_mapped < pages_to_map && !err;
|
||||
pages_mapped += pages_iter, idx += pages_iter) {
|
||||
npages = min_t(int, pages_iter, pages_to_map - pages_mapped);
|
||||
size_to_map = npages * desc_size;
|
||||
dma_sync_single_for_cpu(ddev, sg.addr, sg.length,
|
||||
DMA_TO_DEVICE);
|
||||
mlx5_odp_populate_xlt(xlt, idx, npages, mr, flags);
|
||||
dma_sync_single_for_device(ddev, sg.addr, sg.length,
|
||||
DMA_TO_DEVICE);
|
||||
sg.length = ALIGN(size_to_map, MLX5_UMR_MTT_ALIGNMENT);
|
||||
|
||||
if (pages_mapped + pages_iter >= pages_to_map)
|
||||
mlx5r_umr_final_update_xlt(dev, &wqe, mr, &sg, flags);
|
||||
mlx5r_umr_update_offset(&wqe.ctrl_seg, idx * desc_size);
|
||||
err = mlx5r_umr_post_send_wait(dev, mr->mmkey.key, &wqe, true);
|
||||
}
|
||||
sg.length = orig_sg_length;
|
||||
mlx5r_umr_unmap_free_xlt(dev, xlt, &sg);
|
||||
return err;
|
||||
}
|
||||
|
||||
@ -94,10 +94,8 @@ struct mlx5r_umr_wqe {
|
||||
int mlx5r_umr_revoke_mr(struct mlx5_ib_mr *mr);
|
||||
int mlx5r_umr_rereg_pd_access(struct mlx5_ib_mr *mr, struct ib_pd *pd,
|
||||
int access_flags);
|
||||
void *mlx5r_umr_create_xlt(struct mlx5_ib_dev *dev, struct ib_sge *sg,
|
||||
size_t nents, size_t ent_size, unsigned int flags);
|
||||
void mlx5r_umr_unmap_free_xlt(struct mlx5_ib_dev *dev, void *xlt,
|
||||
struct ib_sge *sg);
|
||||
int mlx5r_umr_update_mr_pas(struct mlx5_ib_mr *mr, unsigned int flags);
|
||||
int mlx5r_umr_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
|
||||
int page_shift, int flags);
|
||||
|
||||
#endif /* _MLX5_IB_UMR_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user