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arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARM
The architecture reference manual refers to the field in bits 23:20 of ID_AA64ISAR0_EL1 with the name "atomic" but the kernel defines for this bitfield use the name "atomics". Bring the two into sync to make it easier to cross reference with the specification. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220503170233.507788-7-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -749,7 +749,7 @@
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#define ID_AA64ISAR0_SM3_SHIFT 36
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#define ID_AA64ISAR0_SHA3_SHIFT 32
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#define ID_AA64ISAR0_RDM_SHIFT 28
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#define ID_AA64ISAR0_ATOMICS_SHIFT 20
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#define ID_AA64ISAR0_ATOMIC_SHIFT 20
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#define ID_AA64ISAR0_CRC32_SHIFT 16
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#define ID_AA64ISAR0_SHA2_SHIFT 12
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#define ID_AA64ISAR0_SHA1_SHIFT 8
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@ -200,7 +200,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMIC_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
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@ -2013,7 +2013,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.type = ARM64_CPUCAP_SYSTEM_FEATURE,
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.matches = has_cpuid_feature,
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.sys_reg = SYS_ID_AA64ISAR0_EL1,
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.field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
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.field_pos = ID_AA64ISAR0_ATOMIC_SHIFT,
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.field_width = 4,
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.sign = FTR_UNSIGNED,
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.min_field_value = 2,
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@ -2520,7 +2520,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
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@ -163,7 +163,7 @@
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ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA1) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA2) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_CRC32) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_ATOMICS) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_ATOMIC) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_RDM) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA3) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_SM3) | \
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