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iio: adc: ti-tlc4541: Fix alignment for DMA safety

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____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: ac2bec9d58 ("iio: adc: tlc4541: add support for TI tlc4541 adc")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-40-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:19 +01:00
parent a2105d87eb
commit 62fa19bf48
1 changed files with 2 additions and 2 deletions
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4
drivers/iio/adc/ti-tlc4541.c
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@ -37,12 +37,12 @@ struct tlc4541_state {
struct spi_message scan_single_msg;
/*
* DMA (thus cache coherency maintenance) requires the
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
* 2 bytes data + 6 bytes padding + 8 bytes timestamp when
* call iio_push_to_buffers_with_timestamp.
*/
__be16 rx_buf[8] ____cacheline_aligned;
__be16 rx_buf[8] __aligned(IIO_DMA_MINALIGN);
};
struct tlc4541_chip_info {