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synced 2024-12-19 09:04:51 +08:00
drm/i915: Remove 'outstanding_lazy_seqno'
The OLS value is now obsolete. Exactly the same value is guarateed to be always available as PLR->seqno. Thus it is safe to remove the OLS completely. And also to rename the PLR to OLR to keep the 'outstanding lazy ...' naming convention valid. For: VIZ-4377 Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Thomas Daniel <Thomas.Daniel@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
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ff8658850a
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6259cead57
@ -1164,7 +1164,7 @@ i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
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BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
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ret = 0;
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if (seqno == ring->outstanding_lazy_seqno)
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if (seqno == i915_gem_request_get_seqno(ring->outstanding_lazy_request))
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ret = i915_add_request(ring, NULL);
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return ret;
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@ -2421,7 +2421,7 @@ int __i915_add_request(struct intel_engine_cs *ring,
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u32 request_ring_position, request_start;
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int ret;
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request = ring->preallocated_lazy_request;
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request = ring->outstanding_lazy_request;
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if (WARN_ON(request == NULL))
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return -ENOMEM;
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@ -2466,7 +2466,6 @@ int __i915_add_request(struct intel_engine_cs *ring,
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return ret;
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}
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request->seqno = intel_ring_get_seqno(ring);
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request->ring = ring;
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request->head = request_start;
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request->tail = request_ring_position;
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@ -2503,8 +2502,7 @@ int __i915_add_request(struct intel_engine_cs *ring,
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}
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trace_i915_gem_request_add(ring, request->seqno);
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ring->outstanding_lazy_seqno = 0;
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ring->preallocated_lazy_request = NULL;
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ring->outstanding_lazy_request = NULL;
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i915_queue_hangcheck(ring->dev);
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@ -2689,9 +2687,8 @@ static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
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i915_gem_free_request(request);
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}
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/* These may not have been flush before the reset, do so now */
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i915_gem_request_assign(&ring->preallocated_lazy_request, NULL);
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ring->outstanding_lazy_seqno = 0;
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/* This may not have been flushed before the reset, so clean it now */
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i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
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}
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void i915_gem_restore_fences(struct drm_device *dev)
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@ -1211,7 +1211,9 @@ i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,
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return ret;
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}
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trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
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trace_i915_gem_ring_dispatch(ring,
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i915_gem_request_get_seqno(intel_ring_get_request(ring)),
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flags);
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i915_gem_execbuffer_move_to_active(vmas, ring);
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i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
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@ -9910,7 +9910,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
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if (ret)
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goto cleanup_unpin;
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work->flip_queued_seqno = intel_ring_get_seqno(ring);
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work->flip_queued_seqno =
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i915_gem_request_get_seqno(intel_ring_get_request(ring));
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work->flip_queued_ring = ring;
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}
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@ -876,22 +876,14 @@ void intel_lr_context_unpin(struct intel_engine_cs *ring,
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}
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}
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static int logical_ring_alloc_seqno(struct intel_engine_cs *ring,
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struct intel_context *ctx)
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static int logical_ring_alloc_request(struct intel_engine_cs *ring,
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struct intel_context *ctx)
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{
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struct drm_i915_gem_request *request;
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int ret;
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/* XXX: The aim is to replace seqno values with request structures.
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* A step along the way is to switch to using the PLR in preference
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* to the OLS. That requires the PLR to only be valid when the OLS is
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* also valid. I.e., the two must be kept in step. */
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if (ring->outstanding_lazy_seqno) {
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WARN_ON(ring->preallocated_lazy_request == NULL);
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if (ring->outstanding_lazy_request)
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return 0;
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}
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WARN_ON(ring->preallocated_lazy_request != NULL);
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request = kmalloc(sizeof(*request), GFP_KERNEL);
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if (request == NULL)
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@ -907,7 +899,7 @@ static int logical_ring_alloc_seqno(struct intel_engine_cs *ring,
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kref_init(&request->ref);
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ret = i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
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ret = i915_gem_get_seqno(ring->dev, &request->seqno);
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if (ret) {
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intel_lr_context_unpin(ring, ctx);
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kfree(request);
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@ -921,7 +913,7 @@ static int logical_ring_alloc_seqno(struct intel_engine_cs *ring,
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request->ctx = ctx;
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i915_gem_context_reference(request->ctx);
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ring->preallocated_lazy_request = request;
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ring->outstanding_lazy_request = request;
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return 0;
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}
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@ -1098,7 +1090,7 @@ int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords)
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return ret;
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/* Preallocate the olr before touching the ring */
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ret = logical_ring_alloc_seqno(ring, ringbuf->FIXME_lrc_ctx);
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ret = logical_ring_alloc_request(ring, ringbuf->FIXME_lrc_ctx);
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if (ret)
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return ret;
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@ -1351,7 +1343,8 @@ static int gen8_emit_request(struct intel_ringbuffer *ringbuf)
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(ring->status_page.gfx_addr +
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(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
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intel_logical_ring_emit(ringbuf, 0);
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intel_logical_ring_emit(ringbuf, ring->outstanding_lazy_seqno);
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intel_logical_ring_emit(ringbuf,
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i915_gem_request_get_seqno(ring->outstanding_lazy_request));
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intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
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intel_logical_ring_emit(ringbuf, MI_NOOP);
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intel_logical_ring_advance_and_submit(ringbuf);
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@ -1376,8 +1369,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *ring)
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intel_logical_ring_stop(ring);
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WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
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i915_gem_request_assign(&ring->preallocated_lazy_request, NULL);
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ring->outstanding_lazy_seqno = 0;
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i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
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if (ring->cleanup)
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ring->cleanup(ring);
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@ -911,17 +911,20 @@ static int gen8_rcs_signal(struct intel_engine_cs *signaller,
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return ret;
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for_each_ring(waiter, dev_priv, i) {
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u32 seqno;
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u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
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if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
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continue;
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seqno = i915_gem_request_get_seqno(
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signaller->outstanding_lazy_request);
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intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
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intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
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PIPE_CONTROL_QW_WRITE |
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PIPE_CONTROL_FLUSH_ENABLE);
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intel_ring_emit(signaller, lower_32_bits(gtt_offset));
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intel_ring_emit(signaller, upper_32_bits(gtt_offset));
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intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
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intel_ring_emit(signaller, seqno);
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intel_ring_emit(signaller, 0);
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intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
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MI_SEMAPHORE_TARGET(waiter->id));
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@ -949,16 +952,19 @@ static int gen8_xcs_signal(struct intel_engine_cs *signaller,
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return ret;
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for_each_ring(waiter, dev_priv, i) {
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u32 seqno;
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u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
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if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
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continue;
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seqno = i915_gem_request_get_seqno(
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signaller->outstanding_lazy_request);
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intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
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MI_FLUSH_DW_OP_STOREDW);
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intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
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MI_FLUSH_DW_USE_GTT);
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intel_ring_emit(signaller, upper_32_bits(gtt_offset));
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intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
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intel_ring_emit(signaller, seqno);
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intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
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MI_SEMAPHORE_TARGET(waiter->id));
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intel_ring_emit(signaller, 0);
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@ -987,9 +993,11 @@ static int gen6_signal(struct intel_engine_cs *signaller,
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for_each_ring(useless, dev_priv, i) {
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u32 mbox_reg = signaller->semaphore.mbox.signal[i];
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if (mbox_reg != GEN6_NOSYNC) {
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u32 seqno = i915_gem_request_get_seqno(
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signaller->outstanding_lazy_request);
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intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
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intel_ring_emit(signaller, mbox_reg);
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intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
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intel_ring_emit(signaller, seqno);
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}
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}
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@ -1024,7 +1032,8 @@ gen6_add_request(struct intel_engine_cs *ring)
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intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
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intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
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intel_ring_emit(ring, ring->outstanding_lazy_seqno);
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intel_ring_emit(ring,
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i915_gem_request_get_seqno(ring->outstanding_lazy_request));
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intel_ring_emit(ring, MI_USER_INTERRUPT);
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__intel_ring_advance(ring);
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@ -1142,7 +1151,8 @@ pc_render_add_request(struct intel_engine_cs *ring)
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PIPE_CONTROL_WRITE_FLUSH |
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PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
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intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
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intel_ring_emit(ring, ring->outstanding_lazy_seqno);
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intel_ring_emit(ring,
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i915_gem_request_get_seqno(ring->outstanding_lazy_request));
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intel_ring_emit(ring, 0);
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
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@ -1161,7 +1171,8 @@ pc_render_add_request(struct intel_engine_cs *ring)
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PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
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PIPE_CONTROL_NOTIFY);
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intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
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intel_ring_emit(ring, ring->outstanding_lazy_seqno);
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intel_ring_emit(ring,
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i915_gem_request_get_seqno(ring->outstanding_lazy_request));
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intel_ring_emit(ring, 0);
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__intel_ring_advance(ring);
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@ -1401,7 +1412,8 @@ i9xx_add_request(struct intel_engine_cs *ring)
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intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
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intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
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intel_ring_emit(ring, ring->outstanding_lazy_seqno);
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intel_ring_emit(ring,
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i915_gem_request_get_seqno(ring->outstanding_lazy_request));
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intel_ring_emit(ring, MI_USER_INTERRUPT);
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__intel_ring_advance(ring);
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@ -1870,8 +1882,7 @@ void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
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intel_unpin_ringbuffer_obj(ringbuf);
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intel_destroy_ringbuffer_obj(ringbuf);
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i915_gem_request_assign(&ring->preallocated_lazy_request, NULL);
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ring->outstanding_lazy_seqno = 0;
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i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
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if (ring->cleanup)
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ring->cleanup(ring);
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@ -2004,7 +2015,7 @@ int intel_ring_idle(struct intel_engine_cs *ring)
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int ret;
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/* We need to add any requests required to flush the objects and ring */
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if (ring->outstanding_lazy_seqno) {
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if (ring->outstanding_lazy_request) {
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ret = i915_add_request(ring, NULL);
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if (ret)
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return ret;
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@ -2022,22 +2033,13 @@ int intel_ring_idle(struct intel_engine_cs *ring)
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}
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static int
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intel_ring_alloc_seqno(struct intel_engine_cs *ring)
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intel_ring_alloc_request(struct intel_engine_cs *ring)
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{
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int ret;
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struct drm_i915_gem_request *request;
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/* XXX: The aim is to replace seqno values with request structures.
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* A step along the way is to switch to using the PLR in preference
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* to the OLS. That requires the PLR to only be valid when the OLS
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* is also valid. I.e., the two must be kept in step. */
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if (ring->outstanding_lazy_seqno) {
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WARN_ON(ring->preallocated_lazy_request == NULL);
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if (ring->outstanding_lazy_request)
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return 0;
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}
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WARN_ON(ring->preallocated_lazy_request != NULL);
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request = kmalloc(sizeof(*request), GFP_KERNEL);
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if (request == NULL)
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@ -2045,13 +2047,13 @@ intel_ring_alloc_seqno(struct intel_engine_cs *ring)
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kref_init(&request->ref);
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ret = i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
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ret = i915_gem_get_seqno(ring->dev, &request->seqno);
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if (ret) {
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kfree(request);
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return ret;
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}
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ring->preallocated_lazy_request = request;
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ring->outstanding_lazy_request = request;
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return 0;
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}
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@ -2092,7 +2094,7 @@ int intel_ring_begin(struct intel_engine_cs *ring,
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return ret;
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/* Preallocate the olr before touching the ring */
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ret = intel_ring_alloc_seqno(ring);
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ret = intel_ring_alloc_request(ring);
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if (ret)
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return ret;
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@ -2127,7 +2129,7 @@ void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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BUG_ON(ring->outstanding_lazy_seqno);
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BUG_ON(ring->outstanding_lazy_request);
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if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
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I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
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@ -267,8 +267,7 @@ struct intel_engine_cs {
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/**
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* Do we have some not yet emitted requests outstanding?
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*/
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struct drm_i915_gem_request *preallocated_lazy_request;
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u32 outstanding_lazy_seqno;
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struct drm_i915_gem_request *outstanding_lazy_request;
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bool gpu_caches_dirty;
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bool fbc_dirty;
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@ -436,17 +435,11 @@ static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
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return ringbuf->tail;
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}
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static inline u32 intel_ring_get_seqno(struct intel_engine_cs *ring)
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{
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BUG_ON(ring->outstanding_lazy_seqno == 0);
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return ring->outstanding_lazy_seqno;
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}
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static inline struct drm_i915_gem_request *
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intel_ring_get_request(struct intel_engine_cs *ring)
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{
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BUG_ON(ring->preallocated_lazy_request == NULL);
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return ring->preallocated_lazy_request;
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BUG_ON(ring->outstanding_lazy_request == NULL);
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return ring->outstanding_lazy_request;
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}
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static inline void i915_trace_irq_get(struct intel_engine_cs *ring, u32 seqno)
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