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arm64: renesas: r8a7795: Sound SSI PIO support
This patch adds SSI for PIO sound support Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -52,6 +52,29 @@
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clock-frequency = <0>;
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};
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/*
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* The external audio clocks are configured as 0 Hz fixed frequency
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* clocks by default.
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* Boards that provide audio clocks should override them.
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*/
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audio_clk_a: audio_clk_a {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_b: audio_clk_b {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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audio_clk_c: audio_clk_c {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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@ -534,5 +557,77 @@
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power-domains = <&cpg>;
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status = "disabled";
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};
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rcar_sound: sound@ec500000 {
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/*
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* #sound-dai-cells is required
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*
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* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
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* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
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*/
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/*
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* #clock-cells is required for audio_clkout0/1/2/3
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*
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* clkout : #clock-cells = <0>; <&rcar_sound>;
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* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
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*/
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compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3";
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reg = <0 0xec500000 0 0x1000>, /* SCU */
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<0 0xec5a0000 0 0x100>, /* ADG */
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<0 0xec540000 0 0x1000>, /* SSIU */
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<0 0xec541000 0 0x280>, /* SSI */
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<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
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reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
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clocks = <&cpg CPG_MOD 1005>,
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<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
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<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
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<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
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<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
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<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
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<&audio_clk_a>, <&audio_clk_b>,
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<&audio_clk_c>,
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<&cpg CPG_CORE R8A7795_CLK_S0D4>;
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clock-names = "ssi-all",
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"ssi.9", "ssi.8", "ssi.7", "ssi.6",
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"ssi.5", "ssi.4", "ssi.3", "ssi.2",
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"ssi.1", "ssi.0",
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"clk_a", "clk_b", "clk_c", "clk_i";
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power-domains = <&cpg>;
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status = "disabled";
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rcar_sound,ssi {
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ssi0: ssi@0 {
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interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
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};
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ssi1: ssi@1 {
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interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
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};
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ssi2: ssi@2 {
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interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
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};
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ssi3: ssi@3 {
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interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
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};
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ssi4: ssi@4 {
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interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
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};
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ssi5: ssi@5 {
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interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
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};
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ssi6: ssi@6 {
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interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
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};
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ssi7: ssi@7 {
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interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
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};
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ssi8: ssi@8 {
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interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
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};
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ssi9: ssi@9 {
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interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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};
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};
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