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spi: spi_bfin: update handling of delay-after-deselect
Move cs_chg_udelay handling (specific to this driver) to cs_deactive(), fixing a bug when some SPI LCD driver needs delay after cs_deactive. Fix bug reported by Cameron Barfield <cbarfield@cyberdata.net> https://blackfin.uclinux.org/gf/project/uclinux-dist/forum/?action=ForumBrowse&forum_id=39&_forum_action=ForumMessageBrowse&thread_id=23630&feedback=Message%20replied. Cc: Cameron Barfield <cbarfield@cyberdata.net> Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -132,7 +132,7 @@ struct chip_data {
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u8 enable_dma;
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u8 enable_dma;
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u8 bits_per_word; /* 8 or 16 */
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u8 bits_per_word; /* 8 or 16 */
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u8 cs_change_per_word;
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u8 cs_change_per_word;
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u8 cs_chg_udelay;
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u16 cs_chg_udelay; /* Some devices require > 255usec delay */
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void (*write) (struct driver_data *);
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void (*write) (struct driver_data *);
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void (*read) (struct driver_data *);
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void (*read) (struct driver_data *);
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void (*duplex) (struct driver_data *);
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void (*duplex) (struct driver_data *);
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@ -211,6 +211,10 @@ static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
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flag |= (chip->flag << 8);
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flag |= (chip->flag << 8);
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write_FLAG(drv_data, flag);
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write_FLAG(drv_data, flag);
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/* Move delay here for consistency */
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if (chip->cs_chg_udelay)
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udelay(chip->cs_chg_udelay);
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}
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}
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#define MAX_SPI_SSEL 7
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#define MAX_SPI_SSEL 7
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@ -307,10 +311,9 @@ static void u8_cs_chg_writer(struct driver_data *drv_data)
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
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while (read_STAT(drv_data) & BIT_STAT_TXS)
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while (read_STAT(drv_data) & BIT_STAT_TXS)
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continue;
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continue;
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cs_deactive(drv_data, chip);
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cs_deactive(drv_data, chip);
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if (chip->cs_chg_udelay)
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udelay(chip->cs_chg_udelay);
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++drv_data->tx;
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++drv_data->tx;
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}
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}
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}
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}
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@ -359,9 +362,6 @@ static void u8_cs_chg_reader(struct driver_data *drv_data)
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while (drv_data->rx < drv_data->rx_end - 1) {
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while (drv_data->rx < drv_data->rx_end - 1) {
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cs_deactive(drv_data, chip);
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cs_deactive(drv_data, chip);
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if (chip->cs_chg_udelay)
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udelay(chip->cs_chg_udelay);
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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continue;
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cs_active(drv_data, chip);
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cs_active(drv_data, chip);
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@ -412,10 +412,9 @@ static void u8_cs_chg_duplex(struct driver_data *drv_data)
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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continue;
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*(u8 *) (drv_data->rx) = read_RDBR(drv_data);
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*(u8 *) (drv_data->rx) = read_RDBR(drv_data);
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cs_deactive(drv_data, chip);
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cs_deactive(drv_data, chip);
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if (chip->cs_chg_udelay)
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udelay(chip->cs_chg_udelay);
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++drv_data->rx;
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++drv_data->rx;
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++drv_data->tx;
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++drv_data->tx;
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}
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}
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@ -452,10 +451,9 @@ static void u16_cs_chg_writer(struct driver_data *drv_data)
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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while ((read_STAT(drv_data) & BIT_STAT_TXS))
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while ((read_STAT(drv_data) & BIT_STAT_TXS))
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continue;
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continue;
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cs_deactive(drv_data, chip);
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cs_deactive(drv_data, chip);
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if (chip->cs_chg_udelay)
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udelay(chip->cs_chg_udelay);
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drv_data->tx += 2;
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drv_data->tx += 2;
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}
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}
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}
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}
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@ -504,9 +502,6 @@ static void u16_cs_chg_reader(struct driver_data *drv_data)
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while (drv_data->rx < drv_data->rx_end - 2) {
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while (drv_data->rx < drv_data->rx_end - 2) {
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cs_deactive(drv_data, chip);
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cs_deactive(drv_data, chip);
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if (chip->cs_chg_udelay)
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udelay(chip->cs_chg_udelay);
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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continue;
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cs_active(drv_data, chip);
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cs_active(drv_data, chip);
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@ -557,10 +552,9 @@ static void u16_cs_chg_duplex(struct driver_data *drv_data)
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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continue;
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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cs_deactive(drv_data, chip);
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cs_deactive(drv_data, chip);
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if (chip->cs_chg_udelay)
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udelay(chip->cs_chg_udelay);
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drv_data->rx += 2;
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drv_data->rx += 2;
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drv_data->tx += 2;
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drv_data->tx += 2;
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}
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}
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@ -162,7 +162,7 @@ struct bfin5xx_spi_chip {
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u8 enable_dma;
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u8 enable_dma;
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u8 bits_per_word;
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u8 bits_per_word;
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u8 cs_change_per_word;
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u8 cs_change_per_word;
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u8 cs_chg_udelay;
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u16 cs_chg_udelay; /* Some devices require 16-bit delays */
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};
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};
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#endif /* _SPI_CHANNEL_H_ */
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#endif /* _SPI_CHANNEL_H_ */
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