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Minor cleanup of ARM64 DTS for v5.19

Browse Source 
Align SPI NOR node names and freq-table-hz to DT schema. Drop
 unused/undocumented dma-channels/dma-requests.
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Merge tag 'dt64-cleanup-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt

Minor cleanup of ARM64 DTS for v5.19

Align SPI NOR node names and freq-table-hz to DT schema. Drop
unused/undocumented dma-channels/dma-requests.

* tag 'dt64-cleanup-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: broadcom: drop useless 'dma-channels/requests' properties
  arm64: dts: stratix10/agilex: drop useless 'dma-channels/requests' properties
  arm64: dts: marvell: align SPI NOR node name with dtschema
  arm64: dts: microchip: align SPI NOR node name with dtschema
  arm64: dts: hisilicon: align 'freq-table-hz' with dtschema in UFS

Link: https://lore.kernel.org/r/20220506081438.149192-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-05-06 22:12:37 +02:00
commit 620b2c35ab
22 changed files with 25 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View File

@ -346,8 +346,6 @@
<0 88 4>,
<0 89 4>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
clock-names = "apb_pclk";
resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;

2
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
View File

@ -289,8 +289,6 @@
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
clocks = <&iprocslow>;
clock-names = "apb_pclk";
};

2
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
View File

@ -556,8 +556,6 @@
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
clocks = <&hsls_div2_clk>;
clock-names = "apb_pclk";
iommus = <&smmu 0x6000 0x0000>;

4
arch/arm64/boot/dts/hisilicon/hi3660.dtsi
View File

@ -1045,8 +1045,8 @@
clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
clock-names = "ref_clk", "phy_clk";
freq-table-hz = <0 0
0 0>;
freq-table-hz = <0 0>,
<0 0>;
/* offset: 0x84; bit: 12 */
resets = <&crg_rst 0x84 12>;
reset-names = "rst";

4
arch/arm64/boot/dts/hisilicon/hi3670.dtsi
View File

@ -671,8 +671,8 @@
clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
<&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
clock-names = "ref_clk", "phy_clk";
freq-table-hz = <0 0
0 0>;
freq-table-hz = <0 0>,
<0 0>;
/* offset: 0x84; bit: 12 */
resets = <&crg_rst 0x84 12>;
reset-names = "rst";

2
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
View File

@ -350,8 +350,6 @@
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
reset-names = "dma", "dma-ocp";
clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;

2
arch/arm64/boot/dts/marvell/armada-3720-db.dts
View File

@ -164,7 +164,7 @@
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins>;
m25p80@0 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <108000000>;

2
arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
View File

@ -211,7 +211,7 @@
assigned-clock-parents = <&tbg 1>;
assigned-clock-rates = <20000000>;
spi-flash@0 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";

2
arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
View File

@ -99,7 +99,7 @@
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins>;
m25p80@0 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <54000000>;

4
arch/arm64/boot/dts/marvell/armada-7040-db.dts
View File

@ -83,7 +83,7 @@
&spi0 {
status = "okay";
spi-flash@0 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
@ -186,7 +186,7 @@
&cp0_spi1 {
status = "okay";
spi-flash@0 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <20000000>;

2
arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
View File

@ -155,7 +155,7 @@
pinctrl-names = "default";
pinctrl-0 = <&cp0_spi1_pins>;
spi-flash@0 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";

2
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
View File

@ -589,7 +589,7 @@
pinctrl-0 = <&cp1_spi1_pins>;
status = "okay";
spi-flash@0 {
flash@0 {
compatible = "st,w25q32";
spi-max-frequency = <50000000>;
reg = <0>;

4
arch/arm64/boot/dts/marvell/armada-8040-db.dts
View File

@ -72,7 +72,7 @@
&spi0 {
status = "okay";
spi-flash@0 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
@ -238,7 +238,7 @@
&cp1_spi1 {
status = "okay";
spi-flash@0 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
spi-max-frequency = <20000000>;

2
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
View File

@ -360,7 +360,7 @@
pinctrl-0 = <&cp1_spi1_pins>;
status = "okay";
spi-flash@0 {
flash@0 {
compatible = "st,w25q32";
spi-max-frequency = <50000000>;
reg = <0>;

2
arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts
View File

@ -185,7 +185,7 @@
&spi0 {
status = "okay";
spi-flash@0 {
flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";

2
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
View File

@ -175,7 +175,7 @@
<0x2000000 0x1000000>; /* CS0 */
status = "okay";
spi-flash@0 {
flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";

2
arch/arm64/boot/dts/marvell/cn9130-db.dtsi
View File

@ -310,7 +310,7 @@
pinctrl-0 = <&cp0_spi0_pins>;
reg = <0x700680 0x50>;
spi-flash@0 {
flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";

2
arch/arm64/boot/dts/marvell/cn9131-db.dtsi
View File

@ -137,7 +137,7 @@
pinctrl-0 = <&cp1_spi0_pins>;
reg = <0x700680 0x50>;
spi-flash@0 {
flash@0 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "jedec,spi-nor";

2
arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
View File

@ -19,7 +19,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <14>; /* CS14 */
spi-flash@6 {
flash@6 {
compatible = "spi-nand";
pinctrl-0 = <&cs14_pins>;
pinctrl-names = "default";

4
arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
View File

@ -47,7 +47,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>; /* CS0 */
spi-flash@9 {
flash@9 {
compatible = "jedec,spi-nor";
spi-max-frequency = <8000000>;
reg = <0x9>; /* SPI */
@ -59,7 +59,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>; /* CS1 */
spi-flash@9 {
flash@9 {
compatible = "spi-nand";
pinctrl-0 = <&cs1_pins>;
pinctrl-names = "default";

4
arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
View File

@ -274,7 +274,7 @@
&spi0 {
status = "okay";
spi-flash@0 {
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <8000000>;
reg = <0>;
@ -289,7 +289,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>; /* CS0 */
spi-flash@9 {
flash@9 {
compatible = "jedec,spi-nor";
spi-max-frequency = <8000000>;
reg = <0x9>; /* SPI */

4
arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
View File

@ -89,7 +89,7 @@
&spi0 {
status = "okay";
spi-flash@0 {
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <8000000>;
reg = <0>;
@ -104,7 +104,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>; /* CS0 */
spi-flash@9 {
flash@9 {
compatible = "jedec,spi-nor";
spi-max-frequency = <8000000>;
reg = <0x9>; /* SPI */