mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-24 03:24:55 +08:00
drm/nouveau/sw: remove dependence on namedb/engctx lookup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
590801c1a3
commit
6157091177
@ -109,7 +109,6 @@ struct nvkm_sclass {
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struct nvkm_oclass {
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s32 handle;
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struct nvkm_ofuncs * const ofuncs;
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struct nvkm_omthds * const omthds;
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int (*ctor)(const struct nvkm_oclass *, void *data, u32 size,
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struct nvkm_object **);
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@ -135,12 +134,6 @@ nv_pclass(struct nvkm_object *parent, u32 oclass)
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return parent;
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}
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struct nvkm_omthds {
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u32 start;
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u32 limit;
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int (*call)(struct nvkm_object *, u32, void *, u32);
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};
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struct nvkm_ofuncs {
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int (*ctor)(struct nvkm_object *, struct nvkm_object *,
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struct nvkm_oclass *, void *data, u32 size,
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@ -171,24 +164,4 @@ int nvkm_object_old(struct nvkm_object *, struct nvkm_object *,
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void nvkm_object_ref(struct nvkm_object *, struct nvkm_object **);
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int nvkm_object_inc(struct nvkm_object *);
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int nvkm_object_dec(struct nvkm_object *, bool suspend);
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static inline int
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nv_exec(void *obj, u32 mthd, void *data, u32 size)
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{
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struct nvkm_omthds *method = nv_oclass(obj)->omthds;
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while (method && method->call) {
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if (mthd >= method->start && mthd <= method->limit)
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return method->call(obj, mthd, data, size);
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method++;
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}
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return -EINVAL;
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}
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static inline int
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nv_call(void *obj, u32 mthd, u32 data)
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{
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return nv_exec(obj, mthd, &data, sizeof(data));
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}
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#endif
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@ -4,10 +4,16 @@
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struct nvkm_sw {
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struct nvkm_engine engine;
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struct list_head chan;
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};
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bool nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data);
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#define nvkm_sw_create(p,e,c,d) \
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nvkm_engine_create((p), (e), (c), true, "SW", "software", (d))
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nvkm_sw_ctor((p), (e), (c), sizeof(**d), (void **)d)
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int
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nvkm_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, int length, void **pobject);
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#define nvkm_sw_destroy(d) \
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nvkm_engine_destroy(&(d)->engine)
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#define nvkm_sw_init(d) \
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@ -174,7 +174,6 @@ int nv50_disp_main_ctor(struct nvkm_object *, struct nvkm_object *,
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struct nvkm_oclass *, void *, u32,
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struct nvkm_object **);
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void nv50_disp_main_dtor(struct nvkm_object *);
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extern struct nvkm_omthds nv50_disp_main_omthds[];
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extern struct nvkm_oclass nv50_disp_cclass;
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void nv50_disp_mthd_chan(struct nv50_disp *, int debug, int head,
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const struct nv50_disp_mthd_chan *);
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@ -31,6 +31,7 @@
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#include <subdev/fb.h>
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#include <subdev/mmu.h>
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#include <subdev/timer.h>
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#include <engine/sw.h>
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#include <nvif/class.h>
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#include <nvif/ioctl.h>
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@ -474,32 +475,6 @@ gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine,
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schedule_work(&fifo->fault);
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}
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static int
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gf100_fifo_swmthd(struct gf100_fifo *fifo, u32 chid, u32 mthd, u32 data)
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{
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struct gf100_fifo_chan *chan = NULL;
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struct nvkm_handle *bind;
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unsigned long flags;
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int ret = -EINVAL;
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spin_lock_irqsave(&fifo->base.lock, flags);
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if (likely(chid >= fifo->base.min && chid <= fifo->base.max))
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chan = (void *)fifo->base.channel[chid];
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if (unlikely(!chan))
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goto out;
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bind = nvkm_namedb_get_class(nv_namedb(chan), NVIF_IOCTL_NEW_V0_SW_GF100);
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if (likely(bind)) {
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if (!mthd || !nv_call(bind->object, mthd, data))
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ret = 0;
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nvkm_namedb_put(bind);
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}
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out:
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spin_unlock_irqrestore(&fifo->base.lock, flags);
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return ret;
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}
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static const struct nvkm_enum
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gf100_fifo_sched_reason[] = {
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{ 0x0a, "CTXSW_TIMEOUT" },
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@ -701,8 +676,10 @@ gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit)
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char msg[128];
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if (stat & 0x00800000) {
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if (!gf100_fifo_swmthd(fifo, chid, mthd, data))
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show &= ~0x00800000;
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if (device->sw) {
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if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data))
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show &= ~0x00800000;
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}
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}
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if (show) {
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@ -31,6 +31,7 @@
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#include <subdev/fb.h>
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#include <subdev/mmu.h>
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#include <subdev/timer.h>
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#include <engine/sw.h>
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#include <nvif/class.h>
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#include <nvif/ioctl.h>
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@ -520,32 +521,6 @@ gk104_fifo_recover(struct gk104_fifo *fifo, struct nvkm_engine *engine,
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schedule_work(&fifo->fault);
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}
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static int
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gk104_fifo_swmthd(struct gk104_fifo *fifo, u32 chid, u32 mthd, u32 data)
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{
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struct gk104_fifo_chan *chan = NULL;
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struct nvkm_handle *bind;
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unsigned long flags;
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int ret = -EINVAL;
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spin_lock_irqsave(&fifo->base.lock, flags);
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if (likely(chid >= fifo->base.min && chid <= fifo->base.max))
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chan = (void *)fifo->base.channel[chid];
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if (unlikely(!chan))
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goto out;
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bind = nvkm_namedb_get_class(nv_namedb(chan), NVIF_IOCTL_NEW_V0_SW_GF100);
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if (likely(bind)) {
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if (!mthd || !nv_call(bind->object, mthd, data))
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ret = 0;
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nvkm_namedb_put(bind);
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}
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out:
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spin_unlock_irqrestore(&fifo->base.lock, flags);
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return ret;
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}
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static const struct nvkm_enum
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gk104_fifo_bind_reason[] = {
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{ 0x01, "BIND_NOT_UNBOUND" },
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@ -864,8 +839,10 @@ gk104_fifo_intr_pbdma_0(struct gk104_fifo *fifo, int unit)
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char msg[128];
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if (stat & 0x00800000) {
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if (!gk104_fifo_swmthd(fifo, chid, mthd, data))
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show &= ~0x00800000;
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if (device->sw) {
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if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data))
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show &= ~0x00800000;
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}
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nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008);
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}
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@ -29,6 +29,7 @@
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#include <core/ramht.h>
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#include <subdev/instmem.h>
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#include <subdev/timer.h>
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#include <engine/sw.h>
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#include <nvif/class.h>
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#include <nvif/unpack.h>
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@ -369,55 +370,29 @@ nv_dma_state_err(u32 state)
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}
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static bool
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nv04_fifo_swmthd(struct nv04_fifo *fifo, u32 chid, u32 addr, u32 data)
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nv04_fifo_swmthd(struct nvkm_device *device, u32 chid, u32 addr, u32 data)
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{
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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struct nv04_fifo_chan *chan = NULL;
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struct nvkm_handle *bind;
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const int subc = (addr >> 13) & 0x7;
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const int mthd = addr & 0x1ffc;
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struct nvkm_sw *sw = device->sw;
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const int subc = (addr & 0x0000e000) >> 13;
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const int mthd = (addr & 0x00001ffc);
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const u32 mask = 0x0000000f << (subc * 4);
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u32 engine = nvkm_rd32(device, 0x003280);
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bool handled = false;
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unsigned long flags;
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u32 engine;
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spin_lock_irqsave(&fifo->base.lock, flags);
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if (likely(chid >= fifo->base.min && chid <= fifo->base.max))
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chan = (void *)fifo->base.channel[chid];
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if (unlikely(!chan))
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goto out;
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switch (mthd) {
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case 0x0000:
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bind = nvkm_namedb_get(nv_namedb(chan), data);
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if (unlikely(!bind))
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break;
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if (nv_engidx(bind->object->engine) == NVDEV_ENGINE_SW) {
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engine = 0x0000000f << (subc * 4);
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chan->subc[subc] = data;
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handled = true;
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nvkm_mask(device, NV04_PFIFO_CACHE1_ENGINE, engine, 0);
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}
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nvkm_namedb_put(bind);
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case 0x0000 ... 0x0000: /* subchannel's engine -> software */
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nvkm_wr32(device, 0x003280, (engine &= ~mask));
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case 0x0180 ... 0x01fc: /* handle -> instance */
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data = nvkm_rd32(device, 0x003258) & 0x0000ffff;
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case 0x0100 ... 0x017c:
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case 0x0200 ... 0x1ffc: /* pass method down to sw */
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if (!(engine & mask) && sw)
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handled = nvkm_sw_mthd(sw, chid, subc, mthd, data);
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break;
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default:
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engine = nvkm_rd32(device, NV04_PFIFO_CACHE1_ENGINE);
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if (unlikely(((engine >> (subc * 4)) & 0xf) != 0))
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break;
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bind = nvkm_namedb_get(nv_namedb(chan), chan->subc[subc]);
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if (likely(bind)) {
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if (!nv_call(bind->object, mthd, data))
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handled = true;
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nvkm_namedb_put(bind);
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}
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break;
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}
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out:
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spin_unlock_irqrestore(&fifo->base.lock, flags);
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return handled;
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}
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@ -426,6 +401,7 @@ nv04_fifo_cache_error(struct nv04_fifo *fifo, u32 chid, u32 get)
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{
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 pull0 = nvkm_rd32(device, 0x003250);
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u32 mthd, data;
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int ptr;
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@ -444,7 +420,8 @@ nv04_fifo_cache_error(struct nv04_fifo *fifo, u32 chid, u32 get)
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data = nvkm_rd32(device, NV40_PFIFO_CACHE1_DATA(ptr));
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}
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if (!nv04_fifo_swmthd(fifo, chid, mthd, data)) {
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if (!(pull0 & 0x00000100) ||
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!nv04_fifo_swmthd(device, chid, mthd, data)) {
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const char *client_name =
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nvkm_client_name_for_fifo_chid(&fifo->base, chid);
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nvkm_error(subdev, "CACHE_ERROR - "
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@ -1,3 +1,4 @@
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nvkm-y += nvkm/engine/sw/base.o
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nvkm-y += nvkm/engine/sw/nv04.o
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nvkm-y += nvkm/engine/sw/nv10.o
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nvkm-y += nvkm/engine/sw/nv50.o
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64
drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c
Normal file
64
drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c
Normal file
@ -0,0 +1,64 @@
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/*
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* Copyright 2015 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs <bskeggs@redhat.com>
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*/
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#include "priv.h"
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#include "chan.h"
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#include <engine/fifo.h>
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bool
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nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data)
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{
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struct nvkm_sw_chan *chan;
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bool handled = false;
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unsigned long flags;
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spin_lock_irqsave(&sw->engine.lock, flags);
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list_for_each_entry(chan, &sw->chan, head) {
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if (chan->fifo->chid == chid) {
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handled = nvkm_sw_chan_mthd(chan, subc, mthd, data);
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list_del(&chan->head);
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list_add(&chan->head, &sw->chan);
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break;
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}
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}
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spin_unlock_irqrestore(&sw->engine.lock, flags);
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return handled;
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}
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int
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nvkm_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, int length, void **pobject)
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{
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struct nvkm_sw *sw;
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int ret;
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ret = nvkm_engine_create_(parent, engine, oclass, true, "sw",
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"sw", length, pobject);
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sw = *pobject;
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if (ret)
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return ret;
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INIT_LIST_HEAD(&sw->chan);
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return 0;
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}
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@ -24,10 +24,28 @@
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#include "chan.h"
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#include <core/notify.h>
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#include <engine/fifo.h>
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#include <nvif/event.h>
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#include <nvif/unpack.h>
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bool
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nvkm_sw_chan_mthd(struct nvkm_sw_chan *chan, int subc, u32 mthd, u32 data)
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{
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switch (mthd) {
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case 0x0000:
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return true;
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case 0x0500:
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nvkm_event_send(&chan->event, 1, 0, NULL, 0);
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return true;
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default:
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if (chan->func->mthd)
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return chan->func->mthd(chan, subc, mthd, data);
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break;
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}
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return false;
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}
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static int
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nvkm_sw_chan_event_ctor(struct nvkm_object *object, void *data, u32 size,
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struct nvkm_notify *notify)
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@ -55,14 +73,17 @@ void
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nvkm_sw_chan_dtor(struct nvkm_object *base)
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{
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struct nvkm_sw_chan *chan = (void *)base;
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list_del(&chan->head);
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nvkm_event_fini(&chan->event);
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nvkm_engctx_destroy(&chan->base);
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}
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int
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nvkm_sw_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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nvkm_sw_chan_ctor(const struct nvkm_sw_chan_func *func,
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struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, int length, void **pobject)
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{
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struct nvkm_sw *sw = (void *)engine;
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struct nvkm_sw_chan *chan;
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int ret;
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@ -72,5 +93,9 @@ nvkm_sw_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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if (ret)
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return ret;
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chan->func = func;
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chan->fifo = nvkm_fifo_chan(parent);
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list_add(&chan->head, &sw->chan);
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return nvkm_event_init(&nvkm_sw_chan_event, 1, 1, &chan->event);
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}
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@ -6,12 +6,22 @@
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struct nvkm_sw_chan {
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struct nvkm_engctx base;
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const struct nvkm_sw_chan_func *func;
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struct nvkm_fifo_chan *fifo;
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struct list_head head;
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struct nvkm_event event;
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};
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#define nvkm_sw_context_create(p,e,c,d) \
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nvkm_sw_chan_ctor((p), (e), (c), sizeof(**d), (void **)d)
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int nvkm_sw_chan_ctor(struct nvkm_object *, struct nvkm_object *,
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struct nvkm_sw_chan_func {
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bool (*mthd)(struct nvkm_sw_chan *, int subc, u32 mthd, u32 data);
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};
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bool nvkm_sw_chan_mthd(struct nvkm_sw_chan *, int subc, u32 mthd, u32 data);
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|
||||
#define nvkm_sw_context_create(f,p,e,c,d) \
|
||||
nvkm_sw_chan_ctor((f), (p), (e), (c), sizeof(**d), (void **)d)
|
||||
int nvkm_sw_chan_ctor(const struct nvkm_sw_chan_func *,
|
||||
struct nvkm_object *, struct nvkm_object *,
|
||||
struct nvkm_oclass *, int, void **);
|
||||
void nvkm_sw_chan_dtor(struct nvkm_object *);
|
||||
#define nvkm_sw_context_init(d) \
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
#include "nv50.h"
|
||||
|
||||
#include <subdev/bar.h>
|
||||
#include <engine/disp.h>
|
||||
|
||||
#include <nvif/ioctl.h>
|
||||
|
||||
@ -31,65 +32,9 @@
|
||||
* software object classes
|
||||
******************************************************************************/
|
||||
|
||||
static int
|
||||
gf100_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd,
|
||||
void *args, u32 size)
|
||||
{
|
||||
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
|
||||
u64 data = *(u32 *)args;
|
||||
if (mthd == 0x0400) {
|
||||
chan->vblank.offset &= 0x00ffffffffULL;
|
||||
chan->vblank.offset |= data << 32;
|
||||
} else {
|
||||
chan->vblank.offset &= 0xff00000000ULL;
|
||||
chan->vblank.offset |= data;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
gf100_sw_mthd_mp_control(struct nvkm_object *object, u32 mthd,
|
||||
void *args, u32 size)
|
||||
{
|
||||
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
|
||||
struct nvkm_sw *sw = (void *)nv_object(chan)->engine;
|
||||
struct nvkm_device *device = sw->engine.subdev.device;
|
||||
u32 data = *(u32 *)args;
|
||||
|
||||
switch (mthd) {
|
||||
case 0x600:
|
||||
nvkm_wr32(device, 0x419e00, data); /* MP.PM_UNK000 */
|
||||
break;
|
||||
case 0x644:
|
||||
if (data & ~0x1ffffe)
|
||||
return -EINVAL;
|
||||
nvkm_wr32(device, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */
|
||||
break;
|
||||
case 0x6ac:
|
||||
nvkm_wr32(device, 0x419eac, data); /* MP.PM_UNK0AC */
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct nvkm_omthds
|
||||
gf100_sw_omthds[] = {
|
||||
{ 0x0400, 0x0400, gf100_sw_mthd_vblsem_offset },
|
||||
{ 0x0404, 0x0404, gf100_sw_mthd_vblsem_offset },
|
||||
{ 0x0408, 0x0408, nv50_sw_mthd_vblsem_value },
|
||||
{ 0x040c, 0x040c, nv50_sw_mthd_vblsem_release },
|
||||
{ 0x0500, 0x0500, nv50_sw_mthd_flip },
|
||||
{ 0x0600, 0x0600, gf100_sw_mthd_mp_control },
|
||||
{ 0x0644, 0x0644, gf100_sw_mthd_mp_control },
|
||||
{ 0x06ac, 0x06ac, gf100_sw_mthd_mp_control },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct nvkm_oclass
|
||||
gf100_sw_sclass[] = {
|
||||
{ NVIF_IOCTL_NEW_V0_SW_GF100, &nvkm_nvsw_ofuncs, gf100_sw_omthds },
|
||||
{ NVIF_IOCTL_NEW_V0_SW_GF100, &nvkm_nvsw_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
@ -115,6 +60,53 @@ gf100_sw_vblsem_release(struct nvkm_notify *notify)
|
||||
return NVKM_NOTIFY_DROP;
|
||||
}
|
||||
|
||||
static bool
|
||||
gf100_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data)
|
||||
{
|
||||
struct nv50_sw_chan *chan = nv50_sw_chan(base);
|
||||
struct nvkm_engine *engine = chan->base.base.gpuobj.object.engine;
|
||||
struct nvkm_device *device = engine->subdev.device;
|
||||
switch (mthd) {
|
||||
case 0x0400:
|
||||
chan->vblank.offset &= 0x00ffffffffULL;
|
||||
chan->vblank.offset |= (u64)data << 32;
|
||||
return true;
|
||||
case 0x0404:
|
||||
chan->vblank.offset &= 0xff00000000ULL;
|
||||
chan->vblank.offset |= data;
|
||||
return true;
|
||||
case 0x0408:
|
||||
chan->vblank.value = data;
|
||||
return true;
|
||||
case 0x040c:
|
||||
if (data < device->disp->vblank.index_nr) {
|
||||
nvkm_notify_get(&chan->vblank.notify[data]);
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
case 0x600: /* MP.PM_UNK000 */
|
||||
nvkm_wr32(device, 0x419e00, data);
|
||||
return true;
|
||||
case 0x644: /* MP.TRAP_WARP_ERROR_EN */
|
||||
if (!(data & ~0x001ffffe)) {
|
||||
nvkm_wr32(device, 0x419e44, data);
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
case 0x6ac: /* MP.PM_UNK0AC */
|
||||
nvkm_wr32(device, 0x419eac, data);
|
||||
return true;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
static const struct nvkm_sw_chan_func
|
||||
gf100_sw_chan_func = {
|
||||
.mthd = gf100_sw_chan_mthd,
|
||||
};
|
||||
|
||||
static struct nv50_sw_cclass
|
||||
gf100_sw_cclass = {
|
||||
.base.handle = NV_ENGCTX(SW, 0xc0),
|
||||
@ -125,6 +117,7 @@ gf100_sw_cclass = {
|
||||
.fini = _nvkm_sw_context_fini,
|
||||
},
|
||||
.vblank = gf100_sw_vblsem_release,
|
||||
.chan = &gf100_sw_chan_func,
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
|
||||
@ -21,6 +21,7 @@
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#define nv04_sw_chan(p) container_of((p), struct nv04_sw_chan, base)
|
||||
#include "priv.h"
|
||||
#include "chan.h"
|
||||
#include "nvsw.h"
|
||||
@ -38,29 +39,6 @@ struct nv04_sw_chan {
|
||||
* software object classes
|
||||
******************************************************************************/
|
||||
|
||||
static int
|
||||
nv04_sw_set_ref(struct nvkm_object *object, u32 mthd, void *data, u32 size)
|
||||
{
|
||||
struct nv04_sw_chan *chan = (void *)nv_engctx(object->parent);
|
||||
atomic_set(&chan->ref, *(u32*)data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv04_sw_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size)
|
||||
{
|
||||
struct nvkm_sw_chan *chan = (void *)nv_engctx(object->parent);
|
||||
nvkm_event_send(&chan->event, 1, 0, NULL, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct nvkm_omthds
|
||||
nv04_sw_omthds[] = {
|
||||
{ 0x0150, 0x0150, nv04_sw_set_ref },
|
||||
{ 0x0500, 0x0500, nv04_sw_flip },
|
||||
{}
|
||||
};
|
||||
|
||||
static int
|
||||
nv04_sw_mthd_get_ref(struct nvkm_object *object, void *data, u32 size)
|
||||
{
|
||||
@ -100,7 +78,7 @@ nv04_sw_ofuncs = {
|
||||
|
||||
static struct nvkm_oclass
|
||||
nv04_sw_sclass[] = {
|
||||
{ NVIF_IOCTL_NEW_V0_SW_NV04, &nv04_sw_ofuncs, nv04_sw_omthds },
|
||||
{ NVIF_IOCTL_NEW_V0_SW_NV04, &nv04_sw_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
@ -108,6 +86,27 @@ nv04_sw_sclass[] = {
|
||||
* software context
|
||||
******************************************************************************/
|
||||
|
||||
static bool
|
||||
nv04_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data)
|
||||
{
|
||||
struct nv04_sw_chan *chan = nv04_sw_chan(base);
|
||||
|
||||
switch (mthd) {
|
||||
case 0x0150:
|
||||
atomic_set(&chan->ref, data);
|
||||
return true;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static const struct nvkm_sw_chan_func
|
||||
nv04_sw_chan_func = {
|
||||
.mthd = nv04_sw_chan_mthd,
|
||||
};
|
||||
|
||||
static int
|
||||
nv04_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
@ -116,7 +115,8 @@ nv04_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nv04_sw_chan *chan;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_sw_context_create(parent, engine, oclass, &chan);
|
||||
ret = nvkm_sw_context_create(&nv04_sw_chan_func,
|
||||
parent, engine, oclass, &chan);
|
||||
*pobject = nv_object(chan);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@ -31,23 +31,9 @@
|
||||
* software object classes
|
||||
******************************************************************************/
|
||||
|
||||
static int
|
||||
nv10_sw_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size)
|
||||
{
|
||||
struct nvkm_sw_chan *chan = (void *)nv_engctx(object->parent);
|
||||
nvkm_event_send(&chan->event, 1, 0, NULL, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct nvkm_omthds
|
||||
nv10_sw_omthds[] = {
|
||||
{ 0x0500, 0x0500, nv10_sw_flip },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct nvkm_oclass
|
||||
nv10_sw_sclass[] = {
|
||||
{ NVIF_IOCTL_NEW_V0_SW_NV10, &nvkm_nvsw_ofuncs, nv10_sw_omthds },
|
||||
{ NVIF_IOCTL_NEW_V0_SW_NV10, &nvkm_nvsw_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
@ -55,6 +41,10 @@ nv10_sw_sclass[] = {
|
||||
* software context
|
||||
******************************************************************************/
|
||||
|
||||
static const struct nvkm_sw_chan_func
|
||||
nv10_sw_chan_func = {
|
||||
};
|
||||
|
||||
static int
|
||||
nv10_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
@ -63,7 +53,8 @@ nv10_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_sw_chan *chan;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_sw_context_create(parent, engine, oclass, &chan);
|
||||
ret = nvkm_sw_context_create(&nv10_sw_chan_func,
|
||||
parent, engine, oclass, &chan);
|
||||
*pobject = nv_object(chan);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@ -35,80 +35,9 @@
|
||||
* software object classes
|
||||
******************************************************************************/
|
||||
|
||||
static int
|
||||
nv50_sw_mthd_dma_vblsem(struct nvkm_object *object, u32 mthd,
|
||||
void *args, u32 size)
|
||||
{
|
||||
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
|
||||
struct nvkm_fifo_chan *fifo = (void *)nv_object(chan)->parent;
|
||||
struct nvkm_handle *handle;
|
||||
int ret = -EINVAL;
|
||||
|
||||
handle = nvkm_namedb_get(nv_namedb(fifo), *(u32 *)args);
|
||||
if (!handle)
|
||||
return -ENOENT;
|
||||
|
||||
if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) {
|
||||
struct nvkm_gpuobj *gpuobj = nv_gpuobj(handle->object);
|
||||
chan->vblank.ctxdma = gpuobj->node->offset >> 4;
|
||||
ret = 0;
|
||||
}
|
||||
nvkm_namedb_put(handle);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd,
|
||||
void *args, u32 size)
|
||||
{
|
||||
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
|
||||
chan->vblank.offset = *(u32 *)args;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nv50_sw_mthd_vblsem_value(struct nvkm_object *object, u32 mthd,
|
||||
void *args, u32 size)
|
||||
{
|
||||
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
|
||||
chan->vblank.value = *(u32 *)args;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nv50_sw_mthd_vblsem_release(struct nvkm_object *object, u32 mthd,
|
||||
void *args, u32 size)
|
||||
{
|
||||
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
|
||||
u32 head = *(u32 *)args;
|
||||
if (head >= nvkm_disp(chan)->vblank.index_nr)
|
||||
return -EINVAL;
|
||||
|
||||
nvkm_notify_get(&chan->vblank.notify[head]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nv50_sw_mthd_flip(struct nvkm_object *object, u32 mthd, void *args, u32 size)
|
||||
{
|
||||
struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
|
||||
nvkm_event_send(&chan->base.event, 1, 0, NULL, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct nvkm_omthds
|
||||
nv50_sw_omthds[] = {
|
||||
{ 0x018c, 0x018c, nv50_sw_mthd_dma_vblsem },
|
||||
{ 0x0400, 0x0400, nv50_sw_mthd_vblsem_offset },
|
||||
{ 0x0404, 0x0404, nv50_sw_mthd_vblsem_value },
|
||||
{ 0x0408, 0x0408, nv50_sw_mthd_vblsem_release },
|
||||
{ 0x0500, 0x0500, nv50_sw_mthd_flip },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct nvkm_oclass
|
||||
nv50_sw_sclass[] = {
|
||||
{ NVIF_IOCTL_NEW_V0_SW_NV50, &nvkm_nvsw_ofuncs, nv50_sw_omthds },
|
||||
{ NVIF_IOCTL_NEW_V0_SW_NV50, &nvkm_nvsw_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
@ -140,6 +69,31 @@ nv50_sw_vblsem_release(struct nvkm_notify *notify)
|
||||
return NVKM_NOTIFY_DROP;
|
||||
}
|
||||
|
||||
static bool
|
||||
nv50_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data)
|
||||
{
|
||||
struct nv50_sw_chan *chan = nv50_sw_chan(base);
|
||||
switch (mthd) {
|
||||
case 0x018c: chan->vblank.ctxdma = data; return true;
|
||||
case 0x0400: chan->vblank.offset = data; return true;
|
||||
case 0x0404: chan->vblank.value = data; return true;
|
||||
case 0x0408:
|
||||
if (data < nvkm_disp(chan)->vblank.index_nr) {
|
||||
nvkm_notify_get(&chan->vblank.notify[data]);
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
static const struct nvkm_sw_chan_func
|
||||
nv50_sw_chan_func = {
|
||||
.mthd = nv50_sw_chan_mthd,
|
||||
};
|
||||
|
||||
void
|
||||
nv50_sw_context_dtor(struct nvkm_object *object)
|
||||
{
|
||||
@ -162,7 +116,7 @@ nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nv50_sw_chan *chan;
|
||||
int ret, i;
|
||||
|
||||
ret = nvkm_sw_context_create(parent, engine, oclass, &chan);
|
||||
ret = nvkm_sw_context_create(pclass->chan, parent, engine, oclass, &chan);
|
||||
*pobject = nv_object(chan);
|
||||
if (ret)
|
||||
return ret;
|
||||
@ -194,6 +148,7 @@ nv50_sw_cclass = {
|
||||
.fini = _nvkm_sw_context_fini,
|
||||
},
|
||||
.vblank = nv50_sw_vblsem_release,
|
||||
.chan = &nv50_sw_chan_func,
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
#ifndef __NVKM_SW_NV50_H__
|
||||
#define __NVKM_SW_NV50_H__
|
||||
#define nv50_sw_chan(p) container_of((p), struct nv50_sw_chan, base)
|
||||
#include "priv.h"
|
||||
#include "chan.h"
|
||||
#include "nvsw.h"
|
||||
@ -18,6 +19,7 @@ int nv50_sw_ctor(struct nvkm_object *, struct nvkm_object *,
|
||||
struct nv50_sw_cclass {
|
||||
struct nvkm_oclass base;
|
||||
int (*vblank)(struct nvkm_notify *);
|
||||
const struct nvkm_sw_chan_func *chan;
|
||||
};
|
||||
|
||||
struct nv50_sw_chan {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user