korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-11-24 04:34:08 +08:00
Code Issues Packages Projects Releases Wiki Activity

clk: renesas: r8a77995: Add missing CPEX clock

Browse Source 
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) added
the CPEX clock on R-Car D3.  This clock can be selected as a clock
source for CMT1 (Compare Match Timer Type 1).

Add the missing clock to the DT bindings header, and implement support
for it in the clock driver.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Geert Uytterhoeven 2018-11-21 10:32:23 +01:00
parent 846dbb405b
commit 6155bfa32c
2 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/clk/renesas/r8a77995-cpg-mssr.c
View File

@ -22,7 +22,7 @@
enum clk_ids { enum clk_ids {
/* Core Clock Outputs exported to DT */ /* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A77995_CLK_CP, LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,
/* External Input Clocks */ /* External Input Clocks */
CLK_EXTAL, CLK_EXTAL,
@ -92,6 +92,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1), DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1),
DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),

1
include/dt-bindings/clock/r8a77995-cpg-mssr.h
View File

@ -49,5 +49,6 @@
#define R8A77995_CLK_LV0 38 #define R8A77995_CLK_LV0 38
#define R8A77995_CLK_LV1 39 #define R8A77995_CLK_LV1 39
#define R8A77995_CLK_CP 40 #define R8A77995_CLK_CP 40
#define R8A77995_CLK_CPEX 41
#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */ #endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */