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intel_idle: Voluntary leave_mm before entering deeper
Avoid TLB flush IPIs for the cores in deeper c-states by voluntary leave_mm() before entering into that state. CPUs tend to flush TLB in those c-states anyways. acpi_idle does this with C3-type states, but it was not caried over when intel_idle was introduced. intel_idle can apply it to C-states in addition to those that ACPI might export as C3... Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
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@ -108,7 +108,7 @@ static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
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.name = "NHM-C3",
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.desc = "MWAIT 0x10",
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.driver_data = (void *) 0x10,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 20,
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.power_usage = 500,
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.target_residency = 80,
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@ -117,7 +117,7 @@ static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
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.name = "NHM-C6",
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.desc = "MWAIT 0x20",
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.driver_data = (void *) 0x20,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 200,
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.power_usage = 350,
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.target_residency = 800,
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@ -149,7 +149,7 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
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.name = "ATM-C4",
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.desc = "MWAIT 0x30",
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.driver_data = (void *) 0x30,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 100,
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.power_usage = 250,
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.target_residency = 400,
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@ -159,7 +159,7 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
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.name = "ATM-C6",
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.desc = "MWAIT 0x40",
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.driver_data = (void *) 0x40,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 200,
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.power_usage = 150,
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.target_residency = 800,
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@ -185,6 +185,16 @@ static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
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local_irq_disable();
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/*
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* If the state flag indicates that the TLB will be flushed or if this
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* is the deepest c-state supported, do a voluntary leave mm to avoid
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* costly and mostly unnecessary wakeups for flushing the user TLB's
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* associated with the active mm.
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*/
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if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED ||
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(&dev->states[dev->state_count - 1] == state))
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leave_mm(cpu);
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if (!(lapic_timer_reliable_states & (1 << (cstate))))
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
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@ -53,6 +53,7 @@ struct cpuidle_state {
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#define CPUIDLE_FLAG_BALANCED (0x40) /* medium latency, moderate savings */
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#define CPUIDLE_FLAG_DEEP (0x80) /* high latency, large savings */
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#define CPUIDLE_FLAG_IGNORE (0x100) /* ignore during this idle period */
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#define CPUIDLE_FLAG_TLB_FLUSHED (0x200) /* tlb will be flushed */
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#define CPUIDLE_DRIVER_FLAGS_MASK (0xFFFF0000)
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