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net: mvpp2: always compare hw-version vs MVPP21
Currently we have PP2v1 and PP2v2 hw-versions, with some different handlers depending upon condition hw_version = MVPP21/MVPP22. In a future there will be also PP2v3. Let's use now the generic "if equal/notEqual MVPP21" for all cases instead of "if MVPP22". This patch does not change any functionality. It is not intended to introduce PP2v3. It just modifies MVPP21/MVPP22 check-condition bringing it to generic and unified form correct for new-code introducing and PP2v3 net-next generation. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -319,7 +319,7 @@ static int mvpp2_get_nrxqs(struct mvpp2 *priv)
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{
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unsigned int nrxqs;
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if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
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if (priv->hw_version != MVPP21 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
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return 1;
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/* According to the PPv2.2 datasheet and our experiments on
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@ -446,7 +446,7 @@ static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
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MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
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*phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
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if (priv->hw_version == MVPP22) {
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if (priv->hw_version != MVPP21) {
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u32 val;
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u32 dma_addr_highbits, phys_addr_highbits;
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@ -742,7 +742,7 @@ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
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if (test_bit(thread, &port->priv->lock_map))
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spin_lock_irqsave(&port->bm_lock[thread], flags);
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if (port->priv->hw_version == MVPP22) {
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if (port->priv->hw_version != MVPP21) {
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u32 val = 0;
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if (sizeof(dma_addr_t) == 8)
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@ -1172,7 +1172,7 @@ mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
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u32 val;
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int i;
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if (port->priv->hw_version != MVPP22)
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if (port->priv->hw_version == MVPP21)
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return;
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if (mask)
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@ -1199,7 +1199,7 @@ static bool mvpp2_port_supports_xlg(struct mvpp2_port *port)
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static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port)
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{
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return !(port->priv->hw_version == MVPP22 && port->gop_id == 0);
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return !(port->priv->hw_version != MVPP21 && port->gop_id == 0);
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}
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/* Port configuration routines */
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@ -1817,7 +1817,7 @@ static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
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MVPP2_GMAC_PORT_RESET_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
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if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
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if (port->priv->hw_version != MVPP21 && port->gop_id == 0) {
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val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
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~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
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writel(val, port->base + MVPP22_XLG_CTRL0_REG);
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@ -1830,7 +1830,7 @@ static void mvpp22_pcs_reset_assert(struct mvpp2_port *port)
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void __iomem *mpcs, *xpcs;
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u32 val;
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if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
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if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
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return;
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mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
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@ -1851,7 +1851,7 @@ static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port)
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void __iomem *mpcs, *xpcs;
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u32 val;
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if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
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if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
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return;
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mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
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@ -4196,7 +4196,7 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
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/* Enable interrupts on all threads */
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mvpp2_interrupts_enable(port);
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if (port->priv->hw_version == MVPP22)
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if (port->priv->hw_version != MVPP21)
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mvpp22_mode_reconfigure(port);
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if (port->phylink) {
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@ -4412,7 +4412,7 @@ static int mvpp2_open(struct net_device *dev)
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valid = true;
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}
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if (priv->hw_version == MVPP22 && port->port_irq) {
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if (priv->hw_version != MVPP21 && port->port_irq) {
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err = request_irq(port->port_irq, mvpp2_port_isr, 0,
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dev->name, port);
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if (err) {
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@ -6060,7 +6060,7 @@ static int mvpp2__mac_prepare(struct phylink_config *config, unsigned int mode,
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MVPP2_GMAC_PORT_RESET_MASK,
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MVPP2_GMAC_PORT_RESET_MASK);
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if (port->priv->hw_version == MVPP22) {
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if (port->priv->hw_version != MVPP21) {
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mvpp22_gop_mask_irq(port);
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phy_power_off(port->comphy);
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@ -6114,7 +6114,7 @@ static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode,
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{
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struct mvpp2_port *port = mvpp2_phylink_to_port(config);
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if (port->priv->hw_version == MVPP22 &&
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if (port->priv->hw_version != MVPP21 &&
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port->phy_interface != interface) {
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port->phy_interface = interface;
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@ -6794,7 +6794,7 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
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if (dram_target_info)
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mvpp2_conf_mbus_windows(dram_target_info, priv);
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if (priv->hw_version == MVPP22)
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if (priv->hw_version != MVPP21)
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mvpp2_axi_init(priv);
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/* Disable HW PHY polling */
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@ -6938,7 +6938,7 @@ static int mvpp2_probe(struct platform_device *pdev)
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dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
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}
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if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
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if (priv->hw_version != MVPP21 && dev_of_node(&pdev->dev)) {
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priv->sysctrl_base =
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syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"marvell,system-controller");
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@ -6951,7 +6951,7 @@ static int mvpp2_probe(struct platform_device *pdev)
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priv->sysctrl_base = NULL;
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}
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if (priv->hw_version == MVPP22 &&
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if (priv->hw_version != MVPP21 &&
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mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS)
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priv->percpu_pools = 1;
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@ -6996,7 +6996,7 @@ static int mvpp2_probe(struct platform_device *pdev)
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if (err < 0)
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goto err_pp_clk;
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if (priv->hw_version == MVPP22) {
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if (priv->hw_version != MVPP21) {
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priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
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if (IS_ERR(priv->mg_clk)) {
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err = PTR_ERR(priv->mg_clk);
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@ -7037,7 +7037,7 @@ static int mvpp2_probe(struct platform_device *pdev)
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return -EINVAL;
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}
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if (priv->hw_version == MVPP22) {
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if (priv->hw_version != MVPP21) {
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err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
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if (err)
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goto err_axi_clk;
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@ -7112,10 +7112,10 @@ err_axi_clk:
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clk_disable_unprepare(priv->axi_clk);
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err_mg_core_clk:
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if (priv->hw_version == MVPP22)
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if (priv->hw_version != MVPP21)
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clk_disable_unprepare(priv->mg_core_clk);
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err_mg_clk:
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if (priv->hw_version == MVPP22)
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if (priv->hw_version != MVPP21)
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clk_disable_unprepare(priv->mg_clk);
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err_gop_clk:
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clk_disable_unprepare(priv->gop_clk);
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