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dmaengine: xdmac: Add interleaved transfer support
The XDMAC supports interleaved tranfers through its flexible descriptor configuration. Add support for that kind of transfers to the dmaengine driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Maxime Ripard
Vinod Koul
parent
0d0ee751f7
commit
6007ccb577
@ -485,6 +485,19 @@ static void at_xdmac_queue_desc(struct dma_chan *chan,
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__func__, prev, &prev->lld.mbr_nda);
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}
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static inline void at_xdmac_increment_block_count(struct dma_chan *chan,
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struct at_xdmac_desc *desc)
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{
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if (!desc)
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return;
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desc->lld.mbr_bc++;
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dev_dbg(chan2dev(chan),
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"%s: incrementing the block count of the desc 0x%p\n",
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__func__, desc);
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}
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static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec,
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struct of_dma *of_dma)
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{
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@ -782,6 +795,224 @@ static inline u32 at_xdmac_align_width(struct dma_chan *chan, dma_addr_t addr)
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return width;
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}
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static struct at_xdmac_desc *
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at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
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struct at_xdmac_chan *atchan,
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struct at_xdmac_desc *prev,
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dma_addr_t src, dma_addr_t dst,
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struct dma_interleaved_template *xt,
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struct data_chunk *chunk)
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{
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struct at_xdmac_desc *desc;
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u32 dwidth;
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unsigned long flags;
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size_t ublen;
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/*
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* WARNING: The channel configuration is set here since there is no
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* dmaengine_slave_config call in this case. Moreover we don't know the
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* direction, it involves we can't dynamically set the source and dest
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* interface so we have to use the same one. Only interface 0 allows EBI
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* access. Hopefully we can access DDR through both ports (at least on
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* SAMA5D4x), so we can use the same interface for source and dest,
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* that solves the fact we don't know the direction.
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*/
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u32 chan_cc = AT_XDMAC_CC_DIF(0)
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| AT_XDMAC_CC_SIF(0)
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| AT_XDMAC_CC_MBSIZE_SIXTEEN
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| AT_XDMAC_CC_TYPE_MEM_TRAN;
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dwidth = at_xdmac_align_width(chan, src | dst | chunk->size);
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if (chunk->size >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
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dev_dbg(chan2dev(chan),
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"%s: chunk too big (%d, max size %lu)...\n",
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__func__, chunk->size,
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AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth);
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return NULL;
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}
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if (prev)
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dev_dbg(chan2dev(chan),
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"Adding items at the end of desc 0x%p\n", prev);
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if (xt->src_inc) {
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if (xt->src_sgl)
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chan_cc |= AT_XDMAC_CC_SAM_UBS_DS_AM;
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else
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chan_cc |= AT_XDMAC_CC_SAM_INCREMENTED_AM;
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}
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if (xt->dst_inc) {
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if (xt->dst_sgl)
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chan_cc |= AT_XDMAC_CC_DAM_UBS_DS_AM;
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else
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chan_cc |= AT_XDMAC_CC_DAM_INCREMENTED_AM;
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}
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spin_lock_irqsave(&atchan->lock, flags);
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desc = at_xdmac_get_desc(atchan);
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spin_unlock_irqrestore(&atchan->lock, flags);
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if (!desc) {
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dev_err(chan2dev(chan), "can't get descriptor\n");
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return NULL;
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}
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chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
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ublen = chunk->size >> dwidth;
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desc->lld.mbr_sa = src;
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desc->lld.mbr_da = dst;
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if (xt->src_inc && xt->src_sgl) {
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if (chunk->src_icg)
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desc->lld.mbr_sus = chunk->src_icg;
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else
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desc->lld.mbr_sus = chunk->icg;
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}
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if (xt->dst_inc && xt->dst_sgl) {
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if (chunk->dst_icg)
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desc->lld.mbr_dus = chunk->dst_icg;
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else
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desc->lld.mbr_dus = chunk->icg;
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}
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desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
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| AT_XDMAC_MBR_UBC_NDEN
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| AT_XDMAC_MBR_UBC_NSEN
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| ublen;
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desc->lld.mbr_cfg = chan_cc;
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dev_dbg(chan2dev(chan),
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"%s: lld: mbr_sa=0x%08x, mbr_da=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
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__func__, desc->lld.mbr_sa, desc->lld.mbr_da,
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desc->lld.mbr_ubc, desc->lld.mbr_cfg);
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/* Chain lld. */
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if (prev)
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at_xdmac_queue_desc(chan, prev, desc);
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return desc;
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}
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static size_t at_xdmac_get_icg(bool inc, bool sgl, size_t icg, size_t dir_icg)
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{
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if (inc) {
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if (dir_icg)
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return dir_icg;
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else if (sgl)
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return icg;
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}
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return 0;
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}
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static size_t at_xdmac_get_dst_icg(struct dma_interleaved_template *xt,
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struct data_chunk *chunk)
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{
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return at_xdmac_get_icg(xt->dst_inc, xt->dst_sgl,
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chunk->icg, chunk->dst_icg);
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}
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static size_t at_xdmac_get_src_icg(struct dma_interleaved_template *xt,
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struct data_chunk *chunk)
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{
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return at_xdmac_get_icg(xt->src_inc, xt->src_sgl,
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chunk->icg, chunk->src_icg);
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}
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static struct dma_async_tx_descriptor *
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at_xdmac_prep_interleaved(struct dma_chan *chan,
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struct dma_interleaved_template *xt,
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unsigned long flags)
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{
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struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
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struct at_xdmac_desc *prev = NULL, *first = NULL;
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struct data_chunk *chunk, *prev_chunk = NULL;
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dma_addr_t dst_addr, src_addr;
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size_t dst_skip, src_skip, len = 0;
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size_t prev_dst_icg = 0, prev_src_icg = 0;
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int i;
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if (!xt || (xt->numf != 1) || (xt->dir != DMA_MEM_TO_MEM))
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return NULL;
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dev_dbg(chan2dev(chan), "%s: src=0x%08x, dest=0x%08x, numf=%d, frame_size=%d, flags=0x%lx\n",
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__func__, xt->src_start, xt->dst_start, xt->numf,
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xt->frame_size, flags);
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src_addr = xt->src_start;
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dst_addr = xt->dst_start;
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for (i = 0; i < xt->frame_size; i++) {
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struct at_xdmac_desc *desc;
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size_t src_icg, dst_icg;
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chunk = xt->sgl + i;
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dst_icg = at_xdmac_get_dst_icg(xt, chunk);
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src_icg = at_xdmac_get_src_icg(xt, chunk);
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src_skip = chunk->size + src_icg;
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dst_skip = chunk->size + dst_icg;
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dev_dbg(chan2dev(chan),
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"%s: chunk size=%d, src icg=%d, dst icg=%d\n",
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__func__, chunk->size, src_icg, dst_icg);
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/*
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* Handle the case where we just have the same
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* transfer to setup, we can just increase the
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* block number and reuse the same descriptor.
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*/
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if (prev_chunk && prev &&
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(prev_chunk->size == chunk->size) &&
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(prev_src_icg == src_icg) &&
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(prev_dst_icg == dst_icg)) {
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dev_dbg(chan2dev(chan),
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"%s: same configuration that the previous chunk, merging the descriptors...\n",
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__func__);
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at_xdmac_increment_block_count(chan, prev);
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continue;
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}
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desc = at_xdmac_interleaved_queue_desc(chan, atchan,
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prev,
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src_addr, dst_addr,
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xt, chunk);
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if (!desc) {
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list_splice_init(&first->descs_list,
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&atchan->free_descs_list);
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return NULL;
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}
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if (!first)
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first = desc;
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dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
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__func__, desc, first);
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list_add_tail(&desc->desc_node, &first->descs_list);
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if (xt->src_sgl)
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src_addr += src_skip;
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if (xt->dst_sgl)
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dst_addr += dst_skip;
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len += chunk->size;
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prev_chunk = chunk;
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prev_dst_icg = dst_icg;
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prev_src_icg = src_icg;
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prev = desc;
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}
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first->tx_dma_desc.cookie = -EBUSY;
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first->tx_dma_desc.flags = flags;
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first->xfer_size = len;
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return &first->tx_dma_desc;
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}
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static struct dma_async_tx_descriptor *
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at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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size_t len, unsigned long flags)
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@ -1404,6 +1635,7 @@ static int at_xdmac_probe(struct platform_device *pdev)
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}
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dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask);
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dma_cap_set(DMA_INTERLEAVE, atxdmac->dma.cap_mask);
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dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
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dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
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/*
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@ -1417,6 +1649,7 @@ static int at_xdmac_probe(struct platform_device *pdev)
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atxdmac->dma.device_tx_status = at_xdmac_tx_status;
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atxdmac->dma.device_issue_pending = at_xdmac_issue_pending;
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atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic;
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atxdmac->dma.device_prep_interleaved_dma = at_xdmac_prep_interleaved;
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atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
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atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
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atxdmac->dma.device_config = at_xdmac_device_config;
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