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arm64: dts: qcom: sdm670: add display subsystem
The Snapdragon 670 has a display subsystem for controlling and outputting to the display. Add support for it in the device tree. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Richard Acayan <mailingradian@gmail.com> Link: https://lore.kernel.org/r/20231017021805.1083350-15-mailingradian@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Richard Acayan
Bjorn Andersson
parent
ba712fd55c
commit
5f8ba4f28d
@ -6,6 +6,7 @@
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* Copyright (c) 2022, Richard Acayan. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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@ -400,6 +401,30 @@
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};
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};
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dsi_opp_table: opp-table-dsi {
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compatible = "operating-points-v2";
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opp-19200000 {
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opp-hz = /bits/ 64 <19200000>;
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required-opps = <&rpmhpd_opp_min_svs>;
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};
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opp-180000000 {
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opp-hz = /bits/ 64 <180000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-275000000 {
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opp-hz = /bits/ 64 <275000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-358000000 {
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opp-hz = /bits/ 64 <358000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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@ -1353,6 +1378,273 @@
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#interrupt-cells = <4>;
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};
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mdss: display-subsystem@ae00000 {
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compatible = "qcom,sdm670-mdss";
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reg = <0 0x0ae00000 0 0x1000>;
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reg-names = "mdss";
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power-domains = <&dispcc MDSS_GDSC>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "iface", "core";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
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<&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
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interconnect-names = "mdp0-mem", "mdp1-mem";
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iommus = <&apps_smmu 0x880 0x8>,
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<&apps_smmu 0xc80 0x8>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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mdss_mdp: display-controller@ae01000 {
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compatible = "qcom,sdm670-dpu";
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reg = <0 0x0ae01000 0 0x8f000>,
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<0 0x0aeb0000 0 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc GCC_DISP_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
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assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd SDM670_CX>;
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf0_out: endpoint {
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remote-endpoint = <&mdss_dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&mdss_dsi1_in>;
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};
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};
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};
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mdp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-19200000 {
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opp-hz = /bits/ 64 <19200000>;
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required-opps = <&rpmhpd_opp_min_svs>;
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};
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opp-171428571 {
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opp-hz = /bits/ 64 <171428571>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-358000000 {
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opp-hz = /bits/ 64 <358000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-430000000 {
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opp-hz = /bits/ 64 <430000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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mdss_dsi0: dsi@ae94000 {
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compatible = "qcom,sdm670-dsi-ctrl",
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"qcom,mdss-dsi-ctrl";
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reg = <0 0x0ae94000 0 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <4>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
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assigned-clock-parents = <&mdss_dsi0_phy 0>,
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<&mdss_dsi0_phy 1>;
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operating-points-v2 = <&dsi_opp_table>;
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power-domains = <&rpmhpd SDM670_CX>;
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phys = <&mdss_dsi0_phy>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf0_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dsi0_out: endpoint {
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};
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};
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};
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};
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mdss_dsi0_phy: phy@ae94400 {
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compatible = "qcom,dsi-phy-10nm";
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reg = <0 0x0ae94400 0 0x200>,
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<0 0x0ae94600 0 0x280>,
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<0 0x0ae94a00 0 0x1e0>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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status = "disabled";
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};
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mdss_dsi1: dsi@ae96000 {
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compatible = "qcom,sdm670-dsi-ctrl",
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"qcom,mdss-dsi-ctrl";
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reg = <0 0x0ae96000 0 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <5>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
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<&dispcc DISP_CC_MDSS_ESC1_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
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assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
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operating-points-v2 = <&dsi_opp_table>;
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power-domains = <&rpmhpd SDM670_CX>;
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phys = <&mdss_dsi1_phy>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dsi1_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dsi1_out: endpoint {
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};
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};
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};
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};
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mdss_dsi1_phy: phy@ae96400 {
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compatible = "qcom,dsi-phy-10nm";
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reg = <0 0x0ae96400 0 0x200>,
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<0 0x0ae96600 0 0x280>,
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<0 0x0ae96a00 0 0x10e>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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status = "disabled";
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};
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};
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dispcc: clock-controller@af00000 {
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compatible = "qcom,sdm845-dispcc";
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reg = <0 0x0af00000 0 0x10000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_DISP_GPLL0_CLK_SRC>,
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<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
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<&mdss_dsi0_phy 0>,
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<&mdss_dsi0_phy 1>,
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<&mdss_dsi1_phy 0>,
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<&mdss_dsi1_phy 1>,
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<0>,
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<0>;
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clock-names = "bi_tcxo",
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"gcc_disp_gpll0_clk_src",
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"gcc_disp_gpll0_div_clk_src",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk",
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"dsi1_phy_pll_out_byteclk",
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"dsi1_phy_pll_out_dsiclk",
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"dp_link_clk_divsel_ten",
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"dp_vco_divided_clk_src_mux";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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apps_smmu: iommu@15000000 {
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compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500";
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reg = <0 0x15000000 0 0x80000>;
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