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drm/amdgpu: expose GPU sensor related information
This includes shader/memory clocks, temperature, GPU load, etc. v2: - add sub-queries for AMDPGU_INFO_GPU_SENSOR_* - do not break the ABI v3: - return -ENOENT when amdgpu_dpm == 0 - expose more sensor queries v4: - s/GPU_POWER/GPU_AVG_POWER/ - improve VDDNB/VDDGFX query description - fix amdgpu_dpm check v5: - agd: fix warning v6: - agd: bump version Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -60,9 +60,10 @@
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* - 3.8.0 - Add support raster config init in the kernel
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* - 3.8.0 - Add support raster config init in the kernel
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* - 3.9.0 - Add support for memory query info about VRAM and GTT.
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* - 3.9.0 - Add support for memory query info about VRAM and GTT.
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* - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
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* - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
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* - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
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*/
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*/
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#define KMS_DRIVER_MAJOR 3
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#define KMS_DRIVER_MAJOR 3
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#define KMS_DRIVER_MINOR 10
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#define KMS_DRIVER_MINOR 11
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#define KMS_DRIVER_PATCHLEVEL 0
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#define KMS_DRIVER_PATCHLEVEL 0
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int amdgpu_vram_limit = 0;
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int amdgpu_vram_limit = 0;
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@ -240,6 +240,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
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uint32_t ui32 = 0;
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uint32_t ui32 = 0;
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uint64_t ui64 = 0;
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uint64_t ui64 = 0;
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int i, found;
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int i, found;
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int ui32_size = sizeof(ui32);
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if (!info->return_size || !info->return_pointer)
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if (!info->return_size || !info->return_pointer)
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return -EINVAL;
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return -EINVAL;
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@ -596,6 +597,80 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
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return -EINVAL;
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return -EINVAL;
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}
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}
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}
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}
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case AMDGPU_INFO_SENSOR: {
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struct pp_gpu_power query = {0};
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int query_size = sizeof(query);
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if (amdgpu_dpm == 0)
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return -ENOENT;
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switch (info->sensor_info.type) {
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case AMDGPU_INFO_SENSOR_GFX_SCLK:
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/* get sclk in Mhz */
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if (amdgpu_dpm_read_sensor(adev,
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AMDGPU_PP_SENSOR_GFX_SCLK,
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(void *)&ui32, &ui32_size)) {
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return -EINVAL;
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}
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ui32 /= 100;
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break;
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case AMDGPU_INFO_SENSOR_GFX_MCLK:
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/* get mclk in Mhz */
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if (amdgpu_dpm_read_sensor(adev,
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AMDGPU_PP_SENSOR_GFX_MCLK,
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(void *)&ui32, &ui32_size)) {
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return -EINVAL;
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}
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ui32 /= 100;
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break;
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case AMDGPU_INFO_SENSOR_GPU_TEMP:
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/* get temperature in millidegrees C */
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if (amdgpu_dpm_read_sensor(adev,
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AMDGPU_PP_SENSOR_GPU_TEMP,
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(void *)&ui32, &ui32_size)) {
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return -EINVAL;
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}
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break;
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case AMDGPU_INFO_SENSOR_GPU_LOAD:
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/* get GPU load */
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if (amdgpu_dpm_read_sensor(adev,
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AMDGPU_PP_SENSOR_GPU_LOAD,
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(void *)&ui32, &ui32_size)) {
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return -EINVAL;
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}
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break;
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case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
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/* get average GPU power */
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if (amdgpu_dpm_read_sensor(adev,
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AMDGPU_PP_SENSOR_GPU_POWER,
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(void *)&query, &query_size)) {
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return -EINVAL;
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}
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ui32 = query.average_gpu_power >> 8;
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break;
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case AMDGPU_INFO_SENSOR_VDDNB:
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/* get VDDNB in millivolts */
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if (amdgpu_dpm_read_sensor(adev,
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AMDGPU_PP_SENSOR_VDDNB,
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(void *)&ui32, &ui32_size)) {
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return -EINVAL;
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}
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break;
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case AMDGPU_INFO_SENSOR_VDDGFX:
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/* get VDDGFX in millivolts */
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if (amdgpu_dpm_read_sensor(adev,
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AMDGPU_PP_SENSOR_VDDGFX,
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(void *)&ui32, &ui32_size)) {
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return -EINVAL;
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}
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break;
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default:
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DRM_DEBUG_KMS("Invalid request %d\n",
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info->sensor_info.type);
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return -EINVAL;
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}
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return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
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}
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default:
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default:
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DRM_DEBUG_KMS("Invalid request %d\n", info->query);
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DRM_DEBUG_KMS("Invalid request %d\n", info->query);
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return -EINVAL;
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return -EINVAL;
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@ -532,6 +532,22 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_VBIOS_IMAGE 0x2
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#define AMDGPU_INFO_VBIOS_IMAGE 0x2
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/* Query UVD handles */
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/* Query UVD handles */
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#define AMDGPU_INFO_NUM_HANDLES 0x1C
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#define AMDGPU_INFO_NUM_HANDLES 0x1C
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/* Query sensor related information */
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#define AMDGPU_INFO_SENSOR 0x1D
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/* Subquery id: Query GPU shader clock */
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#define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
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/* Subquery id: Query GPU memory clock */
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#define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
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/* Subquery id: Query GPU temperature */
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#define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
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/* Subquery id: Query GPU load */
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#define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
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/* Subquery id: Query average GPU power */
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#define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
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/* Subquery id: Query northbridge voltage */
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#define AMDGPU_INFO_SENSOR_VDDNB 0x6
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/* Subquery id: Query graphics voltage */
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#define AMDGPU_INFO_SENSOR_VDDGFX 0x7
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#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
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#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
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#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
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#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
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@ -595,6 +611,10 @@ struct drm_amdgpu_info {
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__u32 type;
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__u32 type;
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__u32 offset;
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__u32 offset;
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} vbios_info;
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} vbios_info;
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struct {
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__u32 type;
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} sensor_info;
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};
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};
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};
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};
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