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arm-soc: soc-specific updates

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This is stuff that does not fit well into another category and in
 particular is not related to a particular board. The largest part
 in here is extending the am33xx support in the omap platform.
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Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull arm soc-specific updates from Arnd Bergmann:
 "This is stuff that does not fit well into another category and in
  particular is not related to a particular board.  The largest part in
  here is extending the am33xx support in the omap platform."

Fix up trivial conflicts in arch/arm/mach-{imx/mach-mx35_3ds.c, tegra/Makefile}

* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (74 commits)
  ARM: LPC32xx: Add PWM support
  ARM: LPC32xx: Add PWM clock
  ARM: LPC32xx: Set system serial based on cpu unique id
  ARM: vexpress: Config option for early printk console
  ARM: vexpress: Add Device Tree for V2P-CA15_CA7 core tile
  ARM: vexpress: Convert V2P-CA15 Device Tree to 64 bit addresses
  ARM: vexpress: Add fixed regulator for SMSC
  ARM: vexpress: Add missing SP804 interrupt in motherboard's DTS files
  ARM: vexpress: Initial common clock support
  ARM: SAMSUNG: Introduce Kconfig variable for Samsung custom clk API
  ARM: EXYNOS: Add missing static storage class specifier in pmu.c file
  ARM: EXYNOS: Make combiner_init function static
  ARM: EXYNOS: Update HSOTG PHY clock setting for EXYNOS4X12
  ARM: versatile: Make plat-versatile clock optional
  ARM: vexpress: Check master site in daughterboard's sysctl operations
  ARM: vexpress: remove automatic errata workaround selection
  ARM: LPC32xx: Adjust to pl08x DMA interface changes
  ARM: EXYNOS: Clear SYS_WDTRESET bit to use watchdog reset
  ARM: imx: fix mx51 ehci setup errors
  ARM: imx: make ehci power/oc polarities configurable
  ...
This commit is contained in:
Linus Torvalds 2012-07-23 16:08:40 -07:00
commit 5e512d0785
91 changed files with 4720 additions and 842 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm/Kconfig
View File

@ -260,6 +260,7 @@ config ARCH_INTEGRATOR
select ICST
select GENERIC_CLOCKEVENTS
select PLAT_VERSATILE
select PLAT_VERSATILE_CLOCK
select PLAT_VERSATILE_FPGA_IRQ
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
@ -277,6 +278,7 @@ config ARCH_REALVIEW
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
select PLAT_VERSATILE
select PLAT_VERSATILE_CLOCK
select PLAT_VERSATILE_CLCD
select ARM_TIMER_SP804
select GPIO_PL061 if GPIOLIB
@ -295,6 +297,7 @@ config ARCH_VERSATILE
select ARCH_WANT_OPTIONAL_GPIOLIB
select NEED_MACH_IO_H if PCI
select PLAT_VERSATILE
select PLAT_VERSATILE_CLOCK
select PLAT_VERSATILE_CLCD
select PLAT_VERSATILE_FPGA_IRQ
select ARM_TIMER_SP804
@ -307,7 +310,7 @@ config ARCH_VEXPRESS
select ARM_AMBA
select ARM_TIMER_SP804
select CLKDEV_LOOKUP
select HAVE_MACH_CLKDEV
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select HAVE_CLK
select HAVE_PATA_PLATFORM
@ -315,6 +318,7 @@ config ARCH_VEXPRESS
select NO_IOPORT
select PLAT_VERSATILE
select PLAT_VERSATILE_CLCD
select REGULATOR_FIXED_VOLTAGE if REGULATOR
help
This enables support for the ARM Ltd Versatile Express boards.
@ -567,6 +571,7 @@ config ARCH_LPC32XX
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select USE_OF
select HAVE_PWM
help
Support for the NXP LPC32XX family of processors
@ -913,7 +918,7 @@ config ARCH_NOMADIK
select ARM_AMBA
select ARM_VIC
select CPU_ARM926T
select CLKDEV_LOOKUP
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select PINCTRL
select MIGHT_HAVE_CACHE_L2X0
@ -1022,8 +1027,6 @@ source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/mach-ks8695/Kconfig"
source "arch/arm/mach-lpc32xx/Kconfig"
source "arch/arm/mach-msm/Kconfig"
source "arch/arm/mach-mv78xx0/Kconfig"

26
arch/arm/Kconfig.debug
View File

@ -310,6 +310,32 @@ choice
The uncompressor code port configuration is now handled
by CONFIG_S3C_LOWLEVEL_UART_PORT.
config DEBUG_VEXPRESS_UART0_DETECT
bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
depends on ARCH_VEXPRESS && CPU_CP15_MMU
help
This option enables a simple heuristic which tries to determine
the motherboard's memory map variant (original or RS1) and then
choose the relevant UART0 base address.
Note that this will only work with standard A-class core tiles,
and may fail with non-standard SMM or custom software models.
config DEBUG_VEXPRESS_UART0_CA9
bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)"
depends on ARCH_VEXPRESS
help
This option selects UART0 at 0x10009000. Except for custom models,
this applies only to the V2P-CA9 tile.
config DEBUG_VEXPRESS_UART0_RS1
bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)"
depends on ARCH_VEXPRESS
help
This option selects UART0 at 0x1c090000. This applies to most
of the tiles using the RS1 memory map, including all new A-class
core tiles, FPGA-based SMMs and software models.
config DEBUG_LL_UART_NONE
bool "No low-level debugging UART"
help

157
arch/arm/boot/dts/ea3250.dts Normal file
View File

@ -0,0 +1,157 @@
/*
* Embedded Artists LPC3250 board
*
* Copyright 2012 Roland Stigge <stigge@antcom.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "lpc32xx.dtsi"
/ {
model = "Embedded Artists LPC3250 board based on NXP LPC3250";
compatible = "ea,ea3250", "nxp,lpc3250";
#address-cells = <1>;
#size-cells = <1>;
memory {
device_type = "memory";
reg = <0 0x4000000>;
};
ahb {
mac: ethernet@31060000 {
phy-mode = "rmii";
use-iram;
};
/* Here, choose exactly one from: ohci, usbd */
ohci@31020000 {
transceiver = <&isp1301>;
status = "okay";
};
/*
usbd@31020000 {
transceiver = <&isp1301>;
status = "okay";
};
*/
/* 128MB Flash via SLC NAND controller */
slc: flash@20020000 {
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
nxp,wdr-clks = <14>;
nxp,wwidth = <260000000>;
nxp,whold = <104000000>;
nxp,wsetup = <200000000>;
nxp,rdr-clks = <14>;
nxp,rwidth = <34666666>;
nxp,rhold = <104000000>;
nxp,rsetup = <200000000>;
nand-on-flash-bbt;
gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
mtd0@00000000 {
label = "ea3250-boot";
reg = <0x00000000 0x00080000>;
read-only;
};
mtd1@00080000 {
label = "ea3250-uboot";
reg = <0x00080000 0x000c0000>;
read-only;
};
mtd2@00140000 {
label = "ea3250-kernel";
reg = <0x00140000 0x00400000>;
};
mtd3@00540000 {
label = "ea3250-rootfs";
reg = <0x00540000 0x07ac0000>;
};
};
apb {
uart5: serial@40090000 {
status = "okay";
};
uart3: serial@40080000 {
status = "okay";
};
uart6: serial@40098000 {
status = "okay";
};
i2c1: i2c@400A0000 {
clock-frequency = <100000>;
eeprom@50 {
compatible = "at,24c256";
reg = <0x50>;
};
eeprom@57 {
compatible = "at,24c64";
reg = <0x57>;
};
uda1380: uda1380@18 {
compatible = "nxp,uda1380";
reg = <0x18>;
power-gpio = <&gpio 0x59 0>;
reset-gpio = <&gpio 0x51 0>;
dac-clk = "wspll";
};
pca9532: pca9532@60 {
compatible = "nxp,pca9532";
gpio-controller;
#gpio-cells = <2>;
reg = <0x60>;
};
};
i2c2: i2c@400A8000 {
clock-frequency = <100000>;
};
i2cusb: i2c@31020300 {
clock-frequency = <100000>;
isp1301: usb-transceiver@2d {
compatible = "nxp,isp1301";
reg = <0x2d>;
};
};
sd@20098000 {
wp-gpios = <&pca9532 5 0>;
cd-gpios = <&pca9532 4 0>;
cd-inverted;
bus-width = <4>;
status = "okay";
};
};
fab {
uart1: serial@40014000 {
status = "okay";
};
};
};
};

74
arch/arm/boot/dts/lpc32xx.dtsi
View File

@ -35,13 +35,14 @@
slc: flash@20020000 {
compatible = "nxp,lpc3220-slc";
reg = <0x20020000 0x1000>;
status = "disable";
status = "disabled";
};
mlc: flash@200B0000 {
mlc: flash@200a8000 {
compatible = "nxp,lpc3220-mlc";
reg = <0x200B0000 0x1000>;
status = "disable";
reg = <0x200a8000 0x11000>;
interrupts = <11 0>;
status = "disabled";
};
dma@31000000 {
@ -57,21 +58,21 @@
compatible = "nxp,ohci-nxp", "usb-ohci";
reg = <0x31020000 0x300>;
interrupts = <0x3b 0>;
status = "disable";
status = "disabled";
};
usbd@31020000 {
compatible = "nxp,lpc3220-udc";
reg = <0x31020000 0x300>;
interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
status = "disable";
status = "disabled";
};
clcd@31040000 {
compatible = "arm,pl110", "arm,primecell";
reg = <0x31040000 0x1000>;
interrupts = <0x0e 0>;
status = "disable";
status = "disabled";
};
mac: ethernet@31060000 {
@ -114,9 +115,10 @@
};
sd@20098000 {
compatible = "arm,pl180", "arm,primecell";
compatible = "arm,pl18x", "arm,primecell";
reg = <0x20098000 0x1000>;
interrupts = <0x0f 0>, <0x0d 0>;
status = "disabled";
};
i2s1: i2s@2009C000 {
@ -124,24 +126,42 @@
reg = <0x2009C000 0x1000>;
};
/* UART5 first since it is the default console, ttyS0 */
uart5: serial@40090000 {
/* actually, ns16550a w/ 64 byte fifos! */
compatible = "nxp,lpc3220-uart";
reg = <0x40090000 0x1000>;
interrupts = <9 0>;
clock-frequency = <13000000>;
reg-shift = <2>;
status = "disabled";
};
uart3: serial@40080000 {
compatible = "nxp,serial";
compatible = "nxp,lpc3220-uart";
reg = <0x40080000 0x1000>;
interrupts = <7 0>;
clock-frequency = <13000000>;
reg-shift = <2>;
status = "disabled";
};
uart4: serial@40088000 {
compatible = "nxp,serial";
compatible = "nxp,lpc3220-uart";
reg = <0x40088000 0x1000>;
};
uart5: serial@40090000 {
compatible = "nxp,serial";
reg = <0x40090000 0x1000>;
interrupts = <8 0>;
clock-frequency = <13000000>;
reg-shift = <2>;
status = "disabled";
};
uart6: serial@40098000 {
compatible = "nxp,serial";
compatible = "nxp,lpc3220-uart";
reg = <0x40098000 0x1000>;
interrupts = <10 0>;
clock-frequency = <13000000>;
reg-shift = <2>;
status = "disabled";
};
i2c1: i2c@400A0000 {
@ -192,18 +212,24 @@
};
uart1: serial@40014000 {
compatible = "nxp,serial";
compatible = "nxp,lpc3220-hsuart";
reg = <0x40014000 0x1000>;
interrupts = <26 0>;
status = "disabled";
};
uart2: serial@40018000 {
compatible = "nxp,serial";
compatible = "nxp,lpc3220-hsuart";
reg = <0x40018000 0x1000>;
interrupts = <25 0>;
status = "disabled";
};
uart7: serial@4001C000 {
compatible = "nxp,serial";
reg = <0x4001C000 0x1000>;
uart7: serial@4001c000 {
compatible = "nxp,lpc3220-hsuart";
reg = <0x4001c000 0x1000>;
interrupts = <24 0>;
status = "disabled";
};
rtc@40024000 {
@ -235,19 +261,21 @@
compatible = "nxp,lpc3220-adc";
reg = <0x40048000 0x1000>;
interrupts = <0x27 0>;
status = "disable";
status = "disabled";
};
tsc@40048000 {
compatible = "nxp,lpc3220-tsc";
reg = <0x40048000 0x1000>;
interrupts = <0x27 0>;
status = "disable";
status = "disabled";
};
key@40050000 {
compatible = "nxp,lpc3220-key";
reg = <0x40050000 0x1000>;
interrupts = <54 0>;
status = "disabled";
};
};

61
arch/arm/boot/dts/phy3250.dts
View File

@ -54,6 +54,17 @@
#address-cells = <1>;
#size-cells = <1>;
nxp,wdr-clks = <14>;
nxp,wwidth = <40000000>;
nxp,whold = <100000000>;
nxp,wsetup = <100000000>;
nxp,rdr-clks = <14>;
nxp,rwidth = <40000000>;
nxp,rhold = <66666666>;
nxp,rsetup = <100000000>;
nand-on-flash-bbt;
gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
mtd0@00000000 {
label = "phy3250-boot";
reg = <0x00000000 0x00064000>;
@ -83,6 +94,14 @@
};
apb {
uart5: serial@40090000 {
status = "okay";
};
uart3: serial@40080000 {
status = "okay";
};
i2c1: i2c@400A0000 {
clock-frequency = <100000>;
@ -114,16 +133,58 @@
};
ssp0: ssp@20084000 {
#address-cells = <1>;
#size-cells = <0>;
pl022,num-chipselects = <1>;
cs-gpios = <&gpio 3 5 0>;
eeprom: at25@0 {
pl022,hierarchy = <0>;
pl022,interface = <0>;
pl022,slave-tx-disable = <0>;
pl022,com-mode = <0>;
pl022,rx-level-trig = <1>;
pl022,tx-level-trig = <1>;
pl022,ctrl-len = <11>;
pl022,wait-state = <0>;
pl022,duplex = <0>;
at25,byte-len = <0x8000>;
at25,addr-mode = <2>;
at25,page-size = <64>;
compatible = "atmel,at25";
reg = <0>;
spi-max-frequency = <5000000>;
};
};
sd@20098000 {
wp-gpios = <&gpio 3 0 0>;
cd-gpios = <&gpio 3 1 0>;
cd-inverted;
bus-width = <4>;
status = "okay";
};
};
fab {
uart2: serial@40018000 {
status = "okay";
};
tsc@40048000 {
status = "okay";
};
key@40050000 {
status = "okay";
keypad,num-rows = <1>;
keypad,num-columns = <1>;
nxp,debounce-delay-ms = <3>;
nxp,scan-delay-ms = <34>;
linux,keymap = <0x00000002>;
};
};
};

11
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
View File

@ -55,6 +55,8 @@
reg-io-width = <4>;
smsc,irq-active-high;
smsc,irq-push-pull;
vdd33a-supply = <&v2m_fixed_3v3>;
vddvario-supply = <&v2m_fixed_3v3>;
};
usb@2,03000000 {
@ -157,6 +159,7 @@
v2m_timer23: timer@120000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x120000 0x1000>;
interrupts = <3>;
};
/* DVI I2C bus */
@ -197,5 +200,13 @@
interrupts = <14>;
};
};
v2m_fixed_3v3: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};

11
arch/arm/boot/dts/vexpress-v2m.dtsi
View File

@ -54,6 +54,8 @@
reg-io-width = <4>;
smsc,irq-active-high;
smsc,irq-push-pull;
vdd33a-supply = <&v2m_fixed_3v3>;
vddvario-supply = <&v2m_fixed_3v3>;
};
usb@3,03000000 {
@ -156,6 +158,7 @@
v2m_timer23: timer@12000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x12000 0x1000>;
interrupts = <3>;
};
/* DVI I2C bus */
@ -196,5 +199,13 @@
interrupts = <14>;
};
};
v2m_fixed_3v3: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};

36
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
View File

@ -14,8 +14,8 @@
arm,hbi = <0x237>;
compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
@ -47,23 +47,23 @@
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>;
reg = <0 0x80000000 0 0x40000000>;
};
hdlcd@2b000000 {
compatible = "arm,hdlcd";
reg = <0x2b000000 0x1000>;
reg = <0 0x2b000000 0 0x1000>;
interrupts = <0 85 4>;
};
memory-controller@2b0a0000 {
compatible = "arm,pl341", "arm,primecell";
reg = <0x2b0a0000 0x1000>;
reg = <0 0x2b0a0000 0 0x1000>;
};
wdt@2b060000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x2b060000 0x1000>;
reg = <0 0x2b060000 0 0x1000>;
interrupts = <98>;
};
@ -72,23 +72,23 @@
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x2c001000 0x1000>,
<0x2c002000 0x1000>,
<0x2c004000 0x2000>,
<0x2c006000 0x2000>;
reg = <0 0x2c001000 0 0x1000>,
<0 0x2c002000 0 0x1000>,
<0 0x2c004000 0 0x2000>,
<0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
memory-controller@7ffd0000 {
compatible = "arm,pl354", "arm,primecell";
reg = <0x7ffd0000 0x1000>;
reg = <0 0x7ffd0000 0 0x1000>;
interrupts = <0 86 4>,
<0 87 4>;
};
dma@7ffb0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x7ffb0000 0x1000>;
reg = <0 0x7ffb0000 0 0x1000>;
interrupts = <0 92 4>,
<0 88 4>,
<0 89 4>,
@ -111,12 +111,12 @@
};
motherboard {
ranges = <0 0 0x08000000 0x04000000>,
<1 0 0x14000000 0x04000000>,
<2 0 0x18000000 0x04000000>,
<3 0 0x1c000000 0x04000000>,
<4 0 0x0c000000 0x04000000>,
<5 0 0x10000000 0x04000000>;
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,
<2 0 0 0x18000000 0x04000000>,
<3 0 0 0x1c000000 0x04000000>,
<4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 0 4>,

188
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts Normal file
View File

@ -0,0 +1,188 @@
/*
* ARM Ltd. Versatile Express
*
* CoreTile Express A15x2 A7x3
* Cortex-A15_A7 MPCore (V2P-CA15_A7)
*
* HBI-0249A
*/
/dts-v1/;
/ {
model = "V2P-CA15_CA7";
arm,hbi = <0x249>;
compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
aliases {
serial0 = &v2m_serial0;
serial1 = &v2m_serial1;
serial2 = &v2m_serial2;
serial3 = &v2m_serial3;
i2c0 = &v2m_i2c_dvi;
i2c1 = &v2m_i2c_pcie;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
};
/* A7s disabled till big.LITTLE patches are available...
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
};
cpu4: cpu@4 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
};
*/
};
memory@80000000 {
device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
wdt@2a490000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0 0x2a490000 0 0x1000>;
interrupts = <98>;
};
hdlcd@2b000000 {
compatible = "arm,hdlcd";
reg = <0 0x2b000000 0 0x1000>;
interrupts = <0 85 4>;
};
memory-controller@2b0a0000 {
compatible = "arm,pl341", "arm,primecell";
reg = <0 0x2b0a0000 0 0x1000>;
};
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x2c001000 0 0x1000>,
<0 0x2c002000 0 0x1000>,
<0 0x2c004000 0 0x2000>,
<0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
memory-controller@7ffd0000 {
compatible = "arm,pl354", "arm,primecell";
reg = <0 0x7ffd0000 0 0x1000>;
interrupts = <0 86 4>,
<0 87 4>;
};
dma@7ff00000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0 0x7ff00000 0 0x1000>;
interrupts = <0 92 4>,
<0 88 4>,
<0 89 4>,
<0 90 4>,
<0 91 4>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
};
pmu {
compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
interrupts = <0 68 4>,
<0 69 4>;
};
motherboard {
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,
<2 0 0 0x18000000 0x04000000>,
<3 0 0 0x1c000000 0x04000000>,
<4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 0 4>,
<0 0 1 &gic 0 1 4>,
<0 0 2 &gic 0 2 4>,
<0 0 3 &gic 0 3 4>,
<0 0 4 &gic 0 4 4>,
<0 0 5 &gic 0 5 4>,
<0 0 6 &gic 0 6 4>,
<0 0 7 &gic 0 7 4>,
<0 0 8 &gic 0 8 4>,
<0 0 9 &gic 0 9 4>,
<0 0 10 &gic 0 10 4>,
<0 0 11 &gic 0 11 4>,
<0 0 12 &gic 0 12 4>,
<0 0 13 &gic 0 13 4>,
<0 0 14 &gic 0 14 4>,
<0 0 15 &gic 0 15 4>,
<0 0 16 &gic 0 16 4>,
<0 0 17 &gic 0 17 4>,
<0 0 18 &gic 0 18 4>,
<0 0 19 &gic 0 19 4>,
<0 0 20 &gic 0 20 4>,
<0 0 21 &gic 0 21 4>,
<0 0 22 &gic 0 22 4>,
<0 0 23 &gic 0 23 4>,
<0 0 24 &gic 0 24 4>,
<0 0 25 &gic 0 25 4>,
<0 0 26 &gic 0 26 4>,
<0 0 27 &gic 0 27 4>,
<0 0 28 &gic 0 28 4>,
<0 0 29 &gic 0 29 4>,
<0 0 30 &gic 0 30 4>,
<0 0 31 &gic 0 31 4>,
<0 0 32 &gic 0 32 4>,
<0 0 33 &gic 0 33 4>,
<0 0 34 &gic 0 34 4>,
<0 0 35 &gic 0 35 4>,
<0 0 36 &gic 0 36 4>,
<0 0 37 &gic 0 37 4>,
<0 0 38 &gic 0 38 4>,
<0 0 39 &gic 0 39 4>,
<0 0 40 &gic 0 40 4>,
<0 0 41 &gic 0 41 4>,
<0 0 42 &gic 0 42 4>;
};
};
/include/ "vexpress-v2m-rs1.dtsi"

24
arch/arm/configs/lpc32xx_defconfig
View File

@ -1,5 +1,7 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
@ -16,8 +18,6 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_ARCH_LPC32XX=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
@ -52,13 +52,17 @@ CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_MUSEUM_IDS=y
CONFIG_MTD_NAND_SLC_LPC32XX=y
CONFIG_MTD_NAND_MLC_LPC32XX=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_AT25=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
@ -79,16 +83,22 @@ CONFIG_LPC_ENET=y
# CONFIG_NET_VENDOR_STMICRO is not set
CONFIG_SMSC_PHY=y
# CONFIG_WLAN is not set
CONFIG_INPUT_MATRIXKMAP=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_LPC32XX=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_LPC32XX=y
CONFIG_SERIO_LIBPS2=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_HS_LPC32XX=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
@ -96,7 +106,8 @@ CONFIG_I2C_PNX=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
CONFIG_SENSORS_DS620=y
CONFIG_SENSORS_MAX6639=y
CONFIG_WATCHDOG=y
CONFIG_PNX4008_WATCHDOG=y
CONFIG_FB=y
@ -133,6 +144,8 @@ CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_PCA9532=y
CONFIG_LEDS_PCA9532_GPIO=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
@ -146,10 +159,10 @@ CONFIG_RTC_DRV_DS1374=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_LPC32XX=y
CONFIG_DMADEVICES=y
CONFIG_AMBA_PL08X=y
CONFIG_STAGING=y
CONFIG_IIO=y
CONFIG_LPC32XX_ADC=y
CONFIG_MAX517=y
CONFIG_IIO=y
CONFIG_EXT2_FS=y
CONFIG_AUTOFS4_FS=y
CONFIG_MSDOS_FS=y
@ -159,7 +172,6 @@ CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_WBUF_VERIFY=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y

1
arch/arm/mach-davinci/Kconfig
View File

@ -4,6 +4,7 @@ config AINTC
bool
config CP_INTC
select IRQ_DOMAIN
bool
config ARCH_DAVINCI_DMx

1
arch/arm/mach-davinci/Makefile
View File

@ -39,3 +39,4 @@ obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_SUSPEND) += pm.o sleep.o
obj-$(CONFIG_HAVE_CLK) += pm_domain.o

63
arch/arm/mach-davinci/cp_intc.c
View File

@ -9,8 +9,10 @@
* kind, whether express or implied.
*/
#include <linux/export.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <mach/common.h>
@ -28,7 +30,7 @@ static inline void cp_intc_write(unsigned long value, unsigned offset)
static void cp_intc_ack_irq(struct irq_data *d)
{
cp_intc_write(d->irq, CP_INTC_SYS_STAT_IDX_CLR);
cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR);
}
/* Disable interrupt */
@ -36,20 +38,20 @@ static void cp_intc_mask_irq(struct irq_data *d)
{
/* XXX don't know why we need to disable nIRQ here... */
cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_CLR);
cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR);
cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
}
/* Enable interrupt */
static void cp_intc_unmask_irq(struct irq_data *d)
{
cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_SET);
cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET);
}
static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
{
unsigned reg = BIT_WORD(d->irq);
unsigned mask = BIT_MASK(d->irq);
unsigned reg = BIT_WORD(d->hwirq);
unsigned mask = BIT_MASK(d->hwirq);
unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg));
@ -99,18 +101,36 @@ static struct irq_chip cp_intc_irq_chip = {
.irq_set_wake = cp_intc_set_wake,
};
void __init cp_intc_init(void)
static struct irq_domain *cp_intc_domain;
static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
unsigned long num_irq = davinci_soc_info.intc_irq_num;
pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
irq_set_chip(virq, &cp_intc_irq_chip);
set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
irq_set_handler(virq, handle_edge_irq);
return 0;
}
static const struct irq_domain_ops cp_intc_host_ops = {
.map = cp_intc_host_map,
.xlate = irq_domain_xlate_onetwocell,
};
int __init __cp_intc_init(struct device_node *node)
{
u32 num_irq = davinci_soc_info.intc_irq_num;
u8 *irq_prio = davinci_soc_info.intc_irq_prios;
u32 *host_map = davinci_soc_info.intc_host_map;
unsigned num_reg = BITS_TO_LONGS(num_irq);
int i;
int i, irq_base;
davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
if (WARN_ON(!davinci_intc_base))
return;
return -EINVAL;
cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
@ -165,13 +185,28 @@ void __init cp_intc_init(void)
for (i = 0; host_map[i] != -1; i++)
cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
/* Set up genirq dispatching for cp_intc */
for (i = 0; i < num_irq; i++) {
irq_set_chip(i, &cp_intc_irq_chip);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
irq_set_handler(i, handle_edge_irq);
irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
if (irq_base < 0) {
pr_warn("Couldn't allocate IRQ numbers\n");
irq_base = 0;
}
/* create a legacy host */
cp_intc_domain = irq_domain_add_legacy(node, num_irq,
irq_base, 0, &cp_intc_host_ops, NULL);
if (!cp_intc_domain) {
pr_err("cp_intc: failed to allocate irq host!\n");
return -EINVAL;
}
/* Enable global interrupt */
cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);
return 0;
}
void __init cp_intc_init(void)
{
__cp_intc_init(NULL);
}

64
arch/arm/mach-davinci/pm_domain.c Normal file
View File

@ -0,0 +1,64 @@
/*
* Runtime PM support code for DaVinci
*
* Author: Kevin Hilman
*
* Copyright (C) 2012 Texas Instruments, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/pm_runtime.h>
#include <linux/pm_clock.h>
#include <linux/platform_device.h>
#ifdef CONFIG_PM_RUNTIME
static int davinci_pm_runtime_suspend(struct device *dev)
{
int ret;
dev_dbg(dev, "%s\n", __func__);
ret = pm_generic_runtime_suspend(dev);
if (ret)
return ret;
ret = pm_clk_suspend(dev);
if (ret) {
pm_generic_runtime_resume(dev);
return ret;
}
return 0;
}
static int davinci_pm_runtime_resume(struct device *dev)
{
dev_dbg(dev, "%s\n", __func__);
pm_clk_resume(dev);
return pm_generic_runtime_resume(dev);
}
#endif
static struct dev_pm_domain davinci_pm_domain = {
.ops = {
SET_RUNTIME_PM_OPS(davinci_pm_runtime_suspend,
davinci_pm_runtime_resume, NULL)
USE_PLATFORM_PM_SLEEP_OPS
},
};
static struct pm_clk_notifier_block platform_bus_notifier = {
.pm_domain = &davinci_pm_domain,
};
static int __init davinci_pm_runtime_init(void)
{
pm_clk_add_notifier(&platform_bus_type, &platform_bus_notifier);
return 0;
}
core_initcall(davinci_pm_runtime_init);

96
arch/arm/mach-ep93xx/core.c
View File

@ -797,6 +797,102 @@ static struct platform_device ep93xx_wdt_device = {
.resource = ep93xx_wdt_resources,
};
/*************************************************************************
* EP93xx IDE
*************************************************************************/
static struct resource ep93xx_ide_resources[] = {
DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38),
DEFINE_RES_IRQ(IRQ_EP93XX_EXT3),
};
static struct platform_device ep93xx_ide_device = {
.name = "ep93xx-ide",
.id = -1,
.dev = {
.dma_mask = &ep93xx_ide_device.dev.coherent_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(ep93xx_ide_resources),
.resource = ep93xx_ide_resources,
};
void __init ep93xx_register_ide(void)
{
platform_device_register(&ep93xx_ide_device);
}
int ep93xx_ide_acquire_gpio(struct platform_device *pdev)
{
int err;
int i;
err = gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev));
if (err)
return err;
err = gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev));
if (err)
goto fail_egpio15;
for (i = 2; i < 8; i++) {
err = gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev));
if (err)
goto fail_gpio_e;
}
for (i = 4; i < 8; i++) {
err = gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev));
if (err)
goto fail_gpio_g;
}
for (i = 0; i < 8; i++) {
err = gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev));
if (err)
goto fail_gpio_h;
}
/* GPIO ports E[7:2], G[7:4] and H used by IDE */
ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
EP93XX_SYSCON_DEVCFG_GONIDE |
EP93XX_SYSCON_DEVCFG_HONIDE);
return 0;
fail_gpio_h:
for (--i; i >= 0; --i)
gpio_free(EP93XX_GPIO_LINE_H(i));
i = 8;
fail_gpio_g:
for (--i; i >= 4; --i)
gpio_free(EP93XX_GPIO_LINE_G(i));
i = 8;
fail_gpio_e:
for (--i; i >= 2; --i)
gpio_free(EP93XX_GPIO_LINE_E(i));
gpio_free(EP93XX_GPIO_LINE_EGPIO15);
fail_egpio15:
gpio_free(EP93XX_GPIO_LINE_EGPIO2);
return err;
}
EXPORT_SYMBOL(ep93xx_ide_acquire_gpio);
void ep93xx_ide_release_gpio(struct platform_device *pdev)
{
int i;
for (i = 2; i < 8; i++)
gpio_free(EP93XX_GPIO_LINE_E(i));
for (i = 4; i < 8; i++)
gpio_free(EP93XX_GPIO_LINE_G(i));
for (i = 0; i < 8; i++)
gpio_free(EP93XX_GPIO_LINE_H(i));
gpio_free(EP93XX_GPIO_LINE_EGPIO15);
gpio_free(EP93XX_GPIO_LINE_EGPIO2);
/* GPIO ports E[7:2], G[7:4] and H used by GPIO */
ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
EP93XX_SYSCON_DEVCFG_GONIDE |
EP93XX_SYSCON_DEVCFG_HONIDE);
}
EXPORT_SYMBOL(ep93xx_ide_release_gpio);
void __init ep93xx_init_devices(void)
{
/* Disallow access to MaverickCrunch initially */

24
arch/arm/mach-ep93xx/edb93xx.c
View File

@ -233,6 +233,29 @@ static void __init edb93xx_register_fb(void)
}
/*************************************************************************
* EDB93xx IDE
*************************************************************************/
static int __init edb93xx_has_ide(void)
{
/*
* Although EDB9312 and EDB9315 do have IDE capability, they have
* INTRQ line wired as pull-up, which makes using IDE interface
* problematic.
*/
return machine_is_edb9312() || machine_is_edb9315() ||
machine_is_edb9315a();
}
static void __init edb93xx_register_ide(void)
{
if (!edb93xx_has_ide())
return;
ep93xx_register_ide();
}
static void __init edb93xx_init_machine(void)
{
ep93xx_init_devices();
@ -243,6 +266,7 @@ static void __init edb93xx_init_machine(void)
edb93xx_register_i2s();
edb93xx_register_pwm();
edb93xx_register_fb();
edb93xx_register_ide();
}

3
arch/arm/mach-ep93xx/include/mach/platform.h
View File

@ -48,6 +48,9 @@ void ep93xx_register_i2s(void);
int ep93xx_i2s_acquire(void);
void ep93xx_i2s_release(void);
void ep93xx_register_ac97(void);
void ep93xx_register_ide(void);
int ep93xx_ide_acquire_gpio(struct platform_device *pdev);
void ep93xx_ide_release_gpio(struct platform_device *pdev);
void ep93xx_init_devices(void);
extern struct sys_timer ep93xx_timer;

1
arch/arm/mach-ep93xx/soc.h
View File

@ -69,6 +69,7 @@
#define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000)
#define EP93XX_IDE_PHYS_BASE EP93XX_AHB_PHYS(0x000a0000)
#define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000)
#define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000)

3
arch/arm/mach-exynos/common.c
View File

@ -540,7 +540,8 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
.map = combiner_irq_domain_map,
};
void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
static void __init combiner_init(void __iomem *combiner_base,
struct device_node *np)
{
int i, irq, irq_base;
unsigned int max_nr, nr_irq;

5
arch/arm/mach-exynos/include/mach/regs-pmu.h
View File

@ -232,6 +232,11 @@
#define EXYNOS5_USB_CFG S5P_PMUREG(0x0230)
#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)
#define EXYNOS5_SYS_WDTRESET (1 << 20)
#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)

20
arch/arm/mach-exynos/include/mach/regs-usb-phy.h
View File

@ -35,11 +35,21 @@
#define PHY1_COMMON_ON_N (1 << 7)
#define PHY0_COMMON_ON_N (1 << 4)
#define PHY0_ID_PULLUP (1 << 2)
#define CLKSEL_MASK (0x3 << 0)
#define CLKSEL_SHIFT (0)
#define CLKSEL_48M (0x0 << 0)
#define CLKSEL_12M (0x2 << 0)
#define CLKSEL_24M (0x3 << 0)
#define EXYNOS4_CLKSEL_SHIFT (0)
#define EXYNOS4210_CLKSEL_MASK (0x3 << 0)
#define EXYNOS4210_CLKSEL_48M (0x0 << 0)
#define EXYNOS4210_CLKSEL_12M (0x2 << 0)
#define EXYNOS4210_CLKSEL_24M (0x3 << 0)
#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0)
#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0)
#define EXYNOS4X12_CLKSEL_10M (0x1 << 0)
#define EXYNOS4X12_CLKSEL_12M (0x2 << 0)
#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0)
#define EXYNOS4X12_CLKSEL_20M (0x4 << 0)
#define EXYNOS4X12_CLKSEL_24M (0x5 << 0)
#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08)
#define HOST_LINK_PORT_SWRST_MASK (0xf << 6)

18
arch/arm/mach-exynos/pmu.c
View File

@ -315,7 +315,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
{ PMU_TABLE_END,},
};
void __iomem *exynos5_list_both_cnt_feed[] = {
static void __iomem *exynos5_list_both_cnt_feed[] = {
EXYNOS5_ARM_CORE0_OPTION,
EXYNOS5_ARM_CORE1_OPTION,
EXYNOS5_ARM_COMMON_OPTION,
@ -329,7 +329,7 @@ void __iomem *exynos5_list_both_cnt_feed[] = {
EXYNOS5_TOP_PWR_SYSMEM_OPTION,
};
void __iomem *exynos5_list_diable_wfi_wfe[] = {
static void __iomem *exynos5_list_diable_wfi_wfe[] = {
EXYNOS5_ARM_CORE1_OPTION,
EXYNOS5_FSYS_ARM_OPTION,
EXYNOS5_ISP_ARM_OPTION,
@ -390,6 +390,8 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
static int __init exynos_pmu_init(void)
{
unsigned int value;
exynos_pmu_config = exynos4210_pmu_config;
if (soc_is_exynos4210()) {
@ -399,6 +401,18 @@ static int __init exynos_pmu_init(void)
exynos_pmu_config = exynos4x12_pmu_config;
pr_info("EXYNOS4x12 PMU Initialize\n");
} else if (soc_is_exynos5250()) {
/*
* When SYS_WDTRESET is set, watchdog timer reset request
* is ignored by power management unit.
*/
value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
value &= ~EXYNOS5_SYS_WDTRESET;
__raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
value &= ~EXYNOS5_SYS_WDTRESET;
__raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
exynos_pmu_config = exynos5250_pmu_config;
pr_info("EXYNOS5250 PMU Initialize\n");
} else {

60
arch/arm/mach-exynos/setup-usb-phy.c
View File

@ -31,27 +31,55 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
struct clk *xusbxti_clk;
u32 phyclk;
/* set clock frequency for PLL */
phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
switch (clk_get_rate(xusbxti_clk)) {
case 12 * MHZ:
phyclk |= CLKSEL_12M;
break;
case 24 * MHZ:
phyclk |= CLKSEL_24M;
break;
default:
case 48 * MHZ:
/* default reference clock */
break;
if (soc_is_exynos4210()) {
/* set clock frequency for PLL */
phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;
switch (clk_get_rate(xusbxti_clk)) {
case 12 * MHZ:
phyclk |= EXYNOS4210_CLKSEL_12M;
break;
case 48 * MHZ:
phyclk |= EXYNOS4210_CLKSEL_48M;
break;
default:
case 24 * MHZ:
phyclk |= EXYNOS4210_CLKSEL_24M;
break;
}
writel(phyclk, EXYNOS4_PHYCLK);
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
/* set clock frequency for PLL */
phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;
switch (clk_get_rate(xusbxti_clk)) {
case 9600 * KHZ:
phyclk |= EXYNOS4X12_CLKSEL_9600K;
break;
case 10 * MHZ:
phyclk |= EXYNOS4X12_CLKSEL_10M;
break;
case 12 * MHZ:
phyclk |= EXYNOS4X12_CLKSEL_12M;
break;
case 19200 * KHZ:
phyclk |= EXYNOS4X12_CLKSEL_19200K;
break;
case 20 * MHZ:
phyclk |= EXYNOS4X12_CLKSEL_20M;
break;
default:
case 24 * MHZ:
/* default reference clock */
phyclk |= EXYNOS4X12_CLKSEL_24M;
break;
}
writel(phyclk, EXYNOS4_PHYCLK);
}
clk_put(xusbxti_clk);
}
writel(phyclk, EXYNOS4_PHYCLK);
}
static int exynos4210_usb_phy0_init(struct platform_device *pdev)

3
arch/arm/mach-imx/Kconfig
View File

@ -73,7 +73,7 @@ config SOC_IMX31
config SOC_IMX35
bool
select CPU_V6
select CPU_V6K
select ARCH_MXC_IOMUX_V3
select COMMON_CLK
select HAVE_EPIT
@ -588,6 +588,7 @@ config MACH_MX35_3DS
select IMX_HAVE_PLATFORM_IPU_CORE
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_RTC
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for MX35PDK platform. This includes specific

4
arch/arm/mach-imx/devices-imx35.h
View File

@ -68,6 +68,10 @@ extern const struct imx_mxc_nand_data imx35_mxc_nand_data;
#define imx35_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
extern const struct imx_mxc_rtc_data imx35_mxc_rtc_data;
#define imx35_add_mxc_rtc() \
imx_add_mxc_rtc(&imx35_mxc_rtc_data)
extern const struct imx_mxc_w1_data imx35_mxc_w1_data;
#define imx35_add_mxc_w1() \
imx_add_mxc_w1(&imx35_mxc_w1_data)

24
arch/arm/mach-imx/ehci-imx25.c
View File

@ -24,14 +24,18 @@
#define MX25_OTG_SIC_SHIFT 29
#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
#define MX25_OTG_PM_BIT (1 << 24)
#define MX25_OTG_PP_BIT (1 << 11)
#define MX25_OTG_OCPOL_BIT (1 << 3)
#define MX25_H1_SIC_SHIFT 21
#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
#define MX25_H1_PP_BIT (1 << 18)
#define MX25_H1_PM_BIT (1 << 8)
#define MX25_H1_IPPUE_UP_BIT (1 << 7)
#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
#define MX25_H1_TLL_BIT (1 << 5)
#define MX25_H1_USBTE_BIT (1 << 4)
#define MX25_H1_OCPOL_BIT (1 << 2)
int mx25_initialize_usb_hw(int port, unsigned int flags)
{
@ -41,21 +45,35 @@ int mx25_initialize_usb_hw(int port, unsigned int flags)
switch (port) {
case 0: /* OTG port */
v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT);
v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
MX25_OTG_OCPOL_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX25_OTG_PM_BIT;
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
v |= MX25_OTG_PP_BIT;
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
v |= MX25_OTG_OCPOL_BIT;
break;
case 1: /* H1 port */
v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT |
MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX25_H1_PM_BIT;
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
v |= MX25_H1_PP_BIT;
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
v |= MX25_H1_OCPOL_BIT;
if (!(flags & MXC_EHCI_TTL_ENABLED))
v |= MX25_H1_TLL_BIT;

24
arch/arm/mach-imx/ehci-imx35.c
View File

@ -24,14 +24,18 @@
#define MX35_OTG_SIC_SHIFT 29
#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
#define MX35_OTG_PM_BIT (1 << 24)
#define MX35_OTG_PP_BIT (1 << 11)
#define MX35_OTG_OCPOL_BIT (1 << 3)
#define MX35_H1_SIC_SHIFT 21
#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
#define MX35_H1_PP_BIT (1 << 18)
#define MX35_H1_PM_BIT (1 << 8)
#define MX35_H1_IPPUE_UP_BIT (1 << 7)
#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
#define MX35_H1_TLL_BIT (1 << 5)
#define MX35_H1_USBTE_BIT (1 << 4)
#define MX35_H1_OCPOL_BIT (1 << 2)
int mx35_initialize_usb_hw(int port, unsigned int flags)
{
@ -41,21 +45,35 @@ int mx35_initialize_usb_hw(int port, unsigned int flags)
switch (port) {
case 0: /* OTG port */
v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
MX35_OTG_OCPOL_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX35_OTG_PM_BIT;
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
v |= MX35_OTG_PP_BIT;
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
v |= MX35_OTG_OCPOL_BIT;
break;
case 1: /* H1 port */
v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX35_H1_PM_BIT;
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
v |= MX35_H1_PP_BIT;
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
v |= MX35_H1_OCPOL_BIT;
if (!(flags & MXC_EHCI_TTL_ENABLED))
v |= MX35_H1_TLL_BIT;

31
arch/arm/mach-imx/ehci-imx5.c
View File

@ -28,11 +28,14 @@
#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
/* USB_PHY_CTRL_FUNC */
#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */
#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */
#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */
/* USBH2CTRL */
#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
@ -80,13 +83,21 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
if (flags & MXC_EHCI_INTERNAL_PHY) {
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
else
v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
/* OC/USBPWR is not used */
v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
} else {
/* OC/USBPWR is used */
v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
} else {
/* OC/USBPWR is not used */
v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
}
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
else
v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
@ -95,9 +106,9 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
else
v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v |= MXC_OTG_UCTRL_OPM_BIT;
else
v &= ~MXC_OTG_UCTRL_OPM_BIT;
else
v |= MXC_OTG_UCTRL_OPM_BIT;
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
}
break;
@ -113,12 +124,16 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
}
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/
else
v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
v |= MXC_H1_OC_POL_BIT;
else
v &= ~MXC_H1_OC_POL_BIT;
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
else
@ -142,7 +157,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
}
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/
else
v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);

1
arch/arm/mach-imx/mach-mx35_3ds.c
View File

@ -572,6 +572,7 @@ static void __init mx35_3ds_init(void)
imx35_add_fec(NULL);
imx35_add_imx2_wdt();
imx35_add_mxc_rtc();
platform_add_devices(devices, ARRAY_SIZE(devices));
imx35_add_imx_uart0(&uart_pdata);

32
arch/arm/mach-lpc32xx/Kconfig
View File

@ -1,32 +0,0 @@
if ARCH_LPC32XX
menu "Individual UART enable selections"
config ARCH_LPC32XX_UART3_SELECT
bool "Add support for standard UART3"
help
Adds support for standard UART 3 when the 8250 serial support
is enabled.
config ARCH_LPC32XX_UART4_SELECT
bool "Add support for standard UART4"
help
Adds support for standard UART 4 when the 8250 serial support
is enabled.
config ARCH_LPC32XX_UART5_SELECT
bool "Add support for standard UART5"
default y
help
Adds support for standard UART 5 when the 8250 serial support
is enabled.
config ARCH_LPC32XX_UART6_SELECT
bool "Add support for standard UART6"
help
Adds support for standard UART 6 when the 8250 serial support
is enabled.
endmenu
endif

1
arch/arm/mach-lpc32xx/Makefile.boot
View File

@ -2,3 +2,4 @@
params_phys-y := 0x80000100
initrd_phys-y := 0x82000000
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb

123
arch/arm/mach-lpc32xx/clock.c
View File

@ -607,6 +607,19 @@ static struct clk clk_dma = {
.get_rate = local_return_parent_rate,
};
static struct clk clk_pwm = {
.parent = &clk_pclk,
.enable = local_onoff_enable,
.enable_reg = LPC32XX_CLKPWR_PWM_CLK_CTRL,
.enable_mask = LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN |
LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK |
LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(1) |
LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN |
LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK |
LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(1),
.get_rate = local_return_parent_rate,
};
static struct clk clk_uart3 = {
.parent = &clk_pclk,
.enable = local_onoff_enable,
@ -691,10 +704,21 @@ static struct clk clk_nand = {
.parent = &clk_hclk,
.enable = local_onoff_enable,
.enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
.enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
.enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN |
LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
.get_rate = local_return_parent_rate,
};
static struct clk clk_nand_mlc = {
.parent = &clk_hclk,
.enable = local_onoff_enable,
.enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
.enable_mask = LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN |
LPC32XX_CLKPWR_NANDCLK_DMA_INT |
LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC,
.get_rate = local_return_parent_rate,
};
static struct clk clk_i2s0 = {
.parent = &clk_hclk,
.enable = local_onoff_enable,
@ -707,7 +731,8 @@ static struct clk clk_i2s1 = {
.parent = &clk_hclk,
.enable = local_onoff_enable,
.enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
.enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
.enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN |
LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA,
.get_rate = local_return_parent_rate,
};
@ -727,14 +752,77 @@ static struct clk clk_rtc = {
.get_rate = local_return_parent_rate,
};
static int local_usb_enable(struct clk *clk, int enable)
{
u32 tmp;
if (enable) {
/* Set up I2C pull levels */
tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE;
__raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
}
return local_onoff_enable(clk, enable);
}
static struct clk clk_usbd = {
.parent = &clk_usbpll,
.enable = local_onoff_enable,
.enable = local_usb_enable,
.enable_reg = LPC32XX_CLKPWR_USB_CTRL,
.enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
.get_rate = local_return_parent_rate,
};
#define OTG_ALWAYS_MASK (LPC32XX_USB_OTG_OTG_CLOCK_ON | \
LPC32XX_USB_OTG_I2C_CLOCK_ON)
static int local_usb_otg_enable(struct clk *clk, int enable)
{
int to = 1000;
if (enable) {
__raw_writel(clk->enable_mask, clk->enable_reg);
while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) &
clk->enable_mask) != clk->enable_mask) && (to > 0))
to--;
} else {
__raw_writel(OTG_ALWAYS_MASK, clk->enable_reg);
while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) &
OTG_ALWAYS_MASK) != OTG_ALWAYS_MASK) && (to > 0))
to--;
}
if (to)
return 0;
else
return -1;
}
static struct clk clk_usb_otg_dev = {
.parent = &clk_usbpll,
.enable = local_usb_otg_enable,
.enable_reg = LPC32XX_USB_OTG_CLK_CTRL,
.enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON |
LPC32XX_USB_OTG_OTG_CLOCK_ON |
LPC32XX_USB_OTG_DEV_CLOCK_ON |
LPC32XX_USB_OTG_I2C_CLOCK_ON,
.get_rate = local_return_parent_rate,
};
static struct clk clk_usb_otg_host = {
.parent = &clk_usbpll,
.enable = local_usb_otg_enable,
.enable_reg = LPC32XX_USB_OTG_CLK_CTRL,
.enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON |
LPC32XX_USB_OTG_OTG_CLOCK_ON |
LPC32XX_USB_OTG_HOST_CLOCK_ON |
LPC32XX_USB_OTG_I2C_CLOCK_ON,
.get_rate = local_return_parent_rate,
};
static int tsc_onoff_enable(struct clk *clk, int enable)
{
u32 tmp;
@ -800,11 +888,17 @@ static int mmc_onoff_enable(struct clk *clk, int enable)
u32 tmp;
tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
~(LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN |
LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS |
LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS |
LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS |
LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS);
/* If rate is 0, disable clock */
if (enable != 0)
tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
__raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
@ -853,7 +947,7 @@ static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
static int mmc_set_rate(struct clk *clk, unsigned long rate)
{
u32 oldclk, tmp;
u32 tmp;
unsigned long prate, div, crate = mmc_round_rate(clk, rate);
prate = clk->parent->get_rate(clk->parent);
@ -861,16 +955,12 @@ static int mmc_set_rate(struct clk *clk, unsigned long rate)
div = prate / crate;
/* The MMC clock must be on when accessing an MMC register */
oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
__raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
LPC32XX_CLKPWR_MS_CTRL);
tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div) |
LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
__raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
__raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
return 0;
}
@ -1111,6 +1201,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9),
CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm),
CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),
@ -1120,8 +1211,9 @@ static struct clk_lookup lookups[] = {
CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2),
CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0),
CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1),
CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan),
CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand),
CLKDEV_INIT("40050000.key", NULL, &clk_kscan),
CLKDEV_INIT("20020000.flash", NULL, &clk_nand),
CLKDEV_INIT("200a8000.flash", NULL, &clk_nand_mlc),
CLKDEV_INIT("40048000.adc", NULL, &clk_adc),
CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0),
CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1),
@ -1130,6 +1222,9 @@ static struct clk_lookup lookups[] = {
CLKDEV_INIT("31060000.ethernet", NULL, &clk_net),
CLKDEV_INIT("dev:clcd", NULL, &clk_lcd),
CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd),
CLKDEV_INIT("31020000.ohci", "ck_usbd", &clk_usbd),
CLKDEV_INIT("31020000.usbd", "ck_usb_otg", &clk_usb_otg_dev),
CLKDEV_INIT("31020000.ohci", "ck_usb_otg", &clk_usb_otg_host),
CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc),
};

10
arch/arm/mach-lpc32xx/common.c
View File

@ -26,6 +26,7 @@
#include <linux/io.h>
#include <asm/mach/map.h>
#include <asm/system_info.h>
#include <mach/hardware.h>
#include <mach/platform.h>
@ -224,7 +225,7 @@ void lpc23xx_restart(char mode, const char *cmd)
;
}
static int __init lpc32xx_display_uid(void)
static int __init lpc32xx_check_uid(void)
{
u32 uid[4];
@ -233,6 +234,11 @@ static int __init lpc32xx_display_uid(void)
printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
uid[3], uid[2], uid[1], uid[0]);
if (!system_serial_low && !system_serial_high) {
system_serial_low = uid[0];
system_serial_high = uid[1];
}
return 1;
}
arch_initcall(lpc32xx_display_uid);
arch_initcall(lpc32xx_check_uid);

2
arch/arm/mach-lpc32xx/include/mach/gpio.h
View File

@ -3,6 +3,4 @@
#include "gpio-lpc32xx.h"
#define ARCH_NR_GPIOS (LPC32XX_GPO_P3_GRP + LPC32XX_GPO_P3_MAX)
#endif /* __MACH_GPIO_H */

14
arch/arm/mach-lpc32xx/include/mach/platform.h
View File

@ -694,4 +694,18 @@
#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
/*
* USB Otg Registers
*/
#define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x))
#define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4)
#define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8)
/* USB OTG CLK CTRL bit defines */
#define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4)
#define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3)
#define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2)
#define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1)
#define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0)
#endif

163
arch/arm/mach-lpc32xx/phy3250.c
View File

@ -30,12 +30,13 @@
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/amba/pl022.h>
#include <linux/amba/pl08x.h>
#include <linux/amba/mmci.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/clk.h>
#include <linux/amba/pl08x.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
@ -50,9 +51,9 @@
/*
* Mapped GPIOLIB GPIOs
*/
#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
#define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
/*
* AMBA LCD controller
@ -158,24 +159,6 @@ static struct clcd_board lpc32xx_clcd_data = {
/*
* AMBA SSP (SPI)
*/
static void phy3250_spi_cs_set(u32 control)
{
gpio_set_value(SPI0_CS_GPIO, (int) control);
}
static struct pl022_config_chip spi0_chip_info = {
.com_mode = INTERRUPT_TRANSFER,
.iface = SSP_INTERFACE_MOTOROLA_SPI,
.hierarchy = SSP_MASTER,
.slave_tx_disable = 0,
.rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
.tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
.ctrl_len = SSP_BITS_8,
.wait_state = SSP_MWIRE_WAIT_ZERO,
.duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
.cs_control = phy3250_spi_cs_set,
};
static struct pl022_ssp_controller lpc32xx_ssp0_data = {
.bus_id = 0,
.num_chipselect = 1,
@ -188,45 +171,56 @@ static struct pl022_ssp_controller lpc32xx_ssp1_data = {
.enable_dma = 0,
};
/* AT25 driver registration */
static int __init phy3250_spi_board_register(void)
static struct pl08x_channel_data pl08x_slave_channels[] = {
{
.bus_id = "nand-slc",
.min_signal = 1, /* SLC NAND Flash */
.max_signal = 1,
.periph_buses = PL08X_AHB1,
},
{
.bus_id = "nand-mlc",
.min_signal = 12, /* MLC NAND Flash */
.max_signal = 12,
.periph_buses = PL08X_AHB1,
},
};
static int pl08x_get_signal(const struct pl08x_channel_data *cd)
{
return cd->min_signal;
}
static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
{
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct spi_board_info info[] = {
{
.modalias = "spidev",
.max_speed_hz = 5000000,
.bus_num = 0,
.chip_select = 0,
.controller_data = &spi0_chip_info,
},
};
#else
static struct spi_eeprom eeprom = {
.name = "at25256a",
.byte_len = 0x8000,
.page_size = 64,
.flags = EE_ADDR2,
};
static struct spi_board_info info[] = {
{
.modalias = "at25",
.max_speed_hz = 5000000,
.bus_num = 0,
.chip_select = 0,
.mode = SPI_MODE_0,
.platform_data = &eeprom,
.controller_data = &spi0_chip_info,
},
};
#endif
return spi_register_board_info(info, ARRAY_SIZE(info));
}
arch_initcall(phy3250_spi_board_register);
static struct pl08x_platform_data pl08x_pd = {
.slave_channels = &pl08x_slave_channels[0],
.num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
.get_signal = pl08x_get_signal,
.put_signal = pl08x_put_signal,
.lli_buses = PL08X_AHB1,
.mem_buses = PL08X_AHB1,
};
static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios)
{
/* Only on and off are supported */
if (ios->power_mode == MMC_POWER_OFF)
gpio_set_value(MMC_PWR_ENABLE_GPIO, 0);
else
gpio_set_value(MMC_PWR_ENABLE_GPIO, 1);
return 0;
}
static struct mmci_platform_data lpc32xx_mmci_data = {
.ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 |
MMC_VDD_32_33 | MMC_VDD_33_34,
.ios_handler = mmc_handle_ios,
.dma_filter = NULL,
/* No DMA for now since AMBA PL080 dmaengine driver only does scatter
* gather, and the MMCI driver doesn't do it this way */
};
static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
@ -234,6 +228,8 @@ static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
&lpc32xx_mmci_data),
{ }
};
@ -241,10 +237,6 @@ static void __init lpc3250_machine_init(void)
{
u32 tmp;
/* Setup SLC NAND controller muxing */
__raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
LPC32XX_CLKPWR_NAND_CLK_CTRL);
/* Setup LCD muxing to RGB565 */
tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
@ -252,47 +244,8 @@ static void __init lpc3250_machine_init(void)
tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
__raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
/* Set up USB power */
tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN |
LPC32XX_CLKPWR_USBCTRL_USBI2C_EN;
__raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL);
/* Set up I2C pull levels */
tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
__raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
/* Disable IrDA pulsing support on UART6 */
tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
__raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
/* Enable DMA for I2S1 channel */
tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
__raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
lpc32xx_serial_init();
/*
* AMBA peripheral clocks need to be enabled prior to AMBA device
* detection or a data fault will occur, so enable the clocks
* here.
*/
tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
__raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
LPC32XX_CLKPWR_LCDCLK_CTRL);
tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
__raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
LPC32XX_CLKPWR_SSP_CLK_CTRL);
tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL);
__raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN),
LPC32XX_CLKPWR_DMA_CLK_CTRL);
/* Test clock needed for UDA1380 initial init */
__raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
@ -302,12 +255,10 @@ static void __init lpc3250_machine_init(void)
lpc32xx_auxdata_lookup, NULL);
/* Register GPIOs used on this board */
if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
printk(KERN_ERR "Error requesting gpio %u",
SPI0_CS_GPIO);
else if (gpio_direction_output(SPI0_CS_GPIO, 1))
printk(KERN_ERR "Error setting gpio %u to output",
SPI0_CS_GPIO);
if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO);
else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO);
}
static char const *lpc32xx_dt_compat[] __initdata = {

90
arch/arm/mach-lpc32xx/serial.c
View File

@ -31,59 +31,6 @@
#define LPC32XX_SUART_FIFO_SIZE 64
/* Standard 8250/16550 compatible serial ports */
static struct plat_serial8250_port serial_std_platform_data[] = {
#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
{
.membase = io_p2v(LPC32XX_UART5_BASE),
.mapbase = LPC32XX_UART5_BASE,
.irq = IRQ_LPC32XX_UART_IIR5,
.uartclk = LPC32XX_MAIN_OSC_FREQ,
.regshift = 2,
.iotype = UPIO_MEM32,
.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
UPF_SKIP_TEST,
},
#endif
#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
{
.membase = io_p2v(LPC32XX_UART3_BASE),
.mapbase = LPC32XX_UART3_BASE,
.irq = IRQ_LPC32XX_UART_IIR3,
.uartclk = LPC32XX_MAIN_OSC_FREQ,
.regshift = 2,
.iotype = UPIO_MEM32,
.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
UPF_SKIP_TEST,
},
#endif
#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
{
.membase = io_p2v(LPC32XX_UART4_BASE),
.mapbase = LPC32XX_UART4_BASE,
.irq = IRQ_LPC32XX_UART_IIR4,
.uartclk = LPC32XX_MAIN_OSC_FREQ,
.regshift = 2,
.iotype = UPIO_MEM32,
.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
UPF_SKIP_TEST,
},
#endif
#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
{
.membase = io_p2v(LPC32XX_UART6_BASE),
.mapbase = LPC32XX_UART6_BASE,
.irq = IRQ_LPC32XX_UART_IIR6,
.uartclk = LPC32XX_MAIN_OSC_FREQ,
.regshift = 2,
.iotype = UPIO_MEM32,
.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
UPF_SKIP_TEST,
},
#endif
{ },
};
struct uartinit {
char *uart_ck_name;
u32 ck_mode_mask;
@ -92,7 +39,6 @@ struct uartinit {
};
static struct uartinit uartinit_data[] __initdata = {
#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
{
.uart_ck_name = "uart5_ck",
.ck_mode_mask =
@ -100,8 +46,6 @@ static struct uartinit uartinit_data[] __initdata = {
.pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
.mapbase = LPC32XX_UART5_BASE,
},
#endif
#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
{
.uart_ck_name = "uart3_ck",
.ck_mode_mask =
@ -109,8 +53,6 @@ static struct uartinit uartinit_data[] __initdata = {
.pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
.mapbase = LPC32XX_UART3_BASE,
},
#endif
#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
{
.uart_ck_name = "uart4_ck",
.ck_mode_mask =
@ -118,8 +60,6 @@ static struct uartinit uartinit_data[] __initdata = {
.pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
.mapbase = LPC32XX_UART4_BASE,
},
#endif
#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
{
.uart_ck_name = "uart6_ck",
.ck_mode_mask =
@ -127,19 +67,6 @@ static struct uartinit uartinit_data[] __initdata = {
.pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
.mapbase = LPC32XX_UART6_BASE,
},
#endif
};
static struct platform_device serial_std_platform_device = {
.name = "serial8250",
.id = 0,
.dev = {
.platform_data = serial_std_platform_data,
},
};
static struct platform_device *lpc32xx_serial_devs[] __initdata = {
&serial_std_platform_device,
};
void __init lpc32xx_serial_init(void)
@ -156,15 +83,8 @@ void __init lpc32xx_serial_init(void)
clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
if (!IS_ERR(clk)) {
clk_enable(clk);
serial_std_platform_data[i].uartclk =
clk_get_rate(clk);
}
/* Fall back on main osc rate if clock rate return fails */
if (serial_std_platform_data[i].uartclk == 0)
serial_std_platform_data[i].uartclk =
LPC32XX_MAIN_OSC_FREQ;
/* Setup UART clock modes for all UARTs, disable autoclock */
clkmodes |= uartinit_data[i].ck_mode_mask;
@ -189,7 +109,7 @@ void __init lpc32xx_serial_init(void)
__raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
/* Force a flush of the RX FIFOs to work around a HW bug */
puart = serial_std_platform_data[i].mapbase;
puart = uartinit_data[i].mapbase;
__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
__raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
j = LPC32XX_SUART_FIFO_SIZE;
@ -198,11 +118,13 @@ void __init lpc32xx_serial_init(void)
__raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
}
/* Disable IrDA pulsing support on UART6 */
tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
__raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
/* Disable UART5->USB transparent mode or USB won't work */
tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
__raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
platform_add_devices(lpc32xx_serial_devs,
ARRAY_SIZE(lpc32xx_serial_devs));
}

2
arch/arm/mach-nomadik/Makefile
View File

@ -7,8 +7,6 @@
# Object file lists.
obj-y += clock.o
# Cpu revision
obj-$(CONFIG_NOMADIK_8815) += cpu-8815.o

69
arch/arm/mach-nomadik/board-nhk8815.c
View File

@ -14,12 +14,14 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/amba/bus.h>
#include <linux/amba/mmci.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/onenand.h>
#include <linux/mtd/partitions.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <asm/hardware/vic.h>
#include <asm/sizes.h>
@ -185,17 +187,29 @@ static void __init nhk8815_onenand_init(void)
#endif
}
static AMBA_APB_DEVICE(uart0, "uart0", 0, NOMADIK_UART0_BASE,
{ IRQ_UART0 }, NULL);
static AMBA_APB_DEVICE(uart1, "uart1", 0, NOMADIK_UART1_BASE,
{ IRQ_UART1 }, NULL);
static struct amba_device *amba_devs[] __initdata = {
&uart0_device,
&uart1_device,
static struct mmci_platform_data mmcsd_plat_data = {
.ocr_mask = MMC_VDD_29_30,
.f_max = 48000000,
.gpio_wp = -1,
.gpio_cd = 111,
.cd_invert = true,
.capabilities = MMC_CAP_MMC_HIGHSPEED |
MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA,
};
static int __init nhk8815_mmcsd_init(void)
{
int ret;
ret = gpio_request(112, "card detect bias");
if (ret)
return ret;
gpio_direction_output(112, 0);
amba_apb_device_add(NULL, "mmci", NOMADIK_SDI_BASE, SZ_4K, IRQ_SDMMC, 0, &mmcsd_plat_data, 0x10180180);
return 0;
}
module_init(nhk8815_mmcsd_init);
static struct resource nhk8815_eth_resources[] = {
{
.name = "smc91x-regs",
@ -253,17 +267,46 @@ static struct sys_timer nomadik_timer = {
.init = nomadik_timer_init,
};
static struct i2c_board_info __initdata nhk8815_i2c0_devices[] = {
{
I2C_BOARD_INFO("stw4811", 0x2d),
},
};
static struct i2c_board_info __initdata nhk8815_i2c1_devices[] = {
{
I2C_BOARD_INFO("camera", 0x10),
},
{
I2C_BOARD_INFO("stw5095", 0x1a),
},
{
I2C_BOARD_INFO("lis3lv02dl", 0x1d),
},
};
static struct i2c_board_info __initdata nhk8815_i2c2_devices[] = {
{
I2C_BOARD_INFO("stw4811-usb", 0x2d),
},
};
static void __init nhk8815_platform_init(void)
{
int i;
cpu8815_platform_init();
nhk8815_onenand_init();
platform_add_devices(nhk8815_platform_devices,
ARRAY_SIZE(nhk8815_platform_devices));
for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
amba_device_register(amba_devs[i], &iomem_resource);
amba_apb_device_add(NULL, "uart0", NOMADIK_UART0_BASE, SZ_4K, IRQ_UART0, 0, NULL, 0);
amba_apb_device_add(NULL, "uart1", NOMADIK_UART1_BASE, SZ_4K, IRQ_UART1, 0, NULL, 0);
i2c_register_board_info(0, nhk8815_i2c0_devices,
ARRAY_SIZE(nhk8815_i2c0_devices));
i2c_register_board_info(1, nhk8815_i2c1_devices,
ARRAY_SIZE(nhk8815_i2c1_devices));
i2c_register_board_info(2, nhk8815_i2c2_devices,
ARRAY_SIZE(nhk8815_i2c2_devices));
}
MACHINE_START(NOMADIK, "NHK8815")

75
arch/arm/mach-nomadik/clock.c
View File

@ -1,75 +0,0 @@
/*
* linux/arch/arm/mach-nomadik/clock.c
*
* Copyright (C) 2009 Alessandro Rubini
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include "clock.h"
/*
* The nomadik board uses generic clocks, but the serial pl011 file
* calls clk_enable(), clk_disable(), clk_get_rate(), so we provide them
*/
unsigned long clk_get_rate(struct clk *clk)
{
return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);
/* enable and disable do nothing */
int clk_enable(struct clk *clk)
{
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);
static struct clk clk_24 = {
.rate = 2400000,
};
static struct clk clk_48 = {
.rate = 48 * 1000 * 1000,
};
/*
* Catch-all default clock to satisfy drivers using the clk API. We don't
* model the actual hardware clocks yet.
*/
static struct clk clk_default;
#define CLK(_clk, dev) \
{ \
.clk = _clk, \
.dev_id = dev, \
}
static struct clk_lookup lookups[] = {
{
.con_id = "apb_pclk",
.clk = &clk_default,
},
CLK(&clk_24, "mtu0"),
CLK(&clk_24, "mtu1"),
CLK(&clk_48, "uart0"),
CLK(&clk_48, "uart1"),
CLK(&clk_default, "gpio.0"),
CLK(&clk_default, "gpio.1"),
CLK(&clk_default, "gpio.2"),
CLK(&clk_default, "gpio.3"),
CLK(&clk_default, "rng"),
};
int __init clk_init(void)
{
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
return 0;
}

15
arch/arm/mach-nomadik/clock.h
View File

@ -1,15 +0,0 @@
/*
* linux/arch/arm/mach-nomadik/clock.h
*
* Copyright (C) 2009 Alessandro Rubini
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
struct clk {
unsigned long rate;
};
int __init clk_init(void);

130
arch/arm/mach-nomadik/cpu-8815.c
View File

@ -22,6 +22,10 @@
#include <linux/amba/bus.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/dma-mapping.h>
#include <linux/platform_data/clk-nomadik.h>
#include <plat/gpio-nomadik.h>
#include <mach/hardware.h>
@ -32,91 +36,63 @@
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include "clock.h"
#include "cpu-8815.h"
#define __MEM_4K_RESOURCE(x) \
.res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
/* The 8815 has 4 GPIO blocks, let's register them immediately */
static resource_size_t __initdata cpu8815_gpio_base[] = {
NOMADIK_GPIO0_BASE,
NOMADIK_GPIO1_BASE,
NOMADIK_GPIO2_BASE,
NOMADIK_GPIO3_BASE,
};
#define GPIO_RESOURCE(block) \
{ \
.start = NOMADIK_GPIO##block##_BASE, \
.end = NOMADIK_GPIO##block##_BASE + SZ_4K - 1, \
.flags = IORESOURCE_MEM, \
}, \
{ \
.start = IRQ_GPIO##block, \
.end = IRQ_GPIO##block, \
.flags = IORESOURCE_IRQ, \
static struct platform_device *
cpu8815_add_gpio(int id, resource_size_t addr, int irq,
struct nmk_gpio_platform_data *pdata)
{
struct resource resources[] = {
{
.start = addr,
.end = addr + 127,
.flags = IORESOURCE_MEM,
},
{
.start = irq,
.end = irq,
.flags = IORESOURCE_IRQ,
}
};
return platform_device_register_resndata(NULL, "gpio", id,
resources, ARRAY_SIZE(resources),
pdata, sizeof(*pdata));
}
void cpu8815_add_gpios(resource_size_t *base, int num, int irq,
struct nmk_gpio_platform_data *pdata)
{
int first = 0;
int i;
for (i = 0; i < num; i++, first += 32, irq++) {
pdata->first_gpio = first;
pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first);
pdata->num_gpio = 32;
cpu8815_add_gpio(i, base[i], irq, pdata);
}
#define GPIO_DEVICE(block) \
{ \
.name = "gpio", \
.id = block, \
.num_resources = 2, \
.resource = &cpu8815_gpio_resources[block * 2], \
.dev = { \
.platform_data = &cpu8815_gpio[block], \
}, \
}
static struct nmk_gpio_platform_data cpu8815_gpio[] = {
{
.name = "GPIO-0-31",
.first_gpio = 0,
.first_irq = NOMADIK_GPIO_TO_IRQ(0),
}, {
.name = "GPIO-32-63",
.first_gpio = 32,
.first_irq = NOMADIK_GPIO_TO_IRQ(32),
}, {
.name = "GPIO-64-95",
.first_gpio = 64,
.first_irq = NOMADIK_GPIO_TO_IRQ(64),
}, {
.name = "GPIO-96-127", /* 124..127 not routed to pin */
.first_gpio = 96,
.first_irq = NOMADIK_GPIO_TO_IRQ(96),
}
};
static struct resource cpu8815_gpio_resources[] = {
GPIO_RESOURCE(0),
GPIO_RESOURCE(1),
GPIO_RESOURCE(2),
GPIO_RESOURCE(3),
};
static struct platform_device cpu8815_platform_gpio[] = {
GPIO_DEVICE(0),
GPIO_DEVICE(1),
GPIO_DEVICE(2),
GPIO_DEVICE(3),
};
static AMBA_APB_DEVICE(cpu8815_amba_rng, "rng", 0, NOMADIK_RNG_BASE, { }, NULL);
static struct platform_device *platform_devs[] __initdata = {
cpu8815_platform_gpio + 0,
cpu8815_platform_gpio + 1,
cpu8815_platform_gpio + 2,
cpu8815_platform_gpio + 3,
};
static struct amba_device *amba_devs[] __initdata = {
&cpu8815_amba_rng_device
};
}
static int __init cpu8815_init(void)
{
int i;
struct nmk_gpio_platform_data pdata = {
/* No custom data yet */
};
platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
amba_device_register(amba_devs[i], &iomem_resource);
cpu8815_add_gpios(cpu8815_gpio_base, ARRAY_SIZE(cpu8815_gpio_base),
IRQ_GPIO0, &pdata);
amba_apb_device_add(NULL, "rng", NOMADIK_RNG_BASE, SZ_4K, 0, 0, NULL, 0);
amba_apb_device_add(NULL, "rtc-pl031", NOMADIK_RTC_BASE, SZ_4K, IRQ_RTC_RTT, 0, NULL, 0);
return 0;
}
arch_initcall(cpu8815_init);
@ -147,7 +123,7 @@ void __init cpu8815_init_irq(void)
* Init clocks here so that they are available for system timer
* initialization.
*/
clk_init();
nomadik_clk_init();
}
/*

38
arch/arm/mach-nomadik/i2c-8815nhk.c
View File

@ -5,6 +5,7 @@
#include <linux/i2c-gpio.h>
#include <linux/platform_device.h>
#include <plat/gpio-nomadik.h>
#include <plat/pincfg.h>
/*
* There are two busses in the 8815NHK.
@ -12,19 +13,27 @@
* use bit-bang through GPIO by now, to keep things simple
*/
/* I2C0 connected to the STw4811 power management chip */
static struct i2c_gpio_platform_data nhk8815_i2c_data0 = {
/* keep defaults for timeouts; pins are push-pull bidirectional */
.scl_pin = 62,
.sda_pin = 63,
};
/* I2C1 connected to various sensors */
static struct i2c_gpio_platform_data nhk8815_i2c_data1 = {
/* keep defaults for timeouts; pins are push-pull bidirectional */
.scl_pin = 53,
.sda_pin = 54,
};
/* first bus: GPIO XX and YY */
/* I2C2 connected to the USB portions of the STw4811 only */
static struct i2c_gpio_platform_data nhk8815_i2c_data2 = {
/* keep defaults for timeouts; pins are push-pull bidirectional */
.scl_pin = 73,
.sda_pin = 74,
};
static struct platform_device nhk8815_i2c_dev0 = {
.name = "i2c-gpio",
.id = 0,
@ -32,7 +41,7 @@ static struct platform_device nhk8815_i2c_dev0 = {
.platform_data = &nhk8815_i2c_data0,
},
};
/* second bus: GPIO XX and YY */
static struct platform_device nhk8815_i2c_dev1 = {
.name = "i2c-gpio",
.id = 1,
@ -41,15 +50,29 @@ static struct platform_device nhk8815_i2c_dev1 = {
},
};
static struct platform_device nhk8815_i2c_dev2 = {
.name = "i2c-gpio",
.id = 2,
.dev = {
.platform_data = &nhk8815_i2c_data2,
},
};
static pin_cfg_t cpu8815_pins_i2c[] = {
PIN_CFG_INPUT(62, GPIO, PULLUP),
PIN_CFG_INPUT(63, GPIO, PULLUP),
PIN_CFG_INPUT(53, GPIO, PULLUP),
PIN_CFG_INPUT(54, GPIO, PULLUP),
PIN_CFG_INPUT(73, GPIO, PULLUP),
PIN_CFG_INPUT(74, GPIO, PULLUP),
};
static int __init nhk8815_i2c_init(void)
{
nmk_gpio_set_mode(nhk8815_i2c_data0.scl_pin, NMK_GPIO_ALT_GPIO);
nmk_gpio_set_mode(nhk8815_i2c_data0.sda_pin, NMK_GPIO_ALT_GPIO);
nmk_config_pins(cpu8815_pins_i2c, ARRAY_SIZE(cpu8815_pins_i2c));
platform_device_register(&nhk8815_i2c_dev0);
nmk_gpio_set_mode(nhk8815_i2c_data1.scl_pin, NMK_GPIO_ALT_GPIO);
nmk_gpio_set_mode(nhk8815_i2c_data1.sda_pin, NMK_GPIO_ALT_GPIO);
platform_device_register(&nhk8815_i2c_dev1);
platform_device_register(&nhk8815_i2c_dev2);
return 0;
}
@ -58,6 +81,7 @@ static void __exit nhk8815_i2c_exit(void)
{
platform_device_unregister(&nhk8815_i2c_dev0);
platform_device_unregister(&nhk8815_i2c_dev1);
platform_device_unregister(&nhk8815_i2c_dev2);
return;
}

85
arch/arm/mach-nomadik/include/mach/irqs.h
View File

@ -22,56 +22,56 @@
#include <mach/hardware.h>
#define IRQ_VIC_START 0 /* first VIC interrupt is 0 */
#define IRQ_VIC_START 1 /* first VIC interrupt is 1 */
/*
* Interrupt numbers generic for all Nomadik Chip cuts
*/
#define IRQ_WATCHDOG 0
#define IRQ_SOFTINT 1
#define IRQ_CRYPTO 2
#define IRQ_OWM 3
#define IRQ_MTU0 4
#define IRQ_MTU1 5
#define IRQ_GPIO0 6
#define IRQ_GPIO1 7
#define IRQ_GPIO2 8
#define IRQ_GPIO3 9
#define IRQ_RTC_RTT 10
#define IRQ_SSP 11
#define IRQ_UART0 12
#define IRQ_DMA1 13
#define IRQ_CLCD_MDIF 14
#define IRQ_DMA0 15
#define IRQ_PWRFAIL 16
#define IRQ_UART1 17
#define IRQ_FIRDA 18
#define IRQ_MSP0 19
#define IRQ_I2C0 20
#define IRQ_I2C1 21
#define IRQ_SDMMC 22
#define IRQ_USBOTG 23
#define IRQ_SVA_IT0 24
#define IRQ_SVA_IT1 25
#define IRQ_SAA_IT0 26
#define IRQ_SAA_IT1 27
#define IRQ_UART2 28
#define IRQ_MSP2 31
#define IRQ_L2CC 48
#define IRQ_HPI 49
#define IRQ_SKE 50
#define IRQ_KP 51
#define IRQ_MEMST 54
#define IRQ_SGA_IT 58
#define IRQ_USBM 60
#define IRQ_MSP1 62
#define IRQ_WATCHDOG 1
#define IRQ_SOFTINT 2
#define IRQ_CRYPTO 3
#define IRQ_OWM 4
#define IRQ_MTU0 5
#define IRQ_MTU1 6
#define IRQ_GPIO0 7
#define IRQ_GPIO1 8
#define IRQ_GPIO2 9
#define IRQ_GPIO3 10
#define IRQ_RTC_RTT 11
#define IRQ_SSP 12
#define IRQ_UART0 13
#define IRQ_DMA1 14
#define IRQ_CLCD_MDIF 15
#define IRQ_DMA0 16
#define IRQ_PWRFAIL 17
#define IRQ_UART1 18
#define IRQ_FIRDA 19
#define IRQ_MSP0 20
#define IRQ_I2C0 21
#define IRQ_I2C1 22
#define IRQ_SDMMC 23
#define IRQ_USBOTG 24
#define IRQ_SVA_IT0 25
#define IRQ_SVA_IT1 26
#define IRQ_SAA_IT0 27
#define IRQ_SAA_IT1 28
#define IRQ_UART2 29
#define IRQ_MSP2 30
#define IRQ_L2CC 49
#define IRQ_HPI 50
#define IRQ_SKE 51
#define IRQ_KP 52
#define IRQ_MEMST 55
#define IRQ_SGA_IT 59
#define IRQ_USBM 61
#define IRQ_MSP1 63
#define NOMADIK_SOC_NR_IRQS 64
#define NOMADIK_GPIO_OFFSET (IRQ_VIC_START+64)
/* After chip-specific IRQ numbers we have the GPIO ones */
#define NOMADIK_NR_GPIO 128 /* last 4 not wired to pins */
#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + NOMADIK_SOC_NR_IRQS)
#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - NOMADIK_SOC_NR_IRQS)
#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + NOMADIK_GPIO_OFFSET)
#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - NOMADIK_GPIO_OFFSET)
#define NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
/* Following two are used by entry_macro.S, to access our dual-vic */
@ -79,4 +79,3 @@
#define VIC_REG_IRQSR1 0x20
#endif /* __ASM_ARCH_IRQS_H */

6
arch/arm/mach-omap2/Makefile
View File

@ -93,6 +93,7 @@ obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o
obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o
obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o
obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o
# OMAP voltage domains
voltagedomain-common := voltage.o vc.o vp.o
@ -102,6 +103,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
# OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o
@ -116,6 +118,8 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o
obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
# PRCM clockdomain control
clockdomain-common += clockdomain.o
@ -131,6 +135,8 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o
obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o

18
arch/arm/mach-omap2/board-generic.c
View File

@ -112,6 +112,24 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
MACHINE_END
#endif
#ifdef CONFIG_SOC_AM33XX
static const char *am33xx_boards_compat[] __initdata = {
"ti,am33xx",
NULL,
};
DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = am33xx_map_io,
.init_early = am33xx_init_early,
.init_irq = omap_init_irq,
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_generic_init,
.timer = &omap3_am33xx_timer,
.dt_compat = am33xx_boards_compat,
MACHINE_END
#endif
#ifdef CONFIG_ARCH_OMAP4
static const char *omap4_boards_compat[] __initdata = {
"ti,omap4",

2
arch/arm/mach-omap2/clockdomain.h
View File

@ -199,6 +199,7 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
extern void __init omap242x_clockdomains_init(void);
extern void __init omap243x_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
@ -206,6 +207,7 @@ extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
extern struct clkdm_ops omap2_clkdm_operations;
extern struct clkdm_ops omap3_clkdm_operations;
extern struct clkdm_ops omap4_clkdm_operations;
extern struct clkdm_ops am33xx_clkdm_operations;
extern struct clkdm_dep gfx_24xx_wkdeps[];
extern struct clkdm_dep dsp_24xx_wkdeps[];

74
arch/arm/mach-omap2/clockdomain33xx.c Normal file
View File

@ -0,0 +1,74 @@
/*
* AM33XX clockdomain control
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* Derived from mach-omap2/clockdomain44xx.c written by Rajendra Nayak
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include "clockdomain.h"
#include "cm33xx.h"
static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
{
am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
return 0;
}
static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
{
am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
return 0;
}
static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
{
am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
}
static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
{
am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
}
static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
{
if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
return am33xx_clkdm_wakeup(clkdm);
return 0;
}
static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
{
bool hwsup = false;
hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
am33xx_clkdm_sleep(clkdm);
return 0;
}
struct clkdm_ops am33xx_clkdm_operations = {
.clkdm_sleep = am33xx_clkdm_sleep,
.clkdm_wakeup = am33xx_clkdm_wakeup,
.clkdm_allow_idle = am33xx_clkdm_allow_idle,
.clkdm_deny_idle = am33xx_clkdm_deny_idle,
.clkdm_clk_enable = am33xx_clkdm_clk_enable,
.clkdm_clk_disable = am33xx_clkdm_clk_disable,
};

196
arch/arm/mach-omap2/clockdomains33xx_data.c Normal file
View File

@ -0,0 +1,196 @@
/*
* AM33XX Clock Domain data.
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include "clockdomain.h"
#include "cm.h"
#include "cm33xx.h"
#include "cm-regbits-33xx.h"
static struct clockdomain l4ls_am33xx_clkdm = {
.name = "l4ls_clkdm",
.pwrdm = { .name = "per_pwrdm" },
.cm_inst = AM33XX_CM_PER_MOD,
.clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l3s_am33xx_clkdm = {
.name = "l3s_clkdm",
.pwrdm = { .name = "per_pwrdm" },
.cm_inst = AM33XX_CM_PER_MOD,
.clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l4fw_am33xx_clkdm = {
.name = "l4fw_clkdm",
.pwrdm = { .name = "per_pwrdm" },
.cm_inst = AM33XX_CM_PER_MOD,
.clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l3_am33xx_clkdm = {
.name = "l3_clkdm",
.pwrdm = { .name = "per_pwrdm" },
.cm_inst = AM33XX_CM_PER_MOD,
.clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l4hs_am33xx_clkdm = {
.name = "l4hs_clkdm",
.pwrdm = { .name = "per_pwrdm" },
.cm_inst = AM33XX_CM_PER_MOD,
.clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain ocpwp_l3_am33xx_clkdm = {
.name = "ocpwp_l3_clkdm",
.pwrdm = { .name = "per_pwrdm" },
.cm_inst = AM33XX_CM_PER_MOD,
.clkdm_offs = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain pruss_ocp_am33xx_clkdm = {
.name = "pruss_ocp_clkdm",
.pwrdm = { .name = "per_pwrdm" },
.cm_inst = AM33XX_CM_PER_MOD,
.clkdm_offs = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain cpsw_125mhz_am33xx_clkdm = {
.name = "cpsw_125mhz_clkdm",
.pwrdm = { .name = "per_pwrdm" },
.cm_inst = AM33XX_CM_PER_MOD,
.clkdm_offs = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain lcdc_am33xx_clkdm = {
.name = "lcdc_clkdm",
.pwrdm = { .name = "per_pwrdm" },
.cm_inst = AM33XX_CM_PER_MOD,
.clkdm_offs = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain clk_24mhz_am33xx_clkdm = {
.name = "clk_24mhz_clkdm",
.pwrdm = { .name = "per_pwrdm" },
.cm_inst = AM33XX_CM_PER_MOD,
.clkdm_offs = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l4_wkup_am33xx_clkdm = {
.name = "l4_wkup_clkdm",
.pwrdm = { .name = "wkup_pwrdm" },
.cm_inst = AM33XX_CM_WKUP_MOD,
.clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l3_aon_am33xx_clkdm = {
.name = "l3_aon_clkdm",
.pwrdm = { .name = "wkup_pwrdm" },
.cm_inst = AM33XX_CM_WKUP_MOD,
.clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l4_wkup_aon_am33xx_clkdm = {
.name = "l4_wkup_aon_clkdm",
.pwrdm = { .name = "wkup_pwrdm" },
.cm_inst = AM33XX_CM_WKUP_MOD,
.clkdm_offs = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain mpu_am33xx_clkdm = {
.name = "mpu_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.cm_inst = AM33XX_CM_MPU_MOD,
.clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l4_rtc_am33xx_clkdm = {
.name = "l4_rtc_clkdm",
.pwrdm = { .name = "rtc_pwrdm" },
.cm_inst = AM33XX_CM_RTC_MOD,
.clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain gfx_l3_am33xx_clkdm = {
.name = "gfx_l3_clkdm",
.pwrdm = { .name = "gfx_pwrdm" },
.cm_inst = AM33XX_CM_GFX_MOD,
.clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = {
.name = "gfx_l4ls_gfx_clkdm",
.pwrdm = { .name = "gfx_pwrdm" },
.cm_inst = AM33XX_CM_GFX_MOD,
.clkdm_offs = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain l4_cefuse_am33xx_clkdm = {
.name = "l4_cefuse_clkdm",
.pwrdm = { .name = "cefuse_pwrdm" },
.cm_inst = AM33XX_CM_CEFUSE_MOD,
.clkdm_offs = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain *clockdomains_am33xx[] __initdata = {
&l4ls_am33xx_clkdm,
&l3s_am33xx_clkdm,
&l4fw_am33xx_clkdm,
&l3_am33xx_clkdm,
&l4hs_am33xx_clkdm,
&ocpwp_l3_am33xx_clkdm,
&pruss_ocp_am33xx_clkdm,
&cpsw_125mhz_am33xx_clkdm,
&lcdc_am33xx_clkdm,
&clk_24mhz_am33xx_clkdm,
&l4_wkup_am33xx_clkdm,
&l3_aon_am33xx_clkdm,
&l4_wkup_aon_am33xx_clkdm,
&mpu_am33xx_clkdm,
&l4_rtc_am33xx_clkdm,
&gfx_l3_am33xx_clkdm,
&gfx_l4ls_gfx_am33xx_clkdm,
&l4_cefuse_am33xx_clkdm,
NULL,
};
void __init am33xx_clockdomains_init(void)
{
clkdm_register_platform_funcs(&am33xx_clkdm_operations);
clkdm_register_clkdms(clockdomains_am33xx);
clkdm_complete_init();
}

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arch/arm/mach-omap2/cm-regbits-33xx.h Normal file
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/*
* AM33XX Power Management register bits
*
* This file is automatically generated from the AM33XX hardware databases.
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
/*
* Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
* CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
*/
#define AM33XX_AUTO_DPLL_MODE_SHIFT 0
#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14
#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11
#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)
/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)
/* Used by CM_PER_CPSW_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)
/* Used by CM_CEFUSE_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
/* Used by CM_L3_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)
/* Used by CM_L3_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)
/* Used by CM_GFX_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9
#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)
/* Used by CM_GFX_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24
#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)
/* Used by CM_PER_PRUSS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5)
/* Used by CM_PER_PRUSS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4)
/* Used by CM_PER_PRUSS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6)
/* Used by CM_PER_L3S_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)
/* Used by CM_L3_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)
/* Used by CM_PER_L4FW_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)
/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)
/* Used by CM_CEFUSE_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
/* Used by CM_RTC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)
/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17
#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)
/* Used by CM_PER_LCDC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)
/* Used by CM_PER_LCDC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7
#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)
/* Used by CM_MPU_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2
#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)
/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)
/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)
/* Used by CM_RTC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9
#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25
#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12
#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10
#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9
#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)
/* Used by CLKSEL_GFX_FCLK */
#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0
#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)
/* Used by CM_CLKOUT_CTRL */
#define AM33XX_CLKOUT2DIV_SHIFT 3
#define AM33XX_CLKOUT2DIV_MASK (0x05 << 3)
/* Used by CM_CLKOUT_CTRL */
#define AM33XX_CLKOUT2EN_SHIFT 7
#define AM33XX_CLKOUT2EN_MASK (1 << 7)
/* Used by CM_CLKOUT_CTRL */
#define AM33XX_CLKOUT2SOURCE_SHIFT 0
#define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0)
/*
* Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
* CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
* CLKSEL_TIMER7_CLK
*/
#define AM33XX_CLKSEL_SHIFT 0
#define AM33XX_CLKSEL_MASK (0x01 << 0)
/*
* Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
* CM_CPTS_RFT_CLKSEL
*/
#define AM33XX_CLKSEL_0_0_SHIFT 0
#define AM33XX_CLKSEL_0_0_MASK (1 << 0)
#define AM33XX_CLKSEL_0_1_SHIFT 0
#define AM33XX_CLKSEL_0_1_MASK (3 << 0)
/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
#define AM33XX_CLKSEL_0_2_SHIFT 0
#define AM33XX_CLKSEL_0_2_MASK (7 << 0)
/* Used by CLKSEL_GFX_FCLK */
#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1
#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
/*
* Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
* CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
* CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
* CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
* CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
* CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
*/
#define AM33XX_CLKTRCTRL_SHIFT 0
#define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
/*
* Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
* CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
* CM_SSC_DELTAMSTEP_DPLL_PER
*/
#define AM33XX_DELTAMSTEP_SHIFT 0
#define AM33XX_DELTAMSTEP_MASK (0x19 << 0)
/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23
#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
/* Used by CM_CLKDCOLDO_DPLL_PER */
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
/* Used by CM_CLKDCOLDO_DPLL_PER */
#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12
#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0
#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0)
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5
#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)
/*
* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
* CM_DIV_M2_DPLL_PER
*/
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
/*
* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
* CM_CLKSEL_DPLL_MPU
*/
#define AM33XX_DPLL_DIV_SHIFT 0
#define AM33XX_DPLL_DIV_MASK (0x7f << 0)
#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
#define AM33XX_DPLL_DIV_0_7_SHIFT 0
#define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU
*/
#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8
#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_EN_SHIFT 0
#define AM33XX_DPLL_EN_MASK (0x7 << 0)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU
*/
#define AM33XX_DPLL_LPMODE_EN_SHIFT 10
#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)
/*
* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
* CM_CLKSEL_DPLL_MPU
*/
#define AM33XX_DPLL_MULT_SHIFT 8
#define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8
#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU
*/
#define AM33XX_DPLL_REGM4XEN_SHIFT 11
#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11)
/* Used by CM_CLKSEL_DPLL_PERIPH */
#define AM33XX_DPLL_SD_DIV_SHIFT 24
#define AM33XX_DPLL_SD_DIV_MASK (24, 31)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_SSC_ACK_SHIFT 13
#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_SSC_EN_SHIFT 12
#define AM33XX_DPLL_SSC_EN_MASK (1 << 12)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
/*
* Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
* CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
* CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
* CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
* CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
* CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
* CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
* CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
* CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
* CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
* CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
* CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
* CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
* CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
* CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
* CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
* CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
* CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
* CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
* CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
* CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
* CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
* CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
* CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
* CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
* CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
* CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
* CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
* CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
* CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
*/
#define AM33XX_IDLEST_SHIFT 16
#define AM33XX_IDLEST_MASK (0x3 << 16)
#define AM33XX_IDLEST_VAL 0x3
/* Used by CM_MAC_CLKSEL */
#define AM33XX_MII_CLK_SEL_SHIFT 2
#define AM33XX_MII_CLK_SEL_MASK (1 << 2)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
* CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
* CM_SSC_MODFREQDIV_DPLL_PER
*/
#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8
#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
* CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
* CM_SSC_MODFREQDIV_DPLL_PER
*/
#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0
#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0)
/*
* Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
* CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
* CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
* CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
* CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
* CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
* CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
* CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
* CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
* CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
* CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
* CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
* CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
* CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
* CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
* CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
* CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
* CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
* CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
* CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
* CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
* CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
* CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
* CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
* CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
* CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
* CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
* CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
* CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
* CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
* CM_CEFUSE_CEFUSE_CLKCTRL
*/
#define AM33XX_MODULEMODE_SHIFT 0
#define AM33XX_MODULEMODE_MASK (0x3 << 0)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)
/* Used by CM_WKUP_GPIO0_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO1_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO2_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO3_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO4_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO5_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO6_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)
/*
* Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
* CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
* CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
* CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
* CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
* CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
*/
#define AM33XX_STBYST_SHIFT 18
#define AM33XX_STBYST_MASK (1 << 18)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_STM_PMD_CLKSEL_SHIFT 22
#define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22)
/*
* Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
*/
#define AM33XX_ST_DPLL_CLK_SHIFT 0
#define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
/* Used by CM_CLKDCOLDO_DPLL_PER */
#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)
/*
* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
* CM_DIV_M2_DPLL_PER
*/
#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9
#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9
#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9
#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9
#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
/*
* Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
*/
#define AM33XX_ST_MN_BYPASS_SHIFT 8
#define AM33XX_ST_MN_BYPASS_MASK (1 << 8)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
#define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20)
/* Used by CONTROL_SEC_CLK_CTRL */
#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4)
#endif

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arch/arm/mach-omap2/cm33xx.c Normal file
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/*
* AM33XX CM functions
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* Reference taken from from OMAP4 cminst44xx.c
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>
#include <plat/common.h>
#include "cm.h"
#include "cm33xx.h"
#include "cm-regbits-34xx.h"
#include "cm-regbits-33xx.h"
#include "prm33xx.h"
/*
* CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
*
* 0x0 func: Module is fully functional, including OCP
* 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
* abortion
* 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
* using separate functional clock
* 0x3 disabled: Module is disabled and cannot be accessed
*
*/
#define CLKCTRL_IDLEST_FUNCTIONAL 0x0
#define CLKCTRL_IDLEST_INTRANSITION 0x1
#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
#define CLKCTRL_IDLEST_DISABLED 0x3
/* Private functions */
/* Read a register in a CM instance */
static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx)
{
return __raw_readl(cm_base + inst + idx);
}
/* Write into a register in a CM */
static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx)
{
__raw_writel(val, cm_base + inst + idx);
}
/* Read-modify-write a register in CM */
static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
{
u32 v;
v = am33xx_cm_read_reg(inst, idx);
v &= ~mask;
v |= bits;
am33xx_cm_write_reg(v, inst, idx);
return v;
}
static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx)
{
return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx);
}
static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx)
{
return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx);
}
static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
{
u32 v;
v = am33xx_cm_read_reg(inst, idx);
v &= mask;
v >>= __ffs(mask);
return v;
}
/**
* _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
*
* Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
* bit 0.
*/
static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
{
u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
v &= AM33XX_IDLEST_MASK;
v >>= AM33XX_IDLEST_SHIFT;
return v;
}
/**
* _is_module_ready - can module registers be accessed without causing an abort?
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
*
* Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
* *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
*/
static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
{
u32 v;
v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs);
return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
}
/**
* _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
* @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
*
* @c must be the unshifted value for CLKTRCTRL - i.e., this function
* will handle the shift itself.
*/
static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
{
u32 v;
v = am33xx_cm_read_reg(inst, cdoffs);
v &= ~AM33XX_CLKTRCTRL_MASK;
v |= c << AM33XX_CLKTRCTRL_SHIFT;
am33xx_cm_write_reg(v, inst, cdoffs);
}
/* Public functions */
/**
* am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
*
* Returns true if the clockdomain referred to by (@inst, @cdoffs)
* is in hardware-supervised idle mode, or 0 otherwise.
*/
bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
{
u32 v;
v = am33xx_cm_read_reg(inst, cdoffs);
v &= AM33XX_CLKTRCTRL_MASK;
v >>= AM33XX_CLKTRCTRL_SHIFT;
return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
}
/**
* am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
*
* Put a clockdomain referred to by (@inst, @cdoffs) into
* hardware-supervised idle mode. No return value.
*/
void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
{
_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
}
/**
* am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
*
* Put a clockdomain referred to by (@inst, @cdoffs) into
* software-supervised idle mode, i.e., controlled manually by the
* Linux OMAP clockdomain code. No return value.
*/
void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
{
_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
}
/**
* am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
*
* Put a clockdomain referred to by (@inst, @cdoffs) into idle
* No return value.
*/
void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
{
_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
}
/**
* am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
*
* Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
* waking it up. No return value.
*/
void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs)
{
_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
}
/*
*
*/
/**
* am33xx_cm_wait_module_ready - wait for a module to be in 'func' state
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
*
* Wait for the module IDLEST to be functional. If the idle state is in any
* the non functional state (trans, idle or disabled), module and thus the
* sysconfig cannot be accessed and will probably lead to an "imprecise
* external abort"
*/
int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
{
int i = 0;
if (!clkctrl_offs)
return 0;
omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
MAX_MODULE_READY_TIME, i);
return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
}
/**
* am33xx_cm_wait_module_idle - wait for a module to be in 'disabled'
* state
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
*
* Wait for the module IDLEST to be disabled. Some PRCM transition,
* like reset assertion or parent clock de-activation must wait the
* module to be fully disabled.
*/
int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
{
int i = 0;
if (!clkctrl_offs)
return 0;
omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) ==
CLKCTRL_IDLEST_DISABLED),
MAX_MODULE_READY_TIME, i);
return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
}
/**
* am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL
* @mode: Module mode (SW or HW)
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
*
* No return value.
*/
void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs)
{
u32 v;
v = am33xx_cm_read_reg(inst, clkctrl_offs);
v &= ~AM33XX_MODULEMODE_MASK;
v |= mode << AM33XX_MODULEMODE_SHIFT;
am33xx_cm_write_reg(v, inst, clkctrl_offs);
}
/**
* am33xx_cm_module_disable - Disable the module inside CLKCTRL
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
*
* No return value.
*/
void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs)
{
u32 v;
v = am33xx_cm_read_reg(inst, clkctrl_offs);
v &= ~AM33XX_MODULEMODE_MASK;
am33xx_cm_write_reg(v, inst, clkctrl_offs);
}

420
arch/arm/mach-omap2/cm33xx.h Normal file
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@ -0,0 +1,420 @@
/*
* AM33XX CM offset macros
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>
#include "common.h"
#include "cm.h"
#include "cm-regbits-33xx.h"
#include "cm33xx.h"
/* CM base address */
#define AM33XX_CM_BASE 0x44e00000
#define AM33XX_CM_REGADDR(inst, reg) \
AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
/* CM instances */
#define AM33XX_CM_PER_MOD 0x0000
#define AM33XX_CM_WKUP_MOD 0x0400
#define AM33XX_CM_DPLL_MOD 0x0500
#define AM33XX_CM_MPU_MOD 0x0600
#define AM33XX_CM_DEVICE_MOD 0x0700
#define AM33XX_CM_RTC_MOD 0x0800
#define AM33XX_CM_GFX_MOD 0x0900
#define AM33XX_CM_CEFUSE_MOD 0x0A00
/* CM */
/* CM.PER_CM register offsets */
#define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
#define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
#define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004
#define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
#define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET 0x0008
#define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
#define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c
#define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
#define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014
#define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014)
#define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018
#define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018)
#define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET 0x001c
#define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c)
#define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET 0x0020
#define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020)
#define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024
#define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024)
#define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028
#define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
#define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c
#define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c)
#define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030
#define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030)
#define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034
#define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034)
#define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET 0x0038
#define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038)
#define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c
#define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c)
#define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0040
#define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040)
#define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044
#define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044)
#define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048
#define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048)
#define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c
#define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c)
#define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050
#define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050)
#define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0054
#define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054)
#define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0058
#define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058)
#define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060
#define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060)
#define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET 0x0064
#define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064)
#define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068
#define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068)
#define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET 0x006c
#define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c)
#define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0070
#define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070)
#define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0074
#define AM33XX_CM_PER_UART3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074)
#define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0078
#define AM33XX_CM_PER_UART4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078)
#define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x007c
#define AM33XX_CM_PER_TIMER7_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c)
#define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0080
#define AM33XX_CM_PER_TIMER2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080)
#define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0084
#define AM33XX_CM_PER_TIMER3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084)
#define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0088
#define AM33XX_CM_PER_TIMER4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088)
#define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET 0x008c
#define AM33XX_CM_PER_MCASP2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c)
#define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET 0x0090
#define AM33XX_CM_PER_RNG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090)
#define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0094
#define AM33XX_CM_PER_AES0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094)
#define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET 0x0098
#define AM33XX_CM_PER_AES1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098)
#define AM33XX_CM_PER_DES_CLKCTRL_OFFSET 0x009c
#define AM33XX_CM_PER_DES_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c)
#define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x00a0
#define AM33XX_CM_PER_SHA0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0)
#define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET 0x00a4
#define AM33XX_CM_PER_PKA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4)
#define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET 0x00a8
#define AM33XX_CM_PER_GPIO6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8)
#define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x00ac
#define AM33XX_CM_PER_GPIO1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac)
#define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x00b0
#define AM33XX_CM_PER_GPIO2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0)
#define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x00b4
#define AM33XX_CM_PER_GPIO3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4)
#define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x00b8
#define AM33XX_CM_PER_GPIO4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8)
#define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x00bc
#define AM33XX_CM_PER_TPCC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc)
#define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x00c0
#define AM33XX_CM_PER_DCAN0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0)
#define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x00c4
#define AM33XX_CM_PER_DCAN1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4)
#define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x00cc
#define AM33XX_CM_PER_EPWMSS1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc)
#define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET 0x00d0
#define AM33XX_CM_PER_EMIF_FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0)
#define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x00d4
#define AM33XX_CM_PER_EPWMSS0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4)
#define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x00d8
#define AM33XX_CM_PER_EPWMSS2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8)
#define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x00dc
#define AM33XX_CM_PER_L3_INSTR_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc)
#define AM33XX_CM_PER_L3_CLKCTRL_OFFSET 0x00e0
#define AM33XX_CM_PER_L3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0)
#define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET 0x00e4
#define AM33XX_CM_PER_IEEE5000_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4)
#define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x00e8
#define AM33XX_CM_PER_PRUSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8)
#define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x00ec
#define AM33XX_CM_PER_TIMER5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec)
#define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x00f0
#define AM33XX_CM_PER_TIMER6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0)
#define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x00f4
#define AM33XX_CM_PER_MMC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4)
#define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x00f8
#define AM33XX_CM_PER_MMC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8)
#define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x00fc
#define AM33XX_CM_PER_TPTC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc)
#define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0100
#define AM33XX_CM_PER_TPTC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100)
#define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0104
#define AM33XX_CM_PER_GPIO5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104)
#define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x010c
#define AM33XX_CM_PER_SPINLOCK_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c)
#define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x0110
#define AM33XX_CM_PER_MAILBOX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110)
#define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c
#define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
#define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x0120
#define AM33XX_CM_PER_L4HS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120)
#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET 0x0124
#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124)
#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET 0x0128
#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128)
#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c
#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
#define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET 0x0130
#define AM33XX_CM_PER_OCPWP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130)
#define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET 0x0134
#define AM33XX_CM_PER_MAILBOX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134)
#define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140
#define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
#define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144
#define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
#define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148
#define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET 0x014c
#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c)
#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150
#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
/* CM.WKUP_CM register offsets */
#define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000
#define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
#define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0004
#define AM33XX_CM_WKUP_CONTROL_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004)
#define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0008
#define AM33XX_CM_WKUP_GPIO0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008)
#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x000c
#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c)
#define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET 0x0010
#define AM33XX_CM_WKUP_TIMER0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010)
#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET 0x0014
#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014)
#define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018
#define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
#define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x001c
#define AM33XX_CM_AUTOIDLE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c)
#define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0020
#define AM33XX_CM_IDLEST_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020)
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0024
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024)
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x0028
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028)
#define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x002c
#define AM33XX_CM_CLKSEL_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c)
#define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0030
#define AM33XX_CM_AUTOIDLE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030)
#define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0034
#define AM33XX_CM_IDLEST_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034)
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x0038
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038)
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x003c
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c)
#define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x0040
#define AM33XX_CM_CLKSEL_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040)
#define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET 0x0044
#define AM33XX_CM_AUTOIDLE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044)
#define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET 0x0048
#define AM33XX_CM_IDLEST_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048)
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET 0x004c
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c)
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET 0x0050
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050)
#define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET 0x0054
#define AM33XX_CM_CLKSEL_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054)
#define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0058
#define AM33XX_CM_AUTOIDLE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058)
#define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET 0x005c
#define AM33XX_CM_IDLEST_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c)
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0060
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060)
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x0064
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064)
#define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x0068
#define AM33XX_CM_CLKSEL_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068)
#define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x006c
#define AM33XX_CM_AUTOIDLE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c)
#define AM33XX_CM_IDLEST_DPLL_PER_OFFSET 0x0070
#define AM33XX_CM_IDLEST_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070)
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0074
#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074)
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0078
#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078)
#define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET 0x007c
#define AM33XX_CM_CLKDCOLDO_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c)
#define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET 0x0080
#define AM33XX_CM_DIV_M4_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080)
#define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET 0x0084
#define AM33XX_CM_DIV_M5_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084)
#define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0088
#define AM33XX_CM_CLKMODE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088)
#define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET 0x008c
#define AM33XX_CM_CLKMODE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c)
#define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0090
#define AM33XX_CM_CLKMODE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090)
#define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0094
#define AM33XX_CM_CLKMODE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094)
#define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET 0x0098
#define AM33XX_CM_CLKMODE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098)
#define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET 0x009c
#define AM33XX_CM_CLKSEL_DPLL_PERIPH AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c)
#define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x00a0
#define AM33XX_CM_DIV_M2_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0)
#define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET 0x00a4
#define AM33XX_CM_DIV_M2_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4)
#define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x00a8
#define AM33XX_CM_DIV_M2_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8)
#define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET 0x00ac
#define AM33XX_CM_DIV_M2_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac)
#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x00b0
#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0)
#define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x00b4
#define AM33XX_CM_WKUP_UART0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4)
#define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x00b8
#define AM33XX_CM_WKUP_I2C0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8)
#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x00bc
#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc)
#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x00c0
#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0)
#define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x00c4
#define AM33XX_CM_WKUP_TIMER1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4)
#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x00c8
#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8)
#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc
#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
#define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET 0x00d0
#define AM33XX_CM_WKUP_WDT0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0)
#define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x00d4
#define AM33XX_CM_WKUP_WDT1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4)
#define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET 0x00d8
#define AM33XX_CM_DIV_M6_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8)
/* CM.DPLL_CM register offsets */
#define AM33XX_CLKSEL_TIMER7_CLK_OFFSET 0x0004
#define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004)
#define AM33XX_CLKSEL_TIMER2_CLK_OFFSET 0x0008
#define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008)
#define AM33XX_CLKSEL_TIMER3_CLK_OFFSET 0x000c
#define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c)
#define AM33XX_CLKSEL_TIMER4_CLK_OFFSET 0x0010
#define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010)
#define AM33XX_CM_MAC_CLKSEL_OFFSET 0x0014
#define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014)
#define AM33XX_CLKSEL_TIMER5_CLK_OFFSET 0x0018
#define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018)
#define AM33XX_CLKSEL_TIMER6_CLK_OFFSET 0x001c
#define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c)
#define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET 0x0020
#define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020)
#define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET 0x0028
#define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028)
#define AM33XX_CLKSEL_GFX_FCLK_OFFSET 0x002c
#define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
#define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET 0x0030
#define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030)
#define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET 0x0034
#define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034)
#define AM33XX_CLKSEL_WDT1_CLK_OFFSET 0x0038
#define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038)
#define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c
#define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c)
/* CM.MPU_CM register offsets */
#define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
#define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
#define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0004
#define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
/* CM.DEVICE_CM register offsets */
#define AM33XX_CM_CLKOUT_CTRL_OFFSET 0x0000
#define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000)
/* CM.RTC_CM register offsets */
#define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0000
#define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000)
#define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004
#define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
/* CM.GFX_CM register offsets */
#define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000
#define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
#define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0004
#define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004)
#define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET 0x0008
#define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008)
#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c
#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
#define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010
#define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010)
#define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014
#define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014)
/* CM.CEFUSE_CM register offsets */
#define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
#define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
#ifdef CONFIG_SOC_AM33XX
extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
u16 clkctrl_offs);
extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
u16 clkctrl_offs);
extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
u16 clkctrl_offs);
extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
u16 clkctrl_offs);
#else
static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
u16 clkctrl_offs)
{
return 0;
}
static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
u16 clkctrl_offs)
{
}
static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
u16 clkctrl_offs)
{
}
static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
u16 clkctrl_offs)
{
return 0;
}
#endif
#endif

3
arch/arm/mach-omap2/common.h
View File

@ -120,6 +120,7 @@ extern void omap2_init_common_infrastructure(void);
extern struct sys_timer omap2_timer;
extern struct sys_timer omap3_timer;
extern struct sys_timer omap3_secure_timer;
extern struct sys_timer omap3_am33xx_timer;
extern struct sys_timer omap4_timer;
void omap2420_init_early(void);
@ -128,8 +129,10 @@ void omap3430_init_early(void);
void omap35xx_init_early(void);
void omap3630_init_early(void);
void omap3_init_early(void); /* Do not use this one */
void am33xx_init_early(void);
void am35xx_init_early(void);
void ti81xx_init_early(void);
void am33xx_init_early(void);
void omap4430_init_early(void);
void omap3_init_late(void); /* Do not use this one */
void omap4430_init_late(void);

37
arch/arm/mach-omap2/control.h
View File

@ -21,6 +21,8 @@
#include <mach/ctrl_module_pad_core_44xx.h>
#include <mach/ctrl_module_pad_wkup_44xx.h>
#include <plat/am33xx.h>
#ifndef __ASSEMBLY__
#define OMAP242X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@ -28,6 +30,8 @@
OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
#define OMAP343X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
#define AM33XX_CTRL_REGADDR(reg) \
AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
#else
#define OMAP242X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@ -35,6 +39,8 @@
OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
#define OMAP343X_CTRL_REGADDR(reg) \
OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
#define AM33XX_CTRL_REGADDR(reg) \
AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
#endif /* __ASSEMBLY__ */
/*
@ -312,15 +318,15 @@
OMAP343X_SCRATCHPAD + reg)
/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
#define AM35XX_HECC_VBUSP_CLK_SHIFT 3
#define AM35XX_USBOTG_FCLK_SHIFT 8
#define AM35XX_CPGMAC_FCLK_SHIFT 9
#define AM35XX_VPFE_FCLK_SHIFT 10
#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
#define AM35XX_HECC_VBUSP_CLK_SHIFT 3
#define AM35XX_USBOTG_FCLK_SHIFT 8
#define AM35XX_CPGMAC_FCLK_SHIFT 9
#define AM35XX_VPFE_FCLK_SHIFT 10
/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
/* AM35XX CONTROL_LVL_INTR_CLEAR bits */
#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
@ -330,21 +336,22 @@
#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
/*AM35XX CONTROL_IP_SW_RESET bits*/
/* AM35XX CONTROL_IP_SW_RESET bits */
#define AM35XX_USBOTGSS_SW_RST BIT(0)
#define AM35XX_CPGMACSS_SW_RST BIT(1)
#define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
#define AM35XX_HECC_SW_RST BIT(3)
#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
/*
* CONTROL AM33XX STATUS register
*/
/* AM33XX CONTROL_STATUS register */
#define AM33XX_CONTROL_STATUS 0x040
#define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc
/*
* CONTROL OMAP STATUS register to identify OMAP3 features
*/
/* AM33XX CONTROL_STATUS bitfields (partial) */
#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22
#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
/* CONTROL OMAP STATUS register to identify OMAP3 features */
#define OMAP3_CONTROL_OMAP_STATUS 0x044c
#define OMAP3_SGX_SHIFT 13

17
arch/arm/mach-omap2/include/mach/debug-macro.S
View File

@ -72,6 +72,8 @@ omap_uart_lsr: .word 0
beq 82f @ configure UART2
cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different
beq 83f @ configure UART3
cmp \rp, #AM33XXUART1 @ AM33XX UART offsets different
beq 84f @ configure UART1
cmp \rp, #ZOOM_UART @ only on zoom2/3
beq 95f @ configure ZOOM_UART
@ -100,7 +102,9 @@ omap_uart_lsr: .word 0
b 98f
83: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE)
b 98f
84: ldr \rp, =AM33XX_UART1_BASE
and \rp, \rp, #0x00ffffff
b 97f
95: ldr \rp, =ZOOM_UART_BASE
str \rp, [\tmp, #0] @ omap_uart_phys
ldr \rp, =ZOOM_UART_VIRT
@ -109,6 +113,17 @@ omap_uart_lsr: .word 0
str \rp, [\tmp, #8] @ omap_uart_lsr
b 10b
/* AM33XX: Store both phys and virt address for the uart */
97: add \rp, \rp, #0x44000000 @ phys base
str \rp, [\tmp, #0] @ omap_uart_phys
sub \rp, \rp, #0x44000000 @ phys base
add \rp, \rp, #0xf9000000 @ virt base
str \rp, [\tmp, #4] @ omap_uart_virt
mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
str \rp, [\tmp, #8] @ omap_uart_lsr
b 10b
/* Store both phys and virt address for the uart */
98: add \rp, \rp, #0x48000000 @ phys base
str \rp, [\tmp, #0] @ omap_uart_phys

13
arch/arm/mach-omap2/io.c
View File

@ -477,6 +477,19 @@ void __init ti81xx_init_late(void)
}
#endif
#ifdef CONFIG_SOC_AM33XX
void __init am33xx_init_early(void)
{
omap2_set_globals_am33xx();
omap3xxx_check_revision();
ti81xx_check_features();
omap_common_init_early();
am33xx_voltagedomains_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
}
#endif
#ifdef CONFIG_ARCH_OMAP4
void __init omap4430_init_early(void)
{

2
arch/arm/mach-omap2/irq.c
View File

@ -280,7 +280,7 @@ int __init omap_intc_of_init(struct device_node *node,
return 0;
}
#ifdef CONFIG_ARCH_OMAP3
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
void omap_intc_save_context(void)

23
arch/arm/mach-omap2/powerdomain.h
View File

@ -67,9 +67,9 @@
/*
* Maximum number of clockdomains that can be associated with a powerdomain.
* CORE powerdomain on OMAP4 is the worst case
* PER powerdomain on AM33XX is the worst case
*/
#define PWRDM_MAX_CLKDMS 9
#define PWRDM_MAX_CLKDMS 11
/* XXX A completely arbitrary number. What is reasonable here? */
#define PWRDM_TRANSITION_BAILOUT 100000
@ -92,6 +92,15 @@ struct powerdomain;
* @pwrdm_clkdms: Clockdomains in this powerdomain
* @node: list_head linking all powerdomains
* @voltdm_node: list_head linking all powerdomains in a voltagedomain
* @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
* @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
* @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
* in @pwrstctrl_offs
* @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
* @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
* @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
* @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
* in @pwrstctrl_offs
* @state:
* @state_counter:
* @timer:
@ -121,6 +130,14 @@ struct powerdomain {
unsigned ret_logic_off_counter;
unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
const u8 pwrstctrl_offs;
const u8 pwrstst_offs;
const u32 logicretstate_mask;
const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
#ifdef CONFIG_PM_DEBUG
s64 timer;
s64 state_timer[PWRDM_MAX_PWRSTS];
@ -222,10 +239,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
extern void omap242x_powerdomains_init(void);
extern void omap243x_powerdomains_init(void);
extern void omap3xxx_powerdomains_init(void);
extern void am33xx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);
extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;
extern struct pwrdm_ops am33xx_pwrdm_operations;
extern struct pwrdm_ops omap4_pwrdm_operations;
/* Common Internal functions used across OMAP rev's */

229
arch/arm/mach-omap2/powerdomain33xx.c Normal file
View File

@ -0,0 +1,229 @@
/*
* AM33XX Powerdomain control
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
*
* Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak
* <rnayak@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <plat/prcm.h>
#include "powerdomain.h"
#include "prm33xx.h"
#include "prm-regbits-33xx.h"
static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
{
am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
(pwrst << OMAP_POWERSTATE_SHIFT),
pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
return 0;
}
static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
{
u32 v;
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
v &= OMAP_POWERSTATE_MASK;
v >>= OMAP_POWERSTATE_SHIFT;
return v;
}
static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
{
u32 v;
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
v &= OMAP_POWERSTATEST_MASK;
v >>= OMAP_POWERSTATEST_SHIFT;
return v;
}
static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
{
u32 v;
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
return v;
}
static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
{
am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
(1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
return 0;
}
static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
{
am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
AM33XX_LASTPOWERSTATEENTERED_MASK,
pwrdm->prcm_offs, pwrdm->pwrstst_offs);
return 0;
}
static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
{
u32 m;
m = pwrdm->logicretstate_mask;
if (!m)
return -EINVAL;
am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
return 0;
}
static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
{
u32 v;
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
v &= AM33XX_LOGICSTATEST_MASK;
v >>= AM33XX_LOGICSTATEST_SHIFT;
return v;
}
static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
{
u32 v, m;
m = pwrdm->logicretstate_mask;
if (!m)
return -EINVAL;
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
v &= m;
v >>= __ffs(m);
return v;
}
static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
u8 pwrst)
{
u32 m;
m = pwrdm->mem_on_mask[bank];
if (!m)
return -EINVAL;
am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
return 0;
}
static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
u8 pwrst)
{
u32 m;
m = pwrdm->mem_ret_mask[bank];
if (!m)
return -EINVAL;
am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
return 0;
}
static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
{
u32 m, v;
m = pwrdm->mem_pwrst_mask[bank];
if (!m)
return -EINVAL;
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
v &= m;
v >>= __ffs(m);
return v;
}
static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
{
u32 m, v;
m = pwrdm->mem_retst_mask[bank];
if (!m)
return -EINVAL;
v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
v &= m;
v >>= __ffs(m);
return v;
}
static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
{
u32 c = 0;
/*
* REVISIT: pwrdm_wait_transition() may be better implemented
* via a callback and a periodic timer check -- how long do we expect
* powerdomain transitions to take?
*/
/* XXX Is this udelay() value meaningful? */
while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
& OMAP_INTRANSITION_MASK) &&
(c++ < PWRDM_TRANSITION_BAILOUT))
udelay(1);
if (c > PWRDM_TRANSITION_BAILOUT) {
pr_err("powerdomain: %s: waited too long to complete transition\n",
pwrdm->name);
return -EAGAIN;
}
pr_debug("powerdomain: completed transition in %d loops\n", c);
return 0;
}
struct pwrdm_ops am33xx_pwrdm_operations = {
.pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst,
.pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst,
.pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst,
.pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst,
.pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst,
.pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst,
.pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst,
.pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst,
.pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange,
.pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst,
.pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst,
.pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst,
.pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst,
.pwrdm_wait_transition = am33xx_pwrdm_wait_transition,
};

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/*
* AM33XX Power domain data
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include "powerdomain.h"
#include "prcm-common.h"
#include "prm-regbits-33xx.h"
#include "prm33xx.h"
static struct powerdomain gfx_33xx_pwrdm = {
.name = "gfx_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = AM33XX_PRM_GFX_MOD,
.pwrstctrl_offs = AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
.pwrstst_offs = AM33XX_PM_GFX_PWRSTST_OFFSET,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
.banks = 1,
.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
.mem_on_mask = {
[0] = AM33XX_GFX_MEM_ONSTATE_MASK, /* gfx_mem */
},
.mem_ret_mask = {
[0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
},
.mem_pwrst_mask = {
[0] = AM33XX_GFX_MEM_STATEST_MASK, /* gfx_mem */
},
.mem_retst_mask = {
[0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
},
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* gfx_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* gfx_mem */
},
};
static struct powerdomain rtc_33xx_pwrdm = {
.name = "rtc_pwrdm",
.voltdm = { .name = "rtc" },
.prcm_offs = AM33XX_PRM_RTC_MOD,
.pwrstctrl_offs = AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
.pwrstst_offs = AM33XX_PM_RTC_PWRSTST_OFFSET,
.pwrsts = PWRSTS_ON,
.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
};
static struct powerdomain wkup_33xx_pwrdm = {
.name = "wkup_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = AM33XX_PRM_WKUP_MOD,
.pwrstctrl_offs = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
.pwrstst_offs = AM33XX_PM_WKUP_PWRSTST_OFFSET,
.pwrsts = PWRSTS_ON,
.logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
};
static struct powerdomain per_33xx_pwrdm = {
.name = "per_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = AM33XX_PRM_PER_MOD,
.pwrstctrl_offs = AM33XX_PM_PER_PWRSTCTRL_OFFSET,
.pwrstst_offs = AM33XX_PM_PER_PWRSTST_OFFSET,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
.banks = 3,
.logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
.mem_on_mask = {
[0] = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */
[1] = AM33XX_PER_MEM_ONSTATE_MASK, /* per_mem */
[2] = AM33XX_RAM_MEM_ONSTATE_MASK, /* ram_mem */
},
.mem_ret_mask = {
[0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
[1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
[2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
},
.mem_pwrst_mask = {
[0] = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */
[1] = AM33XX_PER_MEM_STATEST_MASK, /* per_mem */
[2] = AM33XX_RAM_MEM_STATEST_MASK, /* ram_mem */
},
.mem_retst_mask = {
[0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
[1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
[2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
},
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* pruss_mem */
[1] = PWRSTS_OFF_RET, /* per_mem */
[2] = PWRSTS_OFF_RET, /* ram_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* pruss_mem */
[1] = PWRSTS_ON, /* per_mem */
[2] = PWRSTS_ON, /* ram_mem */
},
};
static struct powerdomain mpu_33xx_pwrdm = {
.name = "mpu_pwrdm",
.voltdm = { .name = "mpu" },
.prcm_offs = AM33XX_PRM_MPU_MOD,
.pwrstctrl_offs = AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
.pwrstst_offs = AM33XX_PM_MPU_PWRSTST_OFFSET,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
.banks = 3,
.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
.mem_on_mask = {
[0] = AM33XX_MPU_L1_ONSTATE_MASK, /* mpu_l1 */
[1] = AM33XX_MPU_L2_ONSTATE_MASK, /* mpu_l2 */
[2] = AM33XX_MPU_RAM_ONSTATE_MASK, /* mpu_ram */
},
.mem_ret_mask = {
[0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
[1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
[2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
},
.mem_pwrst_mask = {
[0] = AM33XX_MPU_L1_STATEST_MASK, /* mpu_l1 */
[1] = AM33XX_MPU_L2_STATEST_MASK, /* mpu_l2 */
[2] = AM33XX_MPU_RAM_STATEST_MASK, /* mpu_ram */
},
.mem_retst_mask = {
[0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
[1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
[2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
},
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* mpu_l1 */
[1] = PWRSTS_OFF_RET, /* mpu_l2 */
[2] = PWRSTS_OFF_RET, /* mpu_ram */
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* mpu_l1 */
[1] = PWRSTS_ON, /* mpu_l2 */
[2] = PWRSTS_ON, /* mpu_ram */
},
};
static struct powerdomain cefuse_33xx_pwrdm = {
.name = "cefuse_pwrdm",
.voltdm = { .name = "core" },
.prcm_offs = AM33XX_PRM_CEFUSE_MOD,
.pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
.pwrstst_offs = AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
.pwrsts = PWRSTS_OFF_ON,
};
static struct powerdomain *powerdomains_am33xx[] __initdata = {
&gfx_33xx_pwrdm,
&rtc_33xx_pwrdm,
&wkup_33xx_pwrdm,
&per_33xx_pwrdm,
&mpu_33xx_pwrdm,
&cefuse_33xx_pwrdm,
NULL,
};
void __init am33xx_powerdomains_init(void)
{
pwrdm_register_platform_funcs(&am33xx_pwrdm_operations);
pwrdm_register_pwrdms(powerdomains_am33xx);
pwrdm_complete_init();
}

357
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/*
* AM33XX PRM_XXX register bits
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
#include "prm.h"
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1
#define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2
#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_AIPOFF_SHIFT 8
#define AM33XX_AIPOFF_MASK (1 << 8)
/* Used by PM_WKUP_PWRSTST */
#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17
#define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0
#define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12
#define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12
#define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14
#define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14
#define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15
#define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13
#define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11
#define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11
#define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13
#define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15
#define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15)
/* Used by RM_WKUP_RSTST */
#define AM33XX_EMULATION_M3_RST_SHIFT 6
#define AM33XX_EMULATION_M3_RST_MASK (1 << 6)
/* Used by RM_MPU_RSTST */
#define AM33XX_EMULATION_MPU_RST_SHIFT 5
#define AM33XX_EMULATION_MPU_RST_MASK (1 << 5)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ENFUNC1_EXPORT_SHIFT 3
#define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ENFUNC3_EXPORT_SHIFT 5
#define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ENFUNC4_SHIFT 6
#define AM33XX_ENFUNC4_MASK (1 << 6)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ENFUNC5_SHIFT 7
#define AM33XX_ENFUNC5_MASK (1 << 7)
/* Used by PRM_RSTST */
#define AM33XX_EXTERNAL_WARM_RST_SHIFT 5
#define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_FORCEWKUP_EN_SHIFT 10
#define AM33XX_FORCEWKUP_EN_MASK (1 << 10)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_FORCEWKUP_ST_SHIFT 10
#define AM33XX_FORCEWKUP_ST_MASK (1 << 10)
/* Used by PM_GFX_PWRSTCTRL */
#define AM33XX_GFX_MEM_ONSTATE_SHIFT 17
#define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17)
/* Used by PM_GFX_PWRSTCTRL */
#define AM33XX_GFX_MEM_RETSTATE_SHIFT 6
#define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6)
/* Used by PM_GFX_PWRSTST */
#define AM33XX_GFX_MEM_STATEST_SHIFT 4
#define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4)
/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
#define AM33XX_GFX_RST_SHIFT 0
#define AM33XX_GFX_RST_MASK (1 << 0)
/* Used by PRM_RSTST */
#define AM33XX_GLOBAL_COLD_RST_SHIFT 0
#define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0)
/* Used by PRM_RSTST */
#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1
#define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1)
/* Used by RM_WKUP_RSTST */
#define AM33XX_ICECRUSHER_M3_RST_SHIFT 7
#define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7)
/* Used by RM_MPU_RSTST */
#define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6
#define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6)
/* Used by PRM_RSTST */
#define AM33XX_ICEPICK_RST_SHIFT 9
#define AM33XX_ICEPICK_RST_MASK (1 << 9)
/* Used by RM_PER_RSTCTRL */
#define AM33XX_PRUSS_LRST_SHIFT 1
#define AM33XX_PRUSS_LRST_MASK (1 << 1)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5
#define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7
#define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7)
/* Used by PM_PER_PWRSTST */
#define AM33XX_PRUSS_MEM_STATEST_SHIFT 23
#define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23)
/*
* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
* PM_WKUP_PWRSTST, PM_RTC_PWRSTST
*/
#define AM33XX_INTRANSITION_SHIFT 20
#define AM33XX_INTRANSITION_MASK (1 << 20)
/* Used by PM_CEFUSE_PWRSTST */
#define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24
#define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
#define AM33XX_LOGICRETSTATE_SHIFT 2
#define AM33XX_LOGICRETSTATE_MASK (1 << 2)
/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
#define AM33XX_LOGICRETSTATE_3_3_SHIFT 3
#define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3)
/*
* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
* PM_WKUP_PWRSTST, PM_RTC_PWRSTST
*/
#define AM33XX_LOGICSTATEST_SHIFT 2
#define AM33XX_LOGICSTATEST_MASK (1 << 2)
/*
* Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
* PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
*/
#define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4
#define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_L1_ONSTATE_SHIFT 18
#define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_L1_RETSTATE_SHIFT 22
#define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22)
/* Used by PM_MPU_PWRSTST */
#define AM33XX_MPU_L1_STATEST_SHIFT 6
#define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_L2_ONSTATE_SHIFT 20
#define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_L2_RETSTATE_SHIFT 23
#define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23)
/* Used by PM_MPU_PWRSTST */
#define AM33XX_MPU_L2_STATEST_SHIFT 8
#define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_RAM_ONSTATE_SHIFT 16
#define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_RAM_RETSTATE_SHIFT 24
#define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24)
/* Used by PM_MPU_PWRSTST */
#define AM33XX_MPU_RAM_STATEST_SHIFT 4
#define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4)
/* Used by PRM_RSTST */
#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2
#define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
/* Used by PRM_SRAM_COUNT */
#define AM33XX_PCHARGECNT_VALUE_SHIFT 0
#define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0)
/* Used by RM_PER_RSTCTRL */
#define AM33XX_PCI_LRST_SHIFT 0
#define AM33XX_PCI_LRST_MASK (1 << 0)
/* Renamed from PCI_LRST Used by RM_PER_RSTST */
#define AM33XX_PCI_LRST_5_5_SHIFT 5
#define AM33XX_PCI_LRST_5_5_MASK (1 << 5)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_PER_MEM_ONSTATE_SHIFT 25
#define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_PER_MEM_RETSTATE_SHIFT 29
#define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29)
/* Used by PM_PER_PWRSTST */
#define AM33XX_PER_MEM_STATEST_SHIFT 17
#define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17)
/*
* Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
* PM_MPU_PWRSTCTRL
*/
#define AM33XX_POWERSTATE_SHIFT 0
#define AM33XX_POWERSTATE_MASK (0x3 << 0)
/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
#define AM33XX_POWERSTATEST_SHIFT 0
#define AM33XX_POWERSTATEST_MASK (0x3 << 0)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_RAM_MEM_ONSTATE_SHIFT 30
#define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_RAM_MEM_RETSTATE_SHIFT 27
#define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27)
/* Used by PM_PER_PWRSTST */
#define AM33XX_RAM_MEM_STATEST_SHIFT 21
#define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21)
/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
#define AM33XX_RETMODE_ENABLE_SHIFT 0
#define AM33XX_RETMODE_ENABLE_MASK (1 << 0)
/* Used by REVISION_PRM */
#define AM33XX_REV_SHIFT 0
#define AM33XX_REV_MASK (0xff << 0)
/* Used by PRM_RSTTIME */
#define AM33XX_RSTTIME1_SHIFT 0
#define AM33XX_RSTTIME1_MASK (0xff << 0)
/* Used by PRM_RSTTIME */
#define AM33XX_RSTTIME2_SHIFT 8
#define AM33XX_RSTTIME2_MASK (0x1f << 8)
/* Used by PRM_RSTCTRL */
#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1
#define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1)
/* Used by PRM_RSTCTRL */
#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0
#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
/* Used by PRM_SRAM_COUNT */
#define AM33XX_SLPCNT_VALUE_SHIFT 16
#define AM33XX_SLPCNT_VALUE_MASK (0xff << 16)
/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
#define AM33XX_SRAMLDO_STATUS_SHIFT 8
#define AM33XX_SRAMLDO_STATUS_MASK (1 << 8)
/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
#define AM33XX_SRAM_IN_TRANSITION_SHIFT 9
#define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9)
/* Used by PRM_SRAM_COUNT */
#define AM33XX_STARTUP_COUNT_SHIFT 24
#define AM33XX_STARTUP_COUNT_MASK (0xff << 24)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_TRANSITION_EN_SHIFT 8
#define AM33XX_TRANSITION_EN_MASK (1 << 8)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_TRANSITION_ST_SHIFT 8
#define AM33XX_TRANSITION_ST_MASK (1 << 8)
/* Used by PRM_SRAM_COUNT */
#define AM33XX_VSETUPCNT_VALUE_SHIFT 8
#define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8)
/* Used by PRM_RSTST */
#define AM33XX_WDT0_RST_SHIFT 3
#define AM33XX_WDT0_RST_MASK (1 << 3)
/* Used by PRM_RSTST */
#define AM33XX_WDT1_RST_SHIFT 4
#define AM33XX_WDT1_RST_MASK (1 << 4)
/* Used by RM_WKUP_RSTCTRL */
#define AM33XX_WKUP_M3_LRST_SHIFT 3
#define AM33XX_WKUP_M3_LRST_MASK (1 << 3)
/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
#define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5
#define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5)
#endif

135
arch/arm/mach-omap2/prm33xx.c Normal file
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@ -0,0 +1,135 @@
/*
* AM33XX PRM functions
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>
#include <plat/common.h>
#include "common.h"
#include "prm33xx.h"
#include "prm-regbits-33xx.h"
/* Read a register in a PRM instance */
u32 am33xx_prm_read_reg(s16 inst, u16 idx)
{
return __raw_readl(prm_base + inst + idx);
}
/* Write into a register in a PRM instance */
void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
{
__raw_writel(val, prm_base + inst + idx);
}
/* Read-modify-write a register in PRM. Caller must lock */
u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
{
u32 v;
v = am33xx_prm_read_reg(inst, idx);
v &= ~mask;
v |= bits;
am33xx_prm_write_reg(v, inst, idx);
return v;
}
/**
* am33xx_prm_is_hardreset_asserted - read the HW reset line state of
* submodules contained in the hwmod module
* @shift: register bit shift corresponding to the reset line to check
* @inst: CM instance register offset (*_INST macro)
* @rstctrl_offs: RM_RSTCTRL register address offset for this module
*
* Returns 1 if the (sub)module hardreset line is currently asserted,
* 0 if the (sub)module hardreset line is not currently asserted, or
* -EINVAL upon parameter error.
*/
int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
{
u32 v;
v = am33xx_prm_read_reg(inst, rstctrl_offs);
v &= 1 << shift;
v >>= shift;
return v;
}
/**
* am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
* @shift: register bit shift corresponding to the reset line to assert
* @inst: CM instance register offset (*_INST macro)
* @rstctrl_reg: RM_RSTCTRL register address for this module
*
* Some IPs like dsp, ipu or iva contain processors that require an HW
* reset line to be asserted / deasserted in order to fully enable the
* IP. These modules may have multiple hard-reset lines that reset
* different 'submodules' inside the IP block. This function will
* place the submodule into reset. Returns 0 upon success or -EINVAL
* upon an argument error.
*/
int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
{
u32 mask = 1 << shift;
am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
return 0;
}
/**
* am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
* wait
* @shift: register bit shift corresponding to the reset line to deassert
* @inst: CM instance register offset (*_INST macro)
* @rstctrl_reg: RM_RSTCTRL register address for this module
* @rstst_reg: RM_RSTST register address for this module
*
* Some IPs like dsp, ipu or iva contain processors that require an HW
* reset line to be asserted / deasserted in order to fully enable the
* IP. These modules may have multiple hard-reset lines that reset
* different 'submodules' inside the IP block. This function will
* take the submodule out of reset and wait until the PRCM indicates
* that the reset has completed before returning. Returns 0 upon success or
* -EINVAL upon an argument error, -EEXIST if the submodule was already out
* of reset, or -EBUSY if the submodule did not exit reset promptly.
*/
int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
u16 rstctrl_offs, u16 rstst_offs)
{
int c;
u32 mask = 1 << shift;
/* Check the current status to avoid de-asserting the line twice */
if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
return -EEXIST;
/* Clear the reset status by writing 1 to the status bit */
am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
/* de-assert the reset control line */
am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
/* wait the status to be set */
omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
rstst_offs),
MAX_MODULE_HARDRESET_WAIT, c);
return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
}

129
arch/arm/mach-omap2/prm33xx.h Normal file
View File

@ -0,0 +1,129 @@
/*
* AM33XX PRM instance offset macros
*
* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
#include "prcm-common.h"
#include "prm.h"
#define AM33XX_PRM_BASE 0x44E00000
#define AM33XX_PRM_REGADDR(inst, reg) \
AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
/* PRM instances */
#define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
#define AM33XX_PRM_PER_MOD 0x0C00
#define AM33XX_PRM_WKUP_MOD 0x0D00
#define AM33XX_PRM_MPU_MOD 0x0E00
#define AM33XX_PRM_DEVICE_MOD 0x0F00
#define AM33XX_PRM_RTC_MOD 0x1000
#define AM33XX_PRM_GFX_MOD 0x1100
#define AM33XX_PRM_CEFUSE_MOD 0x1200
/* PRM */
/* PRM.OCP_SOCKET_PRM register offsets */
#define AM33XX_REVISION_PRM_OFFSET 0x0000
#define AM33XX_REVISION_PRM AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000)
#define AM33XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
#define AM33XX_PRM_IRQSTATUS_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004)
#define AM33XX_PRM_IRQENABLE_MPU_OFFSET 0x0008
#define AM33XX_PRM_IRQENABLE_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008)
#define AM33XX_PRM_IRQSTATUS_M3_OFFSET 0x000c
#define AM33XX_PRM_IRQSTATUS_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c)
#define AM33XX_PRM_IRQENABLE_M3_OFFSET 0x0010
#define AM33XX_PRM_IRQENABLE_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010)
/* PRM.PER_PRM register offsets */
#define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000
#define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
#define AM33XX_RM_PER_RSTST_OFFSET 0x0004
#define AM33XX_RM_PER_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004)
#define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
#define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
#define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c
#define AM33XX_PM_PER_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c)
/* PRM.WKUP_PRM register offsets */
#define AM33XX_RM_WKUP_RSTCTRL_OFFSET 0x0000
#define AM33XX_RM_WKUP_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000)
#define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET 0x0004
#define AM33XX_PM_WKUP_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004)
#define AM33XX_PM_WKUP_PWRSTST_OFFSET 0x0008
#define AM33XX_PM_WKUP_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008)
#define AM33XX_RM_WKUP_RSTST_OFFSET 0x000c
#define AM33XX_RM_WKUP_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c)
/* PRM.MPU_PRM register offsets */
#define AM33XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
#define AM33XX_PM_MPU_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000)
#define AM33XX_PM_MPU_PWRSTST_OFFSET 0x0004
#define AM33XX_PM_MPU_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004)
#define AM33XX_RM_MPU_RSTST_OFFSET 0x0008
#define AM33XX_RM_MPU_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008)
/* PRM.DEVICE_PRM register offsets */
#define AM33XX_PRM_RSTCTRL_OFFSET 0x0000
#define AM33XX_PRM_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000)
#define AM33XX_PRM_RSTTIME_OFFSET 0x0004
#define AM33XX_PRM_RSTTIME AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004)
#define AM33XX_PRM_RSTST_OFFSET 0x0008
#define AM33XX_PRM_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008)
#define AM33XX_PRM_SRAM_COUNT_OFFSET 0x000c
#define AM33XX_PRM_SRAM_COUNT AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c)
#define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x0010
#define AM33XX_PRM_LDO_SRAM_CORE_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010)
#define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x0014
#define AM33XX_PRM_LDO_SRAM_CORE_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014)
#define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x0018
#define AM33XX_PRM_LDO_SRAM_MPU_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018)
#define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x001c
#define AM33XX_PRM_LDO_SRAM_MPU_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c)
/* PRM.RTC_PRM register offsets */
#define AM33XX_PM_RTC_PWRSTCTRL_OFFSET 0x0000
#define AM33XX_PM_RTC_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000)
#define AM33XX_PM_RTC_PWRSTST_OFFSET 0x0004
#define AM33XX_PM_RTC_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004)
/* PRM.GFX_PRM register offsets */
#define AM33XX_PM_GFX_PWRSTCTRL_OFFSET 0x0000
#define AM33XX_PM_GFX_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000)
#define AM33XX_RM_GFX_RSTCTRL_OFFSET 0x0004
#define AM33XX_RM_GFX_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004)
#define AM33XX_PM_GFX_PWRSTST_OFFSET 0x0010
#define AM33XX_PM_GFX_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010)
#define AM33XX_RM_GFX_RSTST_OFFSET 0x0014
#define AM33XX_RM_GFX_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014)
/* PRM.CEFUSE_PRM register offsets */
#define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000
#define AM33XX_PM_CEFUSE_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000)
#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004
#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
extern void am33xx_prm_global_warm_sw_reset(void);
extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
u16 rstctrl_offs);
extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
u16 rstctrl_offs, u16 rstst_offs);
#endif

5
arch/arm/mach-omap2/timer.c
View File

@ -368,6 +368,11 @@ OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
OMAP_SYS_TIMER(3_secure)
#endif
#ifdef CONFIG_SOC_AM33XX
OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
OMAP_SYS_TIMER(3_am33xx)
#endif
#ifdef CONFIG_ARCH_OMAP4
#ifdef CONFIG_LOCAL_TIMERS
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,

1
arch/arm/mach-omap2/voltage.h
View File

@ -156,6 +156,7 @@ int omap_voltage_late_init(void);
extern void omap2xxx_voltagedomains_init(void);
extern void omap3xxx_voltagedomains_init(void);
extern void am33xx_voltagedomains_init(void);
extern void omap44xx_voltagedomains_init(void);
struct voltagedomain *voltdm_lookup(const char *name);

43
arch/arm/mach-omap2/voltagedomains33xx_data.c Normal file
View File

@ -0,0 +1,43 @@
/*
* AM33XX voltage domain data
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include "voltage.h"
static struct voltagedomain am33xx_voltdm_mpu = {
.name = "mpu",
};
static struct voltagedomain am33xx_voltdm_core = {
.name = "core",
};
static struct voltagedomain am33xx_voltdm_rtc = {
.name = "rtc",
};
static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
&am33xx_voltdm_mpu,
&am33xx_voltdm_core,
&am33xx_voltdm_rtc,
NULL,
};
void __init am33xx_voltagedomains_init(void)
{
voltdm_init(voltagedomains_am33xx);
}

3
arch/arm/mach-tegra/Makefile
View File

@ -9,6 +9,7 @@ obj-y += fuse.o
obj-y += pmc.o
obj-y += flowctrl.o
obj-y += powergate.o
obj-y += apbio.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_CPU_IDLE) += sleep.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
@ -18,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_SMP) += reset.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o apbio.o
obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o
obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o
obj-$(CONFIG_TEGRA_PCI) += pcie.o
obj-$(CONFIG_USB_SUPPORT) += usb_phy.o

194
arch/arm/mach-tegra/apbio.c
View File

@ -15,6 +15,9 @@
#include <linux/kernel.h>
#include <linux/io.h>
#include <mach/iomap.h>
#include <linux/of.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/spinlock.h>
#include <linux/completion.h>
@ -22,17 +25,21 @@
#include <linux/mutex.h>
#include <mach/dma.h>
#include <mach/iomap.h>
#include "apbio.h"
#if defined(CONFIG_TEGRA_SYSTEM_DMA) || defined(CONFIG_TEGRA20_APB_DMA)
static DEFINE_MUTEX(tegra_apb_dma_lock);
static struct tegra_dma_channel *tegra_apb_dma;
static u32 *tegra_apb_bb;
static dma_addr_t tegra_apb_bb_phys;
static DECLARE_COMPLETION(tegra_apb_wait);
static u32 tegra_apb_readl_direct(unsigned long offset);
static void tegra_apb_writel_direct(u32 value, unsigned long offset);
#if defined(CONFIG_TEGRA_SYSTEM_DMA)
static struct tegra_dma_channel *tegra_apb_dma;
bool tegra_apb_init(void)
{
struct tegra_dma_channel *ch;
@ -72,13 +79,13 @@ static void apb_dma_complete(struct tegra_dma_req *req)
complete(&tegra_apb_wait);
}
u32 tegra_apb_readl(unsigned long offset)
static u32 tegra_apb_readl_using_dma(unsigned long offset)
{
struct tegra_dma_req req;
int ret;
if (!tegra_apb_dma && !tegra_apb_init())
return readl(IO_TO_VIRT(offset));
return tegra_apb_readl_direct(offset);
mutex_lock(&tegra_apb_dma_lock);
req.complete = apb_dma_complete;
@ -108,13 +115,13 @@ u32 tegra_apb_readl(unsigned long offset)
return *((u32 *)tegra_apb_bb);
}
void tegra_apb_writel(u32 value, unsigned long offset)
static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
{
struct tegra_dma_req req;
int ret;
if (!tegra_apb_dma && !tegra_apb_init()) {
writel(value, IO_TO_VIRT(offset));
tegra_apb_writel_direct(value, offset);
return;
}
@ -143,3 +150,176 @@ void tegra_apb_writel(u32 value, unsigned long offset)
mutex_unlock(&tegra_apb_dma_lock);
}
#else
static struct dma_chan *tegra_apb_dma_chan;
static struct dma_slave_config dma_sconfig;
bool tegra_apb_dma_init(void)
{
dma_cap_mask_t mask;
mutex_lock(&tegra_apb_dma_lock);
/* Check to see if we raced to setup */
if (tegra_apb_dma_chan)
goto skip_init;
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
tegra_apb_dma_chan = dma_request_channel(mask, NULL, NULL);
if (!tegra_apb_dma_chan) {
/*
* This is common until the device is probed, so don't
* shout about it.
*/
pr_debug("%s: can not allocate dma channel\n", __func__);
goto err_dma_alloc;
}
tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
&tegra_apb_bb_phys, GFP_KERNEL);
if (!tegra_apb_bb) {
pr_err("%s: can not allocate bounce buffer\n", __func__);
goto err_buff_alloc;
}
dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_sconfig.slave_id = TEGRA_DMA_REQ_SEL_CNTR;
dma_sconfig.src_maxburst = 1;
dma_sconfig.dst_maxburst = 1;
skip_init:
mutex_unlock(&tegra_apb_dma_lock);
return true;
err_buff_alloc:
dma_release_channel(tegra_apb_dma_chan);
tegra_apb_dma_chan = NULL;
err_dma_alloc:
mutex_unlock(&tegra_apb_dma_lock);
return false;
}
static void apb_dma_complete(void *args)
{
complete(&tegra_apb_wait);
}
static int do_dma_transfer(unsigned long apb_add,
enum dma_transfer_direction dir)
{
struct dma_async_tx_descriptor *dma_desc;
int ret;
if (dir == DMA_DEV_TO_MEM)
dma_sconfig.src_addr = apb_add;
else
dma_sconfig.dst_addr = apb_add;
ret = dmaengine_slave_config(tegra_apb_dma_chan, &dma_sconfig);
if (ret)
return ret;
dma_desc = dmaengine_prep_slave_single(tegra_apb_dma_chan,
tegra_apb_bb_phys, sizeof(u32), dir,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!dma_desc)
return -EINVAL;
dma_desc->callback = apb_dma_complete;
dma_desc->callback_param = NULL;
INIT_COMPLETION(tegra_apb_wait);
dmaengine_submit(dma_desc);
dma_async_issue_pending(tegra_apb_dma_chan);
ret = wait_for_completion_timeout(&tegra_apb_wait,
msecs_to_jiffies(50));
if (WARN(ret == 0, "apb read dma timed out")) {
dmaengine_terminate_all(tegra_apb_dma_chan);
return -EFAULT;
}
return 0;
}
static u32 tegra_apb_readl_using_dma(unsigned long offset)
{
int ret;
if (!tegra_apb_dma_chan && !tegra_apb_dma_init())
return tegra_apb_readl_direct(offset);
mutex_lock(&tegra_apb_dma_lock);
ret = do_dma_transfer(offset, DMA_DEV_TO_MEM);
if (ret < 0) {
pr_err("error in reading offset 0x%08lx using dma\n", offset);
*(u32 *)tegra_apb_bb = 0;
}
mutex_unlock(&tegra_apb_dma_lock);
return *((u32 *)tegra_apb_bb);
}
static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
{
int ret;
if (!tegra_apb_dma_chan && !tegra_apb_dma_init()) {
tegra_apb_writel_direct(value, offset);
return;
}
mutex_lock(&tegra_apb_dma_lock);
*((u32 *)tegra_apb_bb) = value;
ret = do_dma_transfer(offset, DMA_MEM_TO_DEV);
if (ret < 0)
pr_err("error in writing offset 0x%08lx using dma\n", offset);
mutex_unlock(&tegra_apb_dma_lock);
}
#endif
#else
#define tegra_apb_readl_using_dma tegra_apb_readl_direct
#define tegra_apb_writel_using_dma tegra_apb_writel_direct
#endif
typedef u32 (*apbio_read_fptr)(unsigned long offset);
typedef void (*apbio_write_fptr)(u32 value, unsigned long offset);
static apbio_read_fptr apbio_read;
static apbio_write_fptr apbio_write;
static u32 tegra_apb_readl_direct(unsigned long offset)
{
return readl(IO_TO_VIRT(offset));
}
static void tegra_apb_writel_direct(u32 value, unsigned long offset)
{
writel(value, IO_TO_VIRT(offset));
}
void tegra_apb_io_init(void)
{
/* Need to use dma only when it is Tegra20 based platform */
if (of_machine_is_compatible("nvidia,tegra20") ||
!of_have_populated_dt()) {
apbio_read = tegra_apb_readl_using_dma;
apbio_write = tegra_apb_writel_using_dma;
} else {
apbio_read = tegra_apb_readl_direct;
apbio_write = tegra_apb_writel_direct;
}
}
u32 tegra_apb_readl(unsigned long offset)
{
return apbio_read(offset);
}
void tegra_apb_writel(u32 value, unsigned long offset)
{
apbio_write(value, offset);
}

19
arch/arm/mach-tegra/apbio.h
View File

@ -16,24 +16,7 @@
#ifndef __MACH_TEGRA_APBIO_H
#define __MACH_TEGRA_APBIO_H
#ifdef CONFIG_TEGRA_SYSTEM_DMA
void tegra_apb_io_init(void);
u32 tegra_apb_readl(unsigned long offset);
void tegra_apb_writel(u32 value, unsigned long offset);
#else
#include <asm/io.h>
#include <mach/io.h>
static inline u32 tegra_apb_readl(unsigned long offset)
{
return readl(IO_TO_VIRT(offset));
}
static inline void tegra_apb_writel(u32 value, unsigned long offset)
{
writel(value, IO_TO_VIRT(offset));
}
#endif
#endif

3
arch/arm/mach-tegra/common.c
View File

@ -33,6 +33,7 @@
#include "clock.h"
#include "fuse.h"
#include "pmc.h"
#include "apbio.h"
/*
* Storage for debug-macro.S's state.
@ -127,6 +128,7 @@ static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
void __init tegra20_init_early(void)
{
tegra_apb_io_init();
tegra_init_fuse();
tegra2_init_clocks();
tegra_clk_init_from_table(tegra20_clk_init_table);
@ -138,6 +140,7 @@ void __init tegra20_init_early(void)
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
void __init tegra30_init_early(void)
{
tegra_apb_io_init();
tegra_init_fuse();
tegra30_init_clocks();
tegra_clk_init_from_table(tegra30_clk_init_table);

5
arch/arm/mach-vexpress/Kconfig
View File

@ -2,7 +2,8 @@ menu "Versatile Express platform type"
depends on ARCH_VEXPRESS
config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
bool
bool "Enable A5 and A9 only errata work-arounds"
default y
select ARM_ERRATA_720789
select ARM_ERRATA_751472
select PL310_ERRATA_753970 if CACHE_PL310
@ -14,7 +15,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
config ARCH_VEXPRESS_CA9X4
bool "Versatile Express Cortex-A9x4 tile"
select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
select ARM_GIC
select CPU_V7
select HAVE_SMP
@ -22,7 +22,6 @@ config ARCH_VEXPRESS_CA9X4
config ARCH_VEXPRESS_DT
bool "Device Tree support for Versatile Express platforms"
select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
select ARM_GIC
select ARM_PATCH_PHYS_VIRT
select AUTO_ZRELADDR

3
arch/arm/mach-vexpress/Makefile.boot
View File

@ -6,4 +6,5 @@ initrd_phys-y := 0x60800000
dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb \
vexpress-v2p-ca9.dtb \
vexpress-v2p-ca15-tc1.dtb
vexpress-v2p-ca15-tc1.dtb \
vexpress-v2p-ca15_a7.dtb

64
arch/arm/mach-vexpress/ct-ca9x4.c
View File

@ -66,8 +66,15 @@ static void __init ct_ca9x4_init_irq(void)
static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
u32 site = v2m_get_master_site();
/*
* Old firmware was using the "site" component of the command
* to control the DVI muxer (while it should be always 0 ie. MB).
* Newer firmware uses the data register. Keep both for compatibility.
*/
v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE(site), site);
v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE(SYS_CFG_SITE_MB), 2);
}
static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
@ -105,43 +112,11 @@ static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
};
static long ct_round(struct clk *clk, unsigned long rate)
{
return rate;
}
static int ct_set(struct clk *clk, unsigned long rate)
{
return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
}
static const struct clk_ops osc1_clk_ops = {
.round = ct_round,
.set = ct_set,
};
static struct clk osc1_clk = {
.ops = &osc1_clk_ops,
.rate = 24000000,
};
static struct clk ct_sp804_clk = {
.rate = 1000000,
};
static struct clk_lookup lookups[] = {
{ /* CLCD */
.dev_id = "ct:clcd",
.clk = &osc1_clk,
}, { /* SP804 timers */
.dev_id = "sp804",
.con_id = "ct-timer0",
.clk = &ct_sp804_clk,
}, { /* SP804 timers */
.dev_id = "sp804",
.con_id = "ct-timer1",
.clk = &ct_sp804_clk,
},
static struct v2m_osc ct_osc1 = {
.osc = 1,
.rate_min = 10000000,
.rate_max = 80000000,
.rate_default = 23750000,
};
static struct resource pmu_resources[] = {
@ -174,14 +149,10 @@ static struct platform_device pmu_device = {
.resource = pmu_resources,
};
static void __init ct_ca9x4_init_early(void)
{
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
}
static void __init ct_ca9x4_init(void)
{
int i;
struct clk *clk;
#ifdef CONFIG_CACHE_L2X0
void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
@ -193,6 +164,10 @@ static void __init ct_ca9x4_init(void)
l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
#endif
ct_osc1.site = v2m_get_master_site();
clk = v2m_osc_register("ct:osc1", &ct_osc1);
clk_register_clkdev(clk, NULL, "ct:clcd");
for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
@ -234,7 +209,6 @@ struct ct_desc ct_ca9x4_desc __initdata = {
.id = V2M_CT_ID_CA9,
.name = "CA9x4",
.map_io = ct_ca9x4_map_io,
.init_early = ct_ca9x4_init_early,
.init_irq = ct_ca9x4_init_irq,
.init_tile = ct_ca9x4_init,
#ifdef CONFIG_SMP

15
arch/arm/mach-vexpress/include/mach/clkdev.h
View File

@ -1,15 +0,0 @@
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#include <plat/clock.h>
struct clk {
const struct clk_ops *ops;
unsigned long rate;
const struct icst_params *params;
};
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

41
arch/arm/mach-vexpress/include/mach/debug-macro.S
View File

@ -18,6 +18,8 @@
#define DEBUG_LL_VIRT_BASE 0xf8000000
#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
.macro addruart,rp,rv,tmp
@ Make an educated guess regarding the memory map:
@ -41,3 +43,42 @@
.endm
#include <asm/hardware/debug-pl01x.S>
#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9)
.macro addruart,rp,rv,tmp
mov \rp, #DEBUG_LL_UART_OFFSET
orr \rv, \rp, #DEBUG_LL_VIRT_BASE
orr \rp, \rp, #DEBUG_LL_PHYS_BASE
.endm
#include <asm/hardware/debug-pl01x.S>
#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1)
.macro addruart,rp,rv,tmp
mov \rp, #DEBUG_LL_UART_OFFSET_RS1
orr \rv, \rp, #DEBUG_LL_VIRT_BASE
orr \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
.endm
#include <asm/hardware/debug-pl01x.S>
#else /* CONFIG_DEBUG_LL_UART_NONE */
.macro addruart, rp, rv, tmp
/* Safe dummy values */
mov \rp, #0
mov \rv, #DEBUG_LL_VIRT_BASE
.endm
.macro senduart,rd,rx
.endm
.macro waituart,rd,rx
.endm
.macro busyuart,rd,rx
.endm
#endif

28
arch/arm/mach-vexpress/include/mach/motherboard.h
View File

@ -1,6 +1,8 @@
#ifndef __MACH_MOTHERBOARD_H
#define __MACH_MOTHERBOARD_H
#include <linux/clk-provider.h>
/*
* Physical addresses, offset from V2M_PA_CS0-3
*/
@ -104,9 +106,10 @@
#define SYS_CFG_REBOOT (9 << 20)
#define SYS_CFG_DVIMODE (11 << 20)
#define SYS_CFG_POWER (12 << 20)
#define SYS_CFG_SITE_MB (0 << 16)
#define SYS_CFG_SITE_DB1 (1 << 16)
#define SYS_CFG_SITE_DB2 (2 << 16)
#define SYS_CFG_SITE(n) ((n) << 16)
#define SYS_CFG_SITE_MB 0
#define SYS_CFG_SITE_DB1 1
#define SYS_CFG_SITE_DB2 2
#define SYS_CFG_STACK(n) ((n) << 12)
#define SYS_CFG_ERR (1 << 1)
@ -122,6 +125,8 @@ void v2m_flags_set(u32 data);
#define SYS_MISC_MASTERSITE (1 << 14)
#define SYS_PROCIDx_HBI_MASK 0xfff
int v2m_get_master_site(void);
/*
* Core tile IDs
*/
@ -144,4 +149,21 @@ struct ct_desc {
extern struct ct_desc *ct_desc;
/*
* OSC clock provider
*/
struct v2m_osc {
struct clk_hw hw;
u8 site; /* 0 = motherboard, 1 = site 1, 2 = site 2 */
u8 stack; /* board stack position */
u16 osc;
unsigned long rate_min;
unsigned long rate_max;
unsigned long rate_default;
};
#define to_v2m_osc(osc) container_of(osc, struct v2m_osc, hw)
struct clk *v2m_osc_register(const char *name, struct v2m_osc *osc);
#endif

14
arch/arm/mach-vexpress/include/mach/uncompress.h
View File

@ -27,6 +27,7 @@
static unsigned long get_uart_base(void)
{
#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
unsigned long mpcore_periph;
/*
@ -42,6 +43,13 @@ static unsigned long get_uart_base(void)
return UART_BASE;
else
return UART_BASE_RS1;
#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9)
return UART_BASE;
#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1)
return UART_BASE_RS1;
#else
return 0;
#endif
}
/*
@ -51,6 +59,9 @@ static inline void putc(int c)
{
unsigned long base = get_uart_base();
if (!base)
return;
while (AMBA_UART_FR(base) & (1 << 5))
barrier();
@ -61,6 +72,9 @@ static inline void flush(void)
{
unsigned long base = get_uart_base();
if (!base)
return;
while (AMBA_UART_FR(base) & (1 << 3))
barrier();
}

274
arch/arm/mach-vexpress/v2m.c
View File

@ -16,7 +16,10 @@
#include <linux/spinlock.h>
#include <linux/usb/isp1760.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/mtd/physmap.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <asm/arch_timer.h>
#include <asm/mach-types.h>
@ -81,16 +84,6 @@ static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
}
static void __init v2m_timer_init(void)
{
v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
}
static struct sys_timer v2m_timer = {
.init = v2m_timer_init,
};
static DEFINE_SPINLOCK(v2m_cfg_lock);
@ -147,6 +140,13 @@ void __init v2m_flags_set(u32 data)
writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
}
int v2m_get_master_site(void)
{
u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
return misc & SYS_MISC_MASTERSITE ? SYS_CFG_SITE_DB2 : SYS_CFG_SITE_DB1;
}
static struct resource v2m_pcie_i2c_resource = {
.start = V2M_SERIAL_BUS_PCI,
@ -201,6 +201,11 @@ static struct platform_device v2m_eth_device = {
.dev.platform_data = &v2m_eth_config,
};
static struct regulator_consumer_supply v2m_eth_supplies[] = {
REGULATOR_SUPPLY("vddvario", "smsc911x"),
REGULATOR_SUPPLY("vdd33a", "smsc911x"),
};
static struct resource v2m_usb_resources[] = {
{
.start = V2M_ISP1761,
@ -319,98 +324,145 @@ static struct amba_device *v2m_amba_devs[] __initdata = {
};
static long v2m_osc_round(struct clk *clk, unsigned long rate)
static unsigned long v2m_osc_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct v2m_osc *osc = to_v2m_osc(hw);
return !parent_rate ? osc->rate_default : parent_rate;
}
static long v2m_osc_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct v2m_osc *osc = to_v2m_osc(hw);
if (WARN_ON(rate < osc->rate_min))
rate = osc->rate_min;
if (WARN_ON(rate > osc->rate_max))
rate = osc->rate_max;
return rate;
}
static int v2m_osc1_set(struct clk *clk, unsigned long rate)
static int v2m_osc_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_MB | 1, rate);
struct v2m_osc *osc = to_v2m_osc(hw);
v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(osc->site) |
SYS_CFG_STACK(osc->stack) | osc->osc, rate);
return 0;
}
static const struct clk_ops osc1_clk_ops = {
.round = v2m_osc_round,
.set = v2m_osc1_set,
static struct clk_ops v2m_osc_ops = {
.recalc_rate = v2m_osc_recalc_rate,
.round_rate = v2m_osc_round_rate,
.set_rate = v2m_osc_set_rate,
};
static struct clk osc1_clk = {
.ops = &osc1_clk_ops,
.rate = 24000000,
struct clk * __init v2m_osc_register(const char *name, struct v2m_osc *osc)
{
struct clk_init_data init;
WARN_ON(osc->site > 2);
WARN_ON(osc->stack > 15);
WARN_ON(osc->osc > 4095);
init.name = name;
init.ops = &v2m_osc_ops;
init.flags = CLK_IS_ROOT;
init.num_parents = 0;
osc->hw.init = &init;
return clk_register(NULL, &osc->hw);
}
static struct v2m_osc v2m_mb_osc1 = {
.site = SYS_CFG_SITE_MB,
.osc = 1,
.rate_min = 23750000,
.rate_max = 63500000,
.rate_default = 23750000,
};
static struct clk osc2_clk = {
.rate = 24000000,
static const char *v2m_ref_clk_periphs[] __initconst = {
"mb:wdt", "1000f000.wdt", "1c0f0000.wdt", /* SP805 WDT */
};
static struct clk v2m_sp804_clk = {
.rate = 1000000,
static const char *v2m_osc1_periphs[] __initconst = {
"mb:clcd", "1001f000.clcd", "1c1f0000.clcd", /* PL111 CLCD */
};
static struct clk v2m_ref_clk = {
.rate = 32768,
static const char *v2m_osc2_periphs[] __initconst = {
"mb:mmci", "10005000.mmci", "1c050000.mmci", /* PL180 MMCI */
"mb:kmi0", "10006000.kmi", "1c060000.kmi", /* PL050 KMI0 */
"mb:kmi1", "10007000.kmi", "1c070000.kmi", /* PL050 KMI1 */
"mb:uart0", "10009000.uart", "1c090000.uart", /* PL011 UART0 */
"mb:uart1", "1000a000.uart", "1c0a0000.uart", /* PL011 UART1 */
"mb:uart2", "1000b000.uart", "1c0b0000.uart", /* PL011 UART2 */
"mb:uart3", "1000c000.uart", "1c0c0000.uart", /* PL011 UART3 */
};
static struct clk dummy_apb_pclk;
static void __init v2m_clk_init(void)
{
struct clk *clk;
int i;
static struct clk_lookup v2m_lookups[] = {
{ /* AMBA bus clock */
.con_id = "apb_pclk",
.clk = &dummy_apb_pclk,
}, { /* UART0 */
.dev_id = "mb:uart0",
.clk = &osc2_clk,
}, { /* UART1 */
.dev_id = "mb:uart1",
.clk = &osc2_clk,
}, { /* UART2 */
.dev_id = "mb:uart2",
.clk = &osc2_clk,
}, { /* UART3 */
.dev_id = "mb:uart3",
.clk = &osc2_clk,
}, { /* KMI0 */
.dev_id = "mb:kmi0",
.clk = &osc2_clk,
}, { /* KMI1 */
.dev_id = "mb:kmi1",
.clk = &osc2_clk,
}, { /* MMC0 */
.dev_id = "mb:mmci",
.clk = &osc2_clk,
}, { /* CLCD */
.dev_id = "mb:clcd",
.clk = &osc1_clk,
}, { /* SP805 WDT */
.dev_id = "mb:wdt",
.clk = &v2m_ref_clk,
}, { /* SP804 timers */
.dev_id = "sp804",
.con_id = "v2m-timer0",
.clk = &v2m_sp804_clk,
}, { /* SP804 timers */
.dev_id = "sp804",
.con_id = "v2m-timer1",
.clk = &v2m_sp804_clk,
},
clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
CLK_IS_ROOT, 0);
WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));
clk = clk_register_fixed_rate(NULL, "mb:ref_clk", NULL,
CLK_IS_ROOT, 32768);
for (i = 0; i < ARRAY_SIZE(v2m_ref_clk_periphs); i++)
WARN_ON(clk_register_clkdev(clk, NULL, v2m_ref_clk_periphs[i]));
clk = clk_register_fixed_rate(NULL, "mb:sp804_clk", NULL,
CLK_IS_ROOT, 1000000);
WARN_ON(clk_register_clkdev(clk, "v2m-timer0", "sp804"));
WARN_ON(clk_register_clkdev(clk, "v2m-timer1", "sp804"));
clk = v2m_osc_register("mb:osc1", &v2m_mb_osc1);
for (i = 0; i < ARRAY_SIZE(v2m_osc1_periphs); i++)
WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc1_periphs[i]));
clk = clk_register_fixed_rate(NULL, "mb:osc2", NULL,
CLK_IS_ROOT, 24000000);
for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++)
WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i]));
}
static void __init v2m_timer_init(void)
{
v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
v2m_clk_init();
v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
}
static struct sys_timer v2m_timer = {
.init = v2m_timer_init,
};
static void __init v2m_init_early(void)
{
ct_desc->init_early();
clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
if (ct_desc->init_early)
ct_desc->init_early();
versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
}
static void v2m_power_off(void)
{
if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0))
if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
printk(KERN_EMERG "Unable to shutdown\n");
}
static void v2m_restart(char str, const char *cmd)
{
if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
printk(KERN_EMERG "Unable to reboot\n");
}
@ -458,6 +510,9 @@ static void __init v2m_init(void)
{
int i;
regulator_register_fixed(0, v2m_eth_supplies,
ARRAY_SIZE(v2m_eth_supplies));
platform_device_register(&v2m_pcie_i2c_device);
platform_device_register(&v2m_ddc_i2c_device);
platform_device_register(&v2m_flash_device);
@ -522,77 +577,6 @@ void __init v2m_dt_map_io(void)
#endif
}
static struct clk_lookup v2m_dt_lookups[] = {
{ /* AMBA bus clock */
.con_id = "apb_pclk",
.clk = &dummy_apb_pclk,
}, { /* SP804 timers */
.dev_id = "sp804",
.con_id = "v2m-timer0",
.clk = &v2m_sp804_clk,
}, { /* SP804 timers */
.dev_id = "sp804",
.con_id = "v2m-timer1",
.clk = &v2m_sp804_clk,
}, { /* PL180 MMCI */
.dev_id = "mb:mmci", /* 10005000.mmci */
.clk = &osc2_clk,
}, { /* PL050 KMI0 */
.dev_id = "10006000.kmi",
.clk = &osc2_clk,
}, { /* PL050 KMI1 */
.dev_id = "10007000.kmi",
.clk = &osc2_clk,
}, { /* PL011 UART0 */
.dev_id = "10009000.uart",
.clk = &osc2_clk,
}, { /* PL011 UART1 */
.dev_id = "1000a000.uart",
.clk = &osc2_clk,
}, { /* PL011 UART2 */
.dev_id = "1000b000.uart",
.clk = &osc2_clk,
}, { /* PL011 UART3 */
.dev_id = "1000c000.uart",
.clk = &osc2_clk,
}, { /* SP805 WDT */
.dev_id = "1000f000.wdt",
.clk = &v2m_ref_clk,
}, { /* PL111 CLCD */
.dev_id = "1001f000.clcd",
.clk = &osc1_clk,
},
/* RS1 memory map */
{ /* PL180 MMCI */
.dev_id = "mb:mmci", /* 1c050000.mmci */
.clk = &osc2_clk,
}, { /* PL050 KMI0 */
.dev_id = "1c060000.kmi",
.clk = &osc2_clk,
}, { /* PL050 KMI1 */
.dev_id = "1c070000.kmi",
.clk = &osc2_clk,
}, { /* PL011 UART0 */
.dev_id = "1c090000.uart",
.clk = &osc2_clk,
}, { /* PL011 UART1 */
.dev_id = "1c0a0000.uart",
.clk = &osc2_clk,
}, { /* PL011 UART2 */
.dev_id = "1c0b0000.uart",
.clk = &osc2_clk,
}, { /* PL011 UART3 */
.dev_id = "1c0c0000.uart",
.clk = &osc2_clk,
}, { /* SP805 WDT */
.dev_id = "1c0f0000.wdt",
.clk = &v2m_ref_clk,
}, { /* PL111 CLCD */
.dev_id = "1c1f0000.clcd",
.clk = &osc1_clk,
},
};
void __init v2m_dt_init_early(void)
{
struct device_node *node;
@ -605,8 +589,8 @@ void __init v2m_dt_init_early(void)
/* Confirm board type against DT property, if available */
if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ?
int site = v2m_get_master_site();
u32 id = readl(v2m_sysreg_base + (site == SYS_CFG_SITE_DB2 ?
V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
u32 hbi = id & SYS_PROCIDx_HBI_MASK;
@ -614,8 +598,6 @@ void __init v2m_dt_init_early(void)
pr_warning("vexpress: DT HBI (%x) is not matching "
"hardware (%x)!\n", dt_hbi, hbi);
}
clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
}
static struct of_device_id vexpress_irq_match[] __initdata = {
@ -637,6 +619,8 @@ static void __init v2m_dt_timer_init(void)
node = of_find_compatible_node(NULL, NULL, "arm,sp810");
v2m_sysctl_init(of_iomap(node, 0));
v2m_clk_init();
err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
if (WARN_ON(err))
return;

5
arch/arm/plat-mxc/devices/platform-mxc_rtc.c
View File

@ -20,6 +20,11 @@ const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst =
imx_mxc_rtc_data_entry_single(MX31);
#endif /* ifdef CONFIG_SOC_IMX31 */
#ifdef CONFIG_SOC_IMX35
const struct imx_mxc_rtc_data imx35_mxc_rtc_data __initconst =
imx_mxc_rtc_data_entry_single(MX35);
#endif /* ifdef CONFIG_SOC_IMX35 */
struct platform_device *__init imx_add_mxc_rtc(
const struct imx_mxc_rtc_data *data)
{

14
arch/arm/plat-mxc/include/mach/iomux-mx51.h
View File

@ -107,11 +107,13 @@
#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL)
#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL)
#define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D25__GPT_CMPOUT1 IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL)
#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL)
#define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D26__GPT_CMPOUT2 IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
@ -228,6 +230,7 @@
#define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_DRAM_CS1__CCM_CLKO IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
@ -256,12 +259,14 @@
#define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2 IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)
#define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3 IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
@ -637,7 +642,9 @@
#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN15__DI1_PIN15 IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL)
#define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL)
@ -780,6 +787,8 @@
#define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)
#define MX51_PAD_GPIO1_3__CCM_CLKO2 IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_3__GPT_CLKIN IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL)
@ -788,13 +797,16 @@
#define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_4__GPT_CAPIN1 IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_5__CCM_CLKO IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_6__GPT_CAPIN2 IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
@ -803,11 +815,13 @@
#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
#define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_8__CCM_CLKO2 IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_9__CCM_CLKO IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL)
#endif /* __MACH_IOMUX_MX51_H__ */

14
arch/arm/plat-mxc/include/mach/mxc_ehci.h
View File

@ -20,13 +20,15 @@
#define MXC_EHCI_INTERFACE_MASK (0xf)
#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
#define MXC_EHCI_TTL_ENABLED (1 << 6)
#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
#define MXC_EHCI_TTL_ENABLED (1 << 8)
#define MXC_EHCI_INTERNAL_PHY (1 << 7)
#define MXC_EHCI_IPPUE_DOWN (1 << 8)
#define MXC_EHCI_IPPUE_UP (1 << 9)
#define MXC_EHCI_WAKEUP_ENABLED (1 << 10)
#define MXC_EHCI_ITC_NO_THRESHOLD (1 << 11)
#define MXC_EHCI_INTERNAL_PHY (1 << 9)
#define MXC_EHCI_IPPUE_DOWN (1 << 10)
#define MXC_EHCI_IPPUE_UP (1 << 11)
#define MXC_EHCI_WAKEUP_ENABLED (1 << 12)
#define MXC_EHCI_ITC_NO_THRESHOLD (1 << 13)
#define MXC_USBCTRL_OFFSET 0
#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8

4
arch/arm/plat-omap/include/plat/serial.h
View File

@ -60,6 +60,9 @@
/* AM3505/3517 UART4 */
#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
/* AM33XX serial port */
#define AM33XX_UART1_BASE 0x44E09000
/* External port on Zoom2/3 */
#define ZOOM_UART_BASE 0x10000000
#define ZOOM_UART_VIRT 0xfa400000
@ -93,6 +96,7 @@
#define TI81XXUART1 81
#define TI81XXUART2 82
#define TI81XXUART3 83
#define AM33XXUART1 84
#define ZOOM_UART 95 /* Only on zoom2/3 */
/* This is only used by 8250.c for omap1510 */

6
arch/arm/plat-omap/include/plat/uncompress.h
View File

@ -103,6 +103,10 @@ static inline void flush(void)
_DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
TI81XXUART##p)
#define DEBUG_LL_AM33XX(p, mach) \
_DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
AM33XXUART##p)
static inline void __arch_decomp_setup(unsigned long arch_id)
{
int port = 0;
@ -183,6 +187,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
/* TI8148 base boards using UART1 */
DEBUG_LL_TI81XX(1, ti8148evm);
/* AM33XX base boards using UART1 */
DEBUG_LL_AM33XX(1, am335xevm);
} while (0);
}

4
arch/arm/plat-samsung/Kconfig
View File

@ -78,6 +78,10 @@ config S5P_HRT
# clock options
config SAMSUNG_CLOCK
bool
default y if !COMMON_CLK
config SAMSUNG_CLKSRC
bool
help

4
arch/arm/plat-samsung/Makefile
View File

@ -15,8 +15,8 @@ obj-y += init.o cpu.o
obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o
obj-$(CONFIG_S5P_HRT) += s5p-time.o
obj-y += clock.o
obj-y += pwm-clock.o
obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o
obj-$(CONFIG_SAMSUNG_CLOCK) += pwm-clock.o
obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o

4
arch/arm/plat-samsung/include/plat/cpu.h
View File

@ -132,6 +132,10 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
#ifndef KHZ
#define KHZ (1000)
#endif
#ifndef MHZ
#define MHZ (1000*1000)
#endif

3
arch/arm/plat-versatile/Kconfig
View File

@ -1,5 +1,8 @@
if PLAT_VERSATILE
config PLAT_VERSATILE_CLOCK
bool
config PLAT_VERSATILE_CLCD
bool

2
arch/arm/plat-versatile/Makefile
View File

@ -1,4 +1,4 @@
obj-y := clock.o
obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o

1
drivers/clk/Makefile
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@ -3,5 +3,6 @@ obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
clk-mux.o clk-divider.o clk-fixed-factor.o
# SoCs specific
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
obj-$(CONFIG_ARCH_MXS) += mxs/
obj-$(CONFIG_PLAT_SPEAR) += spear/

47
drivers/clk/clk-nomadik.c Normal file
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@ -0,0 +1,47 @@
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk-provider.h>
/*
* The Nomadik clock tree is described in the STN8815A12 DB V4.2
* reference manual for the chip, page 94 ff.
*/
void __init nomadik_clk_init(void)
{
struct clk *clk;
clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
clk_register_clkdev(clk, "apb_pclk", NULL);
clk_register_clkdev(clk, NULL, "gpio.0");
clk_register_clkdev(clk, NULL, "gpio.1");
clk_register_clkdev(clk, NULL, "gpio.2");
clk_register_clkdev(clk, NULL, "gpio.3");
clk_register_clkdev(clk, NULL, "rng");
/*
* The 2.4 MHz TIMCLK reference clock is active at boot time, this is
* actually the MXTALCLK @19.2 MHz divided by 8. This clock is used
* by the timers and watchdog. See page 105 ff.
*/
clk = clk_register_fixed_rate(NULL, "TIMCLK", NULL, CLK_IS_ROOT,
2400000);
clk_register_clkdev(clk, NULL, "mtu0");
clk_register_clkdev(clk, NULL, "mtu1");
/*
* At boot time, PLL2 is set to generate a set of fixed clocks,
* one of them is CLK48, the 48 MHz clock, routed to the UART, MMC/SD
* I2C, IrDA, USB and SSP blocks.
*/
clk = clk_register_fixed_rate(NULL, "CLK48", NULL, CLK_IS_ROOT,
48000000);
clk_register_clkdev(clk, NULL, "uart0");
clk_register_clkdev(clk, NULL, "uart1");
clk_register_clkdev(clk, NULL, "mmci");
clk_register_clkdev(clk, NULL, "ssp");
clk_register_clkdev(clk, NULL, "nmk-i2c.0");
clk_register_clkdev(clk, NULL, "nmk-i2c.1");
}

2
include/linux/platform_data/clk-nomadik.h Normal file
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@ -0,0 +1,2 @@
/* Minimal platform data header */
void nomadik_clk_init(void);