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ASoC: SOF: updates for 5.18
Merge series from Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>: A couple of updates for Intel and AMD hardware, along with minor cleanups Ajit Kumar Pandey (4): ASoC: SOF: amd: Flush cache after ATU_BASE_ADDR_GRP register update ASoC: SOF: amd: Use semaphore register to synchronize ipc's irq ASoC: SOF: amd: Move group register configuration to acp-loader ASoC: SOF: amd: Increase ACP_HW_SEM_RETRY_COUNT value Curtis Malainey (1): ASoC: SOF: fix 32 signed bit overflow Gongjun Song (1): ASoC: SOF: Intel: pci-tgl: add RPL-S support Peter Ujfalusi (2): ASoC: SOF: amd: acp-pcm: Take buffer information directly from runtime ASoC: SOF: amd: Do not set ipc_pcm_params ops as it is optional Pierre-Louis Bossart (2): ASoC: SOF: debug: clarify operator precedence ASoC: SOF: Intel: hda: clarify operator precedence include/sound/sof/header.h | 2 +- include/uapi/sound/sof/abi.h | 2 +- sound/soc/sof/amd/acp-dsp-offset.h | 1 + sound/soc/sof/amd/acp-ipc.c | 22 ++++++++++++++-------- sound/soc/sof/amd/acp-loader.c | 9 +++++++++ sound/soc/sof/amd/acp-pcm.c | 7 ++++--- sound/soc/sof/amd/acp-stream.c | 3 +++ sound/soc/sof/amd/acp.c | 29 ++++++++++++++--------------- sound/soc/sof/amd/acp.h | 3 +-- sound/soc/sof/amd/renoir.c | 1 - sound/soc/sof/debug.c | 2 +- sound/soc/sof/intel/hda.c | 2 +- sound/soc/sof/intel/pci-tgl.c | 2 ++ 13 files changed, 52 insertions(+), 33 deletions(-) -- 2.30.2
This commit is contained in:
commit
5e36946abc
@ -31,7 +31,7 @@
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/* Global Message - Generic */
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#define SOF_GLB_TYPE_SHIFT 28
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#define SOF_GLB_TYPE_MASK (0xfL << SOF_GLB_TYPE_SHIFT)
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#define SOF_GLB_TYPE_MASK (0xfUL << SOF_GLB_TYPE_SHIFT)
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#define SOF_GLB_TYPE(x) ((x) << SOF_GLB_TYPE_SHIFT)
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/* Command Message - Generic */
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@ -27,7 +27,7 @@
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/* SOF ABI version major, minor and patch numbers */
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#define SOF_ABI_MAJOR 3
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#define SOF_ABI_MINOR 19
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#define SOF_ABI_PATCH 0
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#define SOF_ABI_PATCH 1
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/* SOF ABI version number. Format within 32bit word is MMmmmppp */
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#define SOF_ABI_MAJOR_SHIFT 24
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@ -61,6 +61,7 @@
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#define ACP_DSP_SW_INTR_STAT 0x1818
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#define ACP_SW_INTR_TRIG 0x181C
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#define ACP_ERROR_STATUS 0x18C4
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#define ACP_AXI2DAGB_SEM_0 0x1880
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/* Registers from ACP_SHA block */
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#define ACP_SHA_DSP_FW_QUALIFIER 0x1C70
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@ -62,12 +62,26 @@ int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
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{
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struct acp_dev_data *adata = sdev->pdata->hw_pdata;
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unsigned int offset = offsetof(struct scratch_ipc_conf, sof_in_box);
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unsigned int count = ACP_HW_SEM_RETRY_COUNT;
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while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_AXI2DAGB_SEM_0)) {
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/* Wait until acquired HW Semaphore Lock or timeout*/
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count--;
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if (!count) {
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dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);
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return -EINVAL;
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}
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};
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acp_mailbox_write(sdev, offset, msg->msg_data, msg->msg_size);
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acp_ipc_host_msg_set(sdev);
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/* Trigger host to dsp interrupt for the msg */
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acpbus_trigger_host_to_dsp_swintr(adata);
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/* Unlock or Release HW Semaphore */
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_AXI2DAGB_SEM_0, 0x0);
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return 0;
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}
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EXPORT_SYMBOL_NS(acp_sof_ipc_send_msg, SND_SOC_SOF_AMD_COMMON);
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@ -170,14 +184,6 @@ int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_pcm_substream *sub
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}
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EXPORT_SYMBOL_NS(acp_sof_ipc_msg_data, SND_SOC_SOF_AMD_COMMON);
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int acp_sof_ipc_pcm_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
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const struct sof_ipc_pcm_params_reply *reply)
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{
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/* TODO: Implement stream hw params to validate stream offset */
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return 0;
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}
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EXPORT_SYMBOL_NS(acp_sof_ipc_pcm_params, SND_SOC_SOF_AMD_COMMON);
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int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev)
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{
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return ACP_SCRATCH_MEMORY_ADDRESS;
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@ -127,6 +127,12 @@ static void configure_pte_for_fw_loading(int type, int num_pages, struct acp_dev
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return;
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}
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/* Group Enable */
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_BASE_ADDR_GRP_1,
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ACP_SRAM_PTE_OFFSET | BIT(31));
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1,
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PAGE_SIZE_4K_ENABLE);
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for (page_idx = 0; page_idx < num_pages; page_idx++) {
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low = lower_32_bits(addr);
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high = upper_32_bits(addr);
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@ -136,6 +142,9 @@ static void configure_pte_for_fw_loading(int type, int num_pages, struct acp_dev
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offset += 8;
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addr += PAGE_SIZE;
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}
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/* Flush ATU Cache after PTE Update */
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_CTRL, ACP_ATU_CACHE_INVALID);
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}
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/* pre fw run operations */
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@ -19,13 +19,14 @@
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int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params, struct sof_ipc_stream_params *ipc_params)
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{
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struct acp_dsp_stream *stream = substream->runtime->private_data;
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct acp_dsp_stream *stream = runtime->private_data;
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unsigned int buf_offset, index;
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u32 size;
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int ret;
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size = ipc_params->buffer.size;
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stream->num_pages = ipc_params->buffer.pages;
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size = runtime->dma_bytes;
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stream->num_pages = PFN_UP(runtime->dma_bytes);
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stream->dmab = substream->runtime->dma_buffer_p;
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ret = acp_dsp_stream_config(sdev, stream);
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@ -115,6 +115,9 @@ int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *strea
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offset += 8;
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}
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/* Flush ATU Cache after PTE Update */
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_CTRL, ACP_ATU_CACHE_INVALID);
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return 0;
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}
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@ -36,19 +36,6 @@ static int smn_read(struct pci_dev *dev, u32 smn_addr, u32 *data)
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return 0;
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}
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static void configure_acp_groupregisters(struct acp_dev_data *adata)
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{
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struct snd_sof_dev *sdev = adata->dev;
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/* Group Enable */
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_BASE_ADDR_GRP_1,
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ACP_SRAM_PTE_OFFSET | BIT(31));
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1,
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PAGE_SIZE_4K_ENABLE);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACPAXI2AXI_ATU_CTRL, ACP_ATU_CACHE_INVALID);
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}
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static void init_dma_descriptor(struct acp_dev_data *adata)
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{
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struct snd_sof_dev *sdev = adata->dev;
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@ -264,7 +251,6 @@ static int acp_memory_init(struct snd_sof_dev *sdev)
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snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, ACP_DSP_SW_INTR_CNTL,
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ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK);
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configure_acp_groupregisters(adata);
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init_dma_descriptor(adata);
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return 0;
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@ -273,7 +259,7 @@ static int acp_memory_init(struct snd_sof_dev *sdev)
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static irqreturn_t acp_irq_thread(int irq, void *context)
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{
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struct snd_sof_dev *sdev = context;
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unsigned int val;
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unsigned int val, count = ACP_HW_SEM_RETRY_COUNT;
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val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_EXTERNAL_INTR_STAT);
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if (val & ACP_SHA_STAT) {
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@ -284,9 +270,22 @@ static irqreturn_t acp_irq_thread(int irq, void *context)
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val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DSP_SW_INTR_STAT);
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if (val & ACP_DSP_TO_HOST_IRQ) {
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while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_AXI2DAGB_SEM_0)) {
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/* Wait until acquired HW Semaphore lock or timeout */
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count--;
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if (!count) {
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dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);
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return IRQ_NONE;
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}
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};
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sof_ops(sdev)->irq_thread(irq, sdev);
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val |= ACP_DSP_TO_HOST_IRQ;
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP_SW_INTR_STAT, val);
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/* Unlock or Release HW Semaphore */
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_AXI2DAGB_SEM_0, 0x0);
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return IRQ_HANDLED;
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}
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@ -17,6 +17,7 @@
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#define ACP_DSP_BAR 0
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#define ACP_HW_SEM_RETRY_COUNT 10000
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#define ACP_REG_POLL_INTERVAL 500
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#define ACP_REG_POLL_TIMEOUT_US 2000
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#define ACP_DMA_COMPLETE_TIMEOUT_US 5000
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@ -185,8 +186,6 @@ int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev,
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struct snd_sof_ipc_msg *msg);
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int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
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int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
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int acp_sof_ipc_pcm_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
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const struct sof_ipc_pcm_params_reply *reply);
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void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
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void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
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@ -150,7 +150,6 @@ const struct snd_sof_dsp_ops sof_renoir_ops = {
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/*IPC */
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.send_msg = acp_sof_ipc_send_msg,
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.ipc_msg_data = acp_sof_ipc_msg_data,
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.ipc_pcm_params = acp_sof_ipc_pcm_params,
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.get_mailbox_offset = acp_sof_ipc_get_mailbox_offset,
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.irq_thread = acp_sof_ipc_irq_thread,
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.fw_ready = sof_fw_ready,
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@ -395,7 +395,7 @@ static void snd_sof_dbg_print_fw_state(struct snd_sof_dev *sdev, const char *lev
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void snd_sof_dsp_dbg_dump(struct snd_sof_dev *sdev, const char *msg, u32 flags)
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{
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char *level = flags & SOF_DBG_DUMP_OPTIONAL ? KERN_DEBUG : KERN_ERR;
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char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
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bool print_all = sof_debug_check_flag(SOF_DBG_PRINT_ALL_DUMPS);
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if (flags & SOF_DBG_DUMP_OPTIONAL && !print_all)
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@ -534,7 +534,7 @@ static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *le
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void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
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{
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char *level = flags & SOF_DBG_DUMP_OPTIONAL ? KERN_DEBUG : KERN_ERR;
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char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
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struct sof_ipc_dsp_oops_xtensa xoops;
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struct sof_ipc_panic_info panic_info;
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u32 stack[HDA_DSP_STACK_DUMP_SIZE];
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@ -110,6 +110,8 @@ static const struct pci_device_id sof_pci_ids[] = {
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.driver_data = (unsigned long)&ehl_desc},
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{ PCI_DEVICE(0x8086, 0x7ad0), /* ADL-S */
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.driver_data = (unsigned long)&adls_desc},
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{ PCI_DEVICE(0x8086, 0x7a50), /* RPL-S */
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.driver_data = (unsigned long)&adls_desc},
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{ PCI_DEVICE(0x8086, 0x51c8), /* ADL-P */
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.driver_data = (unsigned long)&adl_desc},
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{ PCI_DEVICE(0x8086, 0x51cd), /* ADL-P */
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