korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-12-19 09:04:51 +08:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'net-add-phylink-support-for-PCS'

Browse Source 
Russell King says:

====================
net: add phylink support for PCS

This series adds support for IEEE 802.3 register set compliant PCS
for phylink.  In order to do this, we:

1. convert BUG_ON() in existing accessors to WARN_ON_ONCE() and return
   an error.
2. add accessors for modifying a MDIO device register, and use them in
   phylib, rather than duplicating the code from phylib.
3. add support for decoding the advertisement from clause 22 compatible
   register sets for clause 37 advertisements and SGMII advertisements.
4. add support for clause 45 register sets for 10GBASE-R PCS.

These have been tested on the LX2160A Clearfog-CX platform.

v2: eliminate use of BUG_ON() in the accessors.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2020-03-17 22:51:16 -07:00
commit 5dd3284526
7 changed files with 336 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

68
drivers/net/phy/mdio_bus.c
View File

@ -824,6 +824,38 @@ int __mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val)
}
EXPORT_SYMBOL(__mdiobus_write);
/**
* __mdiobus_modify_changed - Unlocked version of the mdiobus_modify function
* @bus: the mii_bus struct
* @addr: the phy address
* @regnum: register number to modify
* @mask: bit mask of bits to clear
* @set: bit mask of bits to set
*
* Read, modify, and if any change, write the register value back to the
* device. Any error returns a negative number.
*
* NOTE: MUST NOT be called from interrupt context.
*/
int __mdiobus_modify_changed(struct mii_bus *bus, int addr, u32 regnum,
u16 mask, u16 set)
{
int new, ret;
ret = __mdiobus_read(bus, addr, regnum);
if (ret < 0)
return ret;
new = (ret & ~mask) | set;
if (new == ret)
return 0;
ret = __mdiobus_write(bus, addr, regnum, new);
return ret < 0 ? ret : 1;
}
EXPORT_SYMBOL_GPL(__mdiobus_modify_changed);
/**
* mdiobus_read_nested - Nested version of the mdiobus_read function
* @bus: the mii_bus struct
@ -841,7 +873,8 @@ int mdiobus_read_nested(struct mii_bus *bus, int addr, u32 regnum)
{
int retval;
BUG_ON(in_interrupt());
if (WARN_ON_ONCE(in_interrupt()))
return -EINVAL;
mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
retval = __mdiobus_read(bus, addr, regnum);
@ -865,7 +898,8 @@ int mdiobus_read(struct mii_bus *bus, int addr, u32 regnum)
{
int retval;
BUG_ON(in_interrupt());
if (WARN_ON_ONCE(in_interrupt()))
return -EINVAL;
mutex_lock(&bus->mdio_lock);
retval = __mdiobus_read(bus, addr, regnum);
@ -893,7 +927,8 @@ int mdiobus_write_nested(struct mii_bus *bus, int addr, u32 regnum, u16 val)
{
int err;
BUG_ON(in_interrupt());
if (WARN_ON_ONCE(in_interrupt()))
return -EINVAL;
mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
err = __mdiobus_write(bus, addr, regnum, val);
@ -918,7 +953,8 @@ int mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val)
{
int err;
BUG_ON(in_interrupt());
if (WARN_ON_ONCE(in_interrupt()))
return -EINVAL;
mutex_lock(&bus->mdio_lock);
err = __mdiobus_write(bus, addr, regnum, val);
@ -928,6 +964,30 @@ int mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val)
}
EXPORT_SYMBOL(mdiobus_write);
/**
* mdiobus_modify - Convenience function for modifying a given mdio device
* register
* @bus: the mii_bus struct
* @addr: the phy address
* @regnum: register number to write
* @mask: bit mask of bits to clear
* @set: bit mask of bits to set
*/
int mdiobus_modify(struct mii_bus *bus, int addr, u32 regnum, u16 mask, u16 set)
{
int err;
if (WARN_ON_ONCE(in_interrupt()))
return -EINVAL;
mutex_lock(&bus->mdio_lock);
err = __mdiobus_modify_changed(bus, addr, regnum, mask, set);
mutex_unlock(&bus->mdio_lock);
return err < 0 ? err : 0;
}
EXPORT_SYMBOL_GPL(mdiobus_modify);
/**
* mdio_bus_match - determine if given MDIO driver supports the given
* MDIO device

31
drivers/net/phy/phy-core.c
View File

@ -488,37 +488,6 @@ int phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)
}
EXPORT_SYMBOL(phy_write_mmd);
/**
* __phy_modify_changed() - Convenience function for modifying a PHY register
* @phydev: a pointer to a &struct phy_device
* @regnum: register number
* @mask: bit mask of bits to clear
* @set: bit mask of bits to set
*
* Unlocked helper function which allows a PHY register to be modified as
* new register value = (old register value & ~mask) | set
*
* Returns negative errno, 0 if there was no change, and 1 in case of change
*/
int __phy_modify_changed(struct phy_device *phydev, u32 regnum, u16 mask,
u16 set)
{
int new, ret;
ret = __phy_read(phydev, regnum);
if (ret < 0)
return ret;
new = (ret & ~mask) | set;
if (new == ret)
return 0;
ret = __phy_write(phydev, regnum, new);
return ret < 0 ? ret : 1;
}
EXPORT_SYMBOL_GPL(__phy_modify_changed);
/**
* phy_modify_changed - Function for modifying a PHY register
* @phydev: the phy_device struct

236
drivers/net/phy/phylink.c
View File

@ -2068,4 +2068,240 @@ void phylink_helper_basex_speed(struct phylink_link_state *state)
}
EXPORT_SYMBOL_GPL(phylink_helper_basex_speed);
static void phylink_decode_c37_word(struct phylink_link_state *state,
uint16_t config_reg, int speed)
{
bool tx_pause, rx_pause;
int fd_bit;
if (speed == SPEED_2500)
fd_bit = ETHTOOL_LINK_MODE_2500baseX_Full_BIT;
else
fd_bit = ETHTOOL_LINK_MODE_1000baseX_Full_BIT;
mii_lpa_mod_linkmode_x(state->lp_advertising, config_reg, fd_bit);
if (linkmode_test_bit(fd_bit, state->advertising) &&
linkmode_test_bit(fd_bit, state->lp_advertising)) {
state->speed = speed;
state->duplex = DUPLEX_FULL;
} else {
/* negotiation failure */
state->link = false;
}
linkmode_resolve_pause(state->advertising, state->lp_advertising,
&tx_pause, &rx_pause);
if (tx_pause)
state->pause |= MLO_PAUSE_TX;
if (rx_pause)
state->pause |= MLO_PAUSE_RX;
}
static void phylink_decode_sgmii_word(struct phylink_link_state *state,
uint16_t config_reg)
{
if (!(config_reg & LPA_SGMII_LINK)) {
state->link = false;
return;
}
switch (config_reg & LPA_SGMII_SPD_MASK) {
case LPA_SGMII_10:
state->speed = SPEED_10;
break;
case LPA_SGMII_100:
state->speed = SPEED_100;
break;
case LPA_SGMII_1000:
state->speed = SPEED_1000;
break;
default:
state->link = false;
return;
}
if (config_reg & LPA_SGMII_FULL_DUPLEX)
state->duplex = DUPLEX_FULL;
else
state->duplex = DUPLEX_HALF;
}
/**
* phylink_mii_c22_pcs_get_state() - read the MAC PCS state
* @pcs: a pointer to a &struct mdio_device.
* @state: a pointer to a &struct phylink_link_state.
*
* Helper for MAC PCS supporting the 802.3 clause 22 register set for
* clause 37 negotiation and/or SGMII control.
*
* Read the MAC PCS state from the MII device configured in @config and
* parse the Clause 37 or Cisco SGMII link partner negotiation word into
* the phylink @state structure. This is suitable to be directly plugged
* into the mac_pcs_get_state() member of the struct phylink_mac_ops
* structure.
*/
void phylink_mii_c22_pcs_get_state(struct mdio_device *pcs,
struct phylink_link_state *state)
{
struct mii_bus *bus = pcs->bus;
int addr = pcs->addr;
int bmsr, lpa;
bmsr = mdiobus_read(bus, addr, MII_BMSR);
lpa = mdiobus_read(bus, addr, MII_LPA);
if (bmsr < 0 || lpa < 0) {
state->link = false;
return;
}
state->link = !!(bmsr & BMSR_LSTATUS);
state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);
if (!state->link)
return;
switch (state->interface) {
case PHY_INTERFACE_MODE_1000BASEX:
phylink_decode_c37_word(state, lpa, SPEED_1000);
break;
case PHY_INTERFACE_MODE_2500BASEX:
phylink_decode_c37_word(state, lpa, SPEED_2500);
break;
case PHY_INTERFACE_MODE_SGMII:
phylink_decode_sgmii_word(state, lpa);
break;
default:
state->link = false;
break;
}
}
EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_get_state);
/**
* phylink_mii_c22_pcs_set_advertisement() - configure the clause 37 PCS
* advertisement
* @pcs: a pointer to a &struct mdio_device.
* @state: a pointer to the state being configured.
*
* Helper for MAC PCS supporting the 802.3 clause 22 register set for
* clause 37 negotiation and/or SGMII control.
*
* Configure the clause 37 PCS advertisement as specified by @state. This
* does not trigger a renegotiation; phylink will do that via the
* mac_an_restart() method of the struct phylink_mac_ops structure.
*
* Returns negative error code on failure to configure the advertisement,
* zero if no change has been made, or one if the advertisement has changed.
*/
int phylink_mii_c22_pcs_set_advertisement(struct mdio_device *pcs,
const struct phylink_link_state *state)
{
struct mii_bus *bus = pcs->bus;
int addr = pcs->addr;
int val, ret;
u16 adv;
switch (state->interface) {
case PHY_INTERFACE_MODE_1000BASEX:
case PHY_INTERFACE_MODE_2500BASEX:
adv = ADVERTISE_1000XFULL;
if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
state->advertising))
adv |= ADVERTISE_1000XPAUSE;
if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
state->advertising))
adv |= ADVERTISE_1000XPSE_ASYM;
val = mdiobus_read(bus, addr, MII_ADVERTISE);
if (val < 0)
return val;
if (val == adv)
return 0;
ret = mdiobus_write(bus, addr, MII_ADVERTISE, adv);
if (ret < 0)
return ret;
return 1;
case PHY_INTERFACE_MODE_SGMII:
val = mdiobus_read(bus, addr, MII_ADVERTISE);
if (val < 0)
return val;
if (val == 0x0001)
return 0;
ret = mdiobus_write(bus, addr, MII_ADVERTISE, 0x0001);
if (ret < 0)
return ret;
return 1;
default:
/* Nothing to do for other modes */
return 0;
}
}
EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_set_advertisement);
/**
* phylink_mii_c22_pcs_an_restart() - restart 802.3z autonegotiation
* @pcs: a pointer to a &struct mdio_device.
*
* Helper for MAC PCS supporting the 802.3 clause 22 register set for
* clause 37 negotiation.
*
* Restart the clause 37 negotiation with the link partner. This is
* suitable to be directly plugged into the mac_pcs_get_state() member
* of the struct phylink_mac_ops structure.
*/
void phylink_mii_c22_pcs_an_restart(struct mdio_device *pcs)
{
struct mii_bus *bus = pcs->bus;
int val, addr = pcs->addr;
val = mdiobus_read(bus, addr, MII_BMCR);
if (val >= 0) {
val |= BMCR_ANRESTART;
mdiobus_write(bus, addr, MII_BMCR, val);
}
}
EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_an_restart);
#define C45_ADDR(d,a) (MII_ADDR_C45 | (d) << 16 | (a))
void phylink_mii_c45_pcs_get_state(struct mdio_device *pcs,
struct phylink_link_state *state)
{
struct mii_bus *bus = pcs->bus;
int addr = pcs->addr;
int stat;
stat = mdiobus_read(bus, addr, C45_ADDR(MDIO_MMD_PCS, MDIO_STAT1));
if (stat < 0) {
state->link = false;
return;
}
state->link = !!(stat & MDIO_STAT1_LSTATUS);
if (!state->link)
return;
switch (state->interface) {
case PHY_INTERFACE_MODE_10GBASER:
state->speed = SPEED_10000;
state->duplex = DUPLEX_FULL;
break;
default:
break;
}
}
EXPORT_SYMBOL_GPL(phylink_mii_c45_pcs_get_state);
MODULE_LICENSE("GPL v2");

4
include/linux/mdio.h
View File

@ -316,11 +316,15 @@ static inline void mii_10gbt_stat_mod_linkmode_lpa_t(unsigned long *advertising,
int __mdiobus_read(struct mii_bus *bus, int addr, u32 regnum);
int __mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val);
int __mdiobus_modify_changed(struct mii_bus *bus, int addr, u32 regnum,
u16 mask, u16 set);
int mdiobus_read(struct mii_bus *bus, int addr, u32 regnum);
int mdiobus_read_nested(struct mii_bus *bus, int addr, u32 regnum);
int mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val);
int mdiobus_write_nested(struct mii_bus *bus, int addr, u32 regnum, u16 val);
int mdiobus_modify(struct mii_bus *bus, int addr, u32 regnum, u16 mask,
u16 set);
int mdiobus_register_device(struct mdio_device *mdiodev);
int mdiobus_unregister_device(struct mdio_device *mdiodev);

19
include/linux/phy.h
View File

@ -754,6 +754,25 @@ static inline int __phy_write(struct phy_device *phydev, u32 regnum, u16 val)
val);
}
/**
* __phy_modify_changed() - Convenience function for modifying a PHY register
* @phydev: a pointer to a &struct phy_device
* @regnum: register number
* @mask: bit mask of bits to clear
* @set: bit mask of bits to set
*
* Unlocked helper function which allows a PHY register to be modified as
* new register value = (old register value & ~mask) | set
*
* Returns negative errno, 0 if there was no change, and 1 in case of change
*/
static inline int __phy_modify_changed(struct phy_device *phydev, u32 regnum,
u16 mask, u16 set)
{
return __mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr,
regnum, mask, set);
}
/**
* phy_read_mmd - Convenience function for reading a register
* from an MMD on a given PHY.

8
include/linux/phylink.h
View File

@ -317,4 +317,12 @@ int phylink_mii_ioctl(struct phylink *, struct ifreq *, int);
void phylink_set_port_modes(unsigned long *bits);
void phylink_helper_basex_speed(struct phylink_link_state *state);
void phylink_mii_c22_pcs_get_state(struct mdio_device *pcs,
struct phylink_link_state *state);
int phylink_mii_c22_pcs_set_advertisement(struct mdio_device *pcs,
const struct phylink_link_state *state);
void phylink_mii_c22_pcs_an_restart(struct mdio_device *pcs);
void phylink_mii_c45_pcs_get_state(struct mdio_device *pcs,
struct phylink_link_state *state);
#endif

5
include/uapi/linux/mii.h
View File

@ -134,11 +134,16 @@
/* MAC and PHY tx_config_Reg[15:0] for SGMII in-band auto-negotiation.*/
#define ADVERTISE_SGMII 0x0001 /* MAC can do SGMII */
#define LPA_SGMII 0x0001 /* PHY can do SGMII */
#define LPA_SGMII_SPD_MASK 0x0c00 /* SGMII speed mask */
#define LPA_SGMII_FULL_DUPLEX 0x1000 /* SGMII full duplex */
#define LPA_SGMII_DPX_SPD_MASK 0x1C00 /* SGMII duplex and speed bits */
#define LPA_SGMII_10 0x0000 /* 10Mbps */
#define LPA_SGMII_10HALF 0x0000 /* Can do 10mbps half-duplex */
#define LPA_SGMII_10FULL 0x1000 /* Can do 10mbps full-duplex */
#define LPA_SGMII_100 0x0400 /* 100Mbps */
#define LPA_SGMII_100HALF 0x0400 /* Can do 100mbps half-duplex */
#define LPA_SGMII_100FULL 0x1400 /* Can do 100mbps full-duplex */
#define LPA_SGMII_1000 0x0800 /* 1000Mbps */
#define LPA_SGMII_1000HALF 0x0800 /* Can do 1000mbps half-duplex */
#define LPA_SGMII_1000FULL 0x1800 /* Can do 1000mbps full-duplex */
#define LPA_SGMII_LINK 0x8000 /* PHY link with copper-side partner */