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[Blackfin] arch: merge ip0x-specific board changes
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Mike Frysinger
Bryan Wu
parent
f950f605b9
commit
5d1617b247
@ -249,7 +249,7 @@ config MEM_MT48LC8M32B2B5_7
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config MEM_MT48LC32M16A2TG_75
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bool
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depends on (BFIN527_EZKIT)
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depends on (BFIN527_EZKIT || BFIN532_IP0X)
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default y
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source "arch/blackfin/mach-bf527/Kconfig"
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@ -281,6 +281,7 @@ config CLKIN_HZ
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default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
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default "30000000" if BFIN561_EZKIT
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default "24576000" if PNAV10
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default "10000000" if BFIN532_IP0X
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help
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The frequency of CLKIN crystal oscillator on the board in Hz.
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@ -304,6 +305,7 @@ config MEM_ADD_WIDTH
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default 10 if BFIN537_STAMP
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default 11 if BFIN533_STAMP
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default 10 if PNAV10
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default 10 if BFIN532_IP0X
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config PLL_BYPASS
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bool "Bypass PLL"
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@ -450,6 +452,7 @@ config MEM_SIZE
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default 64 if PNAV10
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default 32 if H8606_HVSISTEMAS
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default 64 if BFIN548_BLUETECHNIX_CM
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default 64 if BFIN532_IP0X
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choice
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prompt "DDR SDRAM Chip Type"
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1252
arch/blackfin/configs/IP0X_defconfig
Normal file
1252
arch/blackfin/configs/IP0X_defconfig
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File diff suppressed because it is too large
Load Diff
@ -26,6 +26,12 @@ config H8606_HVSISTEMAS
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help
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HV Sistemas H8606 board support.
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config BFIN532_IP0X
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bool "IP04/IP08 IP-PBX"
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depends on (BF532)
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help
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Core support for IP04/IP04 open hardware IP-PBX.
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config GENERIC_BF533_BOARD
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bool "Generic"
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help
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@ -4,6 +4,7 @@
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obj-$(CONFIG_GENERIC_BF533_BOARD) += generic_board.o
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obj-$(CONFIG_BFIN533_STAMP) += stamp.o
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obj-$(CONFIG_BFIN532_IP0X) += ip0x.o
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obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o
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obj-$(CONFIG_BFIN533_BLUETECHNIX_CM) += cm_bf533.o
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obj-$(CONFIG_H8606_HVSISTEMAS) += H8606.o
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279
arch/blackfin/mach-bf533/boards/ip0x.c
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279
arch/blackfin/mach-bf533/boards/ip0x.c
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@ -0,0 +1,279 @@
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/*
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* File: arch/blackfin/mach-bf533/ip0x.c
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* Based on: arch/blackfin/mach-bf533/bf1.c
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* Based on: arch/blackfin/mach-bf533/stamp.c
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* Author: Ivan Danov <idanov@gmail.com>
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* Modified for IP0X David Rowe
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*
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* Created: 2007
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* Description: Board info file for the IP04/IP08 boards, which
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* are derived from the BlackfinOne V2.0 boards.
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*
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* Modified:
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* COpyright 2007 David Rowe
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* Copyright 2006 Intratrade Ltd.
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* Copyright 2005 National ICT Australia (NICTA)
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* Copyright 2004-2006 Analog Devices Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
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#include <linux/usb/isp1362.h>
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#endif
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#include <asm/irq.h>
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#include <asm/bfin5xx_spi.h>
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/*
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* Name the Board for the /proc/cpuinfo
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*/
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const char bfin_board_name[] = "IP04/IP08";
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/*
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* Driver needs to know address, irq and flag pin.
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*/
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#if defined(CONFIG_BFIN532_IP0X)
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#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
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#include <linux/dm9000.h>
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static struct resource dm9000_resource1[] = {
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{
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.start = 0x20100000,
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.end = 0x20100000 + 1,
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.flags = IORESOURCE_MEM
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},{
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.start = 0x20100000 + 2,
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.end = 0x20100000 + 3,
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.flags = IORESOURCE_MEM
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},{
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.start = IRQ_PF15,
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.end = IRQ_PF15,
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.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
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}
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};
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static struct resource dm9000_resource2[] = {
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{
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.start = 0x20200000,
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.end = 0x20200000 + 1,
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.flags = IORESOURCE_MEM
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},{
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.start = 0x20200000 + 2,
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.end = 0x20200000 + 3,
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.flags = IORESOURCE_MEM
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},{
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.start = IRQ_PF14,
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.end = IRQ_PF14,
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.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
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}
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};
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/*
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* for the moment we limit ourselves to 16bit IO until some
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* better IO routines can be written and tested
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*/
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static struct dm9000_plat_data dm9000_platdata1 = {
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.flags = DM9000_PLATF_16BITONLY,
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};
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static struct platform_device dm9000_device1 = {
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.name = "dm9000",
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.id = 0,
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.num_resources = ARRAY_SIZE(dm9000_resource1),
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.resource = dm9000_resource1,
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.dev = {
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.platform_data = &dm9000_platdata1,
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}
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};
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static struct dm9000_plat_data dm9000_platdata2 = {
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.flags = DM9000_PLATF_16BITONLY,
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};
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static struct platform_device dm9000_device2 = {
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.name = "dm9000",
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.id = 1,
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.num_resources = ARRAY_SIZE(dm9000_resource2),
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.resource = dm9000_resource2,
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.dev = {
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.platform_data = &dm9000_platdata2,
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}
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};
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#endif
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#endif
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#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
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/* all SPI peripherals info goes here */
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#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
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static struct bfin5xx_spi_chip spi_mmc_chip_info = {
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/*
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* CPOL (Clock Polarity)
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* 0 - Active high SCK
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* 1 - Active low SCK
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* CPHA (Clock Phase) Selects transfer format and operation mode
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* 0 - SCLK toggles from middle of the first data bit, slave select
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* pins controlled by hardware.
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* 1 - SCLK toggles from beginning of first data bit, slave select
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* pins controller by user software.
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* .ctl_reg = 0x1c00, * CPOL=1,CPHA=1,Sandisk 1G work
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* NO NO .ctl_reg = 0x1800, * CPOL=1,CPHA=0
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* NO NO .ctl_reg = 0x1400, * CPOL=0,CPHA=1
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*/
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.ctl_reg = 0x1000, /* CPOL=0,CPHA=0,Sandisk 1G work */
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.enable_dma = 0, /* if 1 - block!!! */
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.bits_per_word = 8,
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.cs_change_per_word = 0,
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};
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#endif
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/* Notice: for blackfin, the speed_hz is the value of register
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* SPI_BAUD, not the real baudrate */
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static struct spi_board_info bfin_spi_board_info[] __initdata = {
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#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
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{
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.modalias = "spi_mmc",
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.max_speed_hz = 2,
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.bus_num = 1,
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.chip_select = CONFIG_SPI_MMC_CS_CHAN,
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.platform_data = NULL,
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.controller_data = &spi_mmc_chip_info,
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},
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#endif
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};
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/* SPI controller data */
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static struct bfin5xx_spi_master spi_bfin_master_info = {
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.num_chipselect = 8,
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.enable_dma = 1, /* master has the ability to do dma transfer */
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};
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static struct platform_device spi_bfin_master_device = {
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.name = "bfin-spi-master",
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.id = 1, /* Bus number */
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.dev = {
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.platform_data = &spi_bfin_master_info, /* Passed to driver */
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},
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};
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#endif /* spi master and devices */
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#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
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static struct resource bfin_uart_resources[] = {
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{
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.start = 0xFFC00400,
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.end = 0xFFC004FF,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device bfin_uart_device = {
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.name = "bfin-uart",
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.id = 1,
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.num_resources = ARRAY_SIZE(bfin_uart_resources),
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.resource = bfin_uart_resources,
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};
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#endif
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#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
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static struct resource isp1362_hcd_resources[] = {
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{
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.start = 0x20300000,
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.end = 0x20300000 + 1,
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.flags = IORESOURCE_MEM,
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},{
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.start = 0x20300000 + 2,
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.end = 0x20300000 + 3,
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.flags = IORESOURCE_MEM,
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},{
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.start = IRQ_PF11,
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.end = IRQ_PF11,
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.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
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},
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};
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static struct isp1362_platform_data isp1362_priv = {
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.sel15Kres = 1,
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.clknotstop = 0,
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.oc_enable = 0, /* external OC */
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.int_act_high = 0,
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.int_edge_triggered = 0,
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.remote_wakeup_connected = 0,
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.no_power_switching = 1,
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.power_switching_mode = 0,
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};
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static struct platform_device isp1362_hcd_device = {
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.name = "isp1362-hcd",
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.id = 0,
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.dev = {
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.platform_data = &isp1362_priv,
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},
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.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
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.resource = isp1362_hcd_resources,
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};
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#endif
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static struct platform_device *ip0x_devices[] __initdata = {
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#if defined(CONFIG_BFIN532_IP0X)
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#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
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&dm9000_device1,
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&dm9000_device2,
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#endif
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#endif
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#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
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&spi_bfin_master_device,
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#endif
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#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
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&bfin_uart_device,
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#endif
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#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
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&isp1362_hcd_device,
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#endif
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};
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static int __init ip0x_init(void)
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{
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int i;
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printk(KERN_INFO "%s(): registering device resources\n", __func__);
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platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
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#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
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for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); ++i) {
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int j = 1 << bfin_spi_board_info[i].chip_select;
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/* set spi cs to 1 */
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bfin_write_FIO_DIR(bfin_read_FIO_DIR() | j);
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bfin_write_FIO_FLAG_S(j);
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}
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spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
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#endif
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return 0;
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}
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arch_initcall(ip0x_init);
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@ -29,7 +29,8 @@
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD)
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#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \
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CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD)
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#if (CONFIG_SCLK_HZ > 119402985)
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#define SDRAM_tRP TRP_2
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#define SDRAM_tRP_num 2
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@ -118,6 +119,13 @@
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#define SDRAM_CL CL_3
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#endif
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#if (CONFIG_MEM_MT48LC32M16A2TG_75)
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/*SDRAM INFORMATION: */
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */
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#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
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#define SDRAM_CL CL_3
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#endif
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#if (CONFIG_MEM_GENERIC_BOARD)
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/*SDRAM INFORMATION: Modify this for your board */
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#define SDRAM_Tref 64 /* Refresh period in milliseconds */
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