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drm/i915/gen11+: Only load DRAM information from pcode
Up to now we were reading some DRAM information from MCHBAR register and from pcode what is already not good but some GEN12(TGL-H and ADL-S) platforms have MCHBAR DRAM information in different offsets. This was notified to HW team that decided that the best alternative is always apply the 16gb_dimm watermark adjustment for GEN12+ platforms and read the remaning DRAM information needed to other display programming from pcode. So here moving the DRAM pcode function to intel_dram.c, removing the duplicated fields from intel_qgv_info, setting and using information from dram_info. v2: - bring back num_points to intel_qgv_info as num_qgv_point can be overwritten in icl_get_qgv_points() - add gen12_get_dram_info() and simplify gen11_get_dram_info() Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210128164312.91160-2-jose.souza@intel.com
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@ -20,76 +20,9 @@ struct intel_qgv_point {
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struct intel_qgv_info {
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struct intel_qgv_info {
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struct intel_qgv_point points[I915_NUM_QGV_POINTS];
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struct intel_qgv_point points[I915_NUM_QGV_POINTS];
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u8 num_points;
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u8 num_points;
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u8 num_channels;
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u8 t_bl;
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u8 t_bl;
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enum intel_dram_type dram_type;
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};
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};
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static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
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struct intel_qgv_info *qi)
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{
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u32 val = 0;
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int ret;
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ret = sandybridge_pcode_read(dev_priv,
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ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
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ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
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&val, NULL);
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if (ret)
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return ret;
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if (IS_GEN(dev_priv, 12)) {
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switch (val & 0xf) {
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case 0:
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qi->dram_type = INTEL_DRAM_DDR4;
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break;
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case 3:
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qi->dram_type = INTEL_DRAM_LPDDR4;
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break;
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case 4:
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qi->dram_type = INTEL_DRAM_DDR3;
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break;
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case 5:
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qi->dram_type = INTEL_DRAM_LPDDR3;
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break;
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default:
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MISSING_CASE(val & 0xf);
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break;
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}
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} else if (IS_GEN(dev_priv, 11)) {
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switch (val & 0xf) {
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case 0:
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qi->dram_type = INTEL_DRAM_DDR4;
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break;
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case 1:
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qi->dram_type = INTEL_DRAM_DDR3;
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break;
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case 2:
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qi->dram_type = INTEL_DRAM_LPDDR3;
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break;
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case 3:
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qi->dram_type = INTEL_DRAM_LPDDR4;
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break;
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default:
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MISSING_CASE(val & 0xf);
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break;
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}
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} else {
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MISSING_CASE(INTEL_GEN(dev_priv));
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qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */
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}
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qi->num_channels = (val & 0xf0) >> 4;
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qi->num_points = (val & 0xf00) >> 8;
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if (IS_GEN(dev_priv, 12))
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qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16;
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else if (IS_GEN(dev_priv, 11))
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qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
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return 0;
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}
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static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
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static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
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struct intel_qgv_point *sp,
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struct intel_qgv_point *sp,
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int point)
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int point)
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@ -139,11 +72,15 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
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static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
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static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
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struct intel_qgv_info *qi)
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struct intel_qgv_info *qi)
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{
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{
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const struct dram_info *dram_info = &dev_priv->dram_info;
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int i, ret;
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int i, ret;
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ret = icl_pcode_read_mem_global_info(dev_priv, qi);
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qi->num_points = dram_info->num_qgv_points;
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if (ret)
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return ret;
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if (IS_GEN(dev_priv, 12))
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qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 16;
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else if (IS_GEN(dev_priv, 11))
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qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
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if (drm_WARN_ON(&dev_priv->drm,
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if (drm_WARN_ON(&dev_priv->drm,
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qi->num_points > ARRAY_SIZE(qi->points)))
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qi->num_points > ARRAY_SIZE(qi->points)))
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@ -209,7 +146,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
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{
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{
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struct intel_qgv_info qi = {};
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struct intel_qgv_info qi = {};
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bool is_y_tile = true; /* assume y tile may be used */
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bool is_y_tile = true; /* assume y tile may be used */
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int num_channels;
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int num_channels = dev_priv->dram_info.num_channels;
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int deinterleave;
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int deinterleave;
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int ipqdepth, ipqdepthpch;
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int ipqdepth, ipqdepthpch;
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int dclk_max;
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int dclk_max;
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@ -222,7 +159,6 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
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"Failed to get memory subsystem information, ignoring bandwidth limits");
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"Failed to get memory subsystem information, ignoring bandwidth limits");
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return ret;
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return ret;
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}
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}
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num_channels = qi.num_channels;
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deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
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deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
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dclk_max = icl_sagv_max_dclk(&qi);
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dclk_max = icl_sagv_max_dclk(&qi);
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@ -609,14 +609,15 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
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goto err_msi;
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goto err_msi;
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intel_opregion_setup(dev_priv);
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intel_opregion_setup(dev_priv);
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intel_pcode_init(dev_priv);
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/*
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/*
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* Fill the dram structure to get the system dram info. This will be
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* Fill the dram structure to get the system dram info. This will be
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* used for memory latency calculation.
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* used for memory latency calculation.
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*/
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*/
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intel_dram_detect(dev_priv);
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intel_dram_detect(dev_priv);
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intel_pcode_init(dev_priv);
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intel_bw_init_hw(dev_priv);
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intel_bw_init_hw(dev_priv);
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return 0;
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return 0;
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@ -1135,6 +1135,7 @@ struct drm_i915_private {
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INTEL_DRAM_LPDDR3,
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INTEL_DRAM_LPDDR3,
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INTEL_DRAM_LPDDR4
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INTEL_DRAM_LPDDR4
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} type;
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} type;
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u8 num_qgv_points;
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} dram_info;
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} dram_info;
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struct intel_bw_info {
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struct intel_bw_info {
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@ -5,6 +5,7 @@
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#include "i915_drv.h"
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#include "i915_drv.h"
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#include "intel_dram.h"
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#include "intel_dram.h"
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#include "intel_sideband.h"
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struct dram_dimm_info {
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struct dram_dimm_info {
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u16 size;
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u16 size;
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@ -408,6 +409,81 @@ static int bxt_get_dram_info(struct drm_i915_private *i915)
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return 0;
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return 0;
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}
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}
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static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
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{
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struct dram_info *dram_info = &dev_priv->dram_info;
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u32 val = 0;
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int ret;
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ret = sandybridge_pcode_read(dev_priv,
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ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
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ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
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&val, NULL);
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if (ret)
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return ret;
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if (IS_GEN(dev_priv, 12)) {
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switch (val & 0xf) {
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case 0:
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dram_info->type = INTEL_DRAM_DDR4;
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break;
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case 3:
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dram_info->type = INTEL_DRAM_LPDDR4;
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break;
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case 4:
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dram_info->type = INTEL_DRAM_DDR3;
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break;
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case 5:
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dram_info->type = INTEL_DRAM_LPDDR3;
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break;
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default:
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MISSING_CASE(val & 0xf);
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return -1;
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}
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} else {
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switch (val & 0xf) {
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case 0:
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dram_info->type = INTEL_DRAM_DDR4;
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break;
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case 1:
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dram_info->type = INTEL_DRAM_DDR3;
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break;
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case 2:
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dram_info->type = INTEL_DRAM_LPDDR3;
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break;
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case 3:
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dram_info->type = INTEL_DRAM_LPDDR4;
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break;
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default:
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MISSING_CASE(val & 0xf);
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return -1;
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}
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}
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dram_info->num_channels = (val & 0xf0) >> 4;
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dram_info->num_qgv_points = (val & 0xf00) >> 8;
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return 0;
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}
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static int gen11_get_dram_info(struct drm_i915_private *i915)
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{
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int ret = skl_get_dram_info(i915);
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if (ret)
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return ret;
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return icl_pcode_read_mem_global_info(i915);
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}
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static int gen12_get_dram_info(struct drm_i915_private *i915)
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{
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/* Always needed for GEN12+ */
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i915->dram_info.is_16gb_dimm = true;
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return icl_pcode_read_mem_global_info(i915);
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}
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void intel_dram_detect(struct drm_i915_private *i915)
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void intel_dram_detect(struct drm_i915_private *i915)
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{
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{
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struct dram_info *dram_info = &i915->dram_info;
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struct dram_info *dram_info = &i915->dram_info;
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@ -423,7 +499,11 @@ void intel_dram_detect(struct drm_i915_private *i915)
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if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
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if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
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return;
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return;
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if (IS_GEN9_LP(i915))
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if (INTEL_GEN(i915) >= 12)
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ret = gen12_get_dram_info(i915);
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else if (INTEL_GEN(i915) >= 11)
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ret = gen11_get_dram_info(i915);
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else if (IS_GEN9_LP(i915))
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ret = bxt_get_dram_info(i915);
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ret = bxt_get_dram_info(i915);
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else
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else
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ret = skl_get_dram_info(i915);
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ret = skl_get_dram_info(i915);
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