korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-12-16 23:45:31 +08:00
Code Issues Packages Projects Releases Wiki Activity

ARM: DT: Hisilicon ARM32 SoCs DT updates for 5.10 (take two)

Browse Source 
- Fix the system controller compatible for the hi3620 and hip04 SoCs
 - Add the basic device tree for the hisilicon SD5203 SoC
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJfdCMMAAoJEAvIV27ZiWZcUxIP/1S7eF+l39oud7SPzX7cvY62
 CoYkixPDTm8TvryE7iJD5adSz3ioLQhW5A/lCvglr2nWUOuDOGe06+Oqs5szggHr
 QzUc5mQ90c0uHTzHegr0Gjry6M+paMaLnLaPw6xl6y8I77szPrsebmxLzjXMLqIk
 78XEo+DogxnDZWDfdALKTcTJYP5mhwCDi7HnT4OvIjXMlmGtbmTc7zXOhBQtKk6P
 IEe4h9Qhpjs5MA/kkf9QVWKpwoVP1bVIIaocCNcuqx+2ScGiCb/MibZ4gkRJV5B1
 Wre3tN/kDh0Uq10jrjruH2krpy28dUFhx3pma1Yyn9SLhx8LZzB2L66wndLp4cXf
 nzMuvwW57Lk3Q9y5ZFy97fGE8hO3mWb1xrkFFvuvxormkq1c07iQJ3LGf3NG8SeH
 E/6mq6XQcnO/5UU8sXky3BSWIcxgFO67MT6qaJbTziTRWCDLRZCULR1IufxXCQ5O
 ZLfVobjm+okA0Hz6c3jfShziv957qDClVqUn6wUfThlQaP05ekIdNxn7jNQOd/ju
 Z2WGLDbh1a0GvheAjDPguxyhmFwDzWl4VgwuOSzvxyJ8O6LcjEeOBMEDVDAWLUFK
 3Bs2fqZhVLD8yyJfPPDBfdmn4rBcpmUCP0yaoi0N5YnFDXtOtUJhngnrHVEJY3Ui
 W6xY7lrnVF3znkyOaJET
 =qsbd
 -----END PGP SIGNATURE-----

Merge tag 'hisi-arm32-dt-for-5.10-tag2' of git://github.com/hisilicon/linux-hisi into arm/dt

ARM: DT: Hisilicon ARM32 SoCs DT updates for 5.10 (take two)

- Fix the system controller compatible for the hi3620 and hip04 SoCs
- Add the basic device tree for the hisilicon SD5203 SoC

* tag 'hisi-arm32-dt-for-5.10-tag2' of git://github.com/hisilicon/linux-hisi:
  ARM: dts: hisilicon: add SD5203 dts
  ARM: dts: hisilicon: fix the system controller compatible nodes

Link: https://lore.kernel.org/r/5F742717.5080405@hisilicon.com
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2020-10-03 12:44:42 -07:00
commit 5c505432de
4 changed files with 100 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/Makefile
View File

@ -359,6 +359,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \
mps2-an399.dtb
dtb-$(CONFIG_ARCH_MOXART) += \
moxart-uc7112lx.dtb
dtb-$(CONFIG_ARCH_SD5203) += \
sd5203.dtb
dtb-$(CONFIG_SOC_IMX1) += \
imx1-ads.dtb \
imx1-apf9328.dtb

2
arch/arm/boot/dts/hi3620.dtsi
View File

@ -89,7 +89,7 @@
};
sysctrl: system-controller@802000 {
compatible = "hisilicon,sysctrl";
compatible = "hisilicon,sysctrl", "syscon";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x802000 0x1000>;

2
arch/arm/boot/dts/hip04.dtsi
View File

@ -213,7 +213,7 @@
};
sysctrl: sysctrl {
compatible = "hisilicon,sysctrl";
compatible = "hisilicon,sysctrl", "syscon";
reg = <0x3e00000 0x00100000>;
};

96
arch/arm/boot/dts/sd5203.dts Normal file
View File

@ -0,0 +1,96 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020 Hisilicon Limited.
*
* DTS file for Hisilicon SD5203 Board
*/
/dts-v1/;
/ {
model = "Hisilicon SD5203";
compatible = "H836ASDJ", "hisilicon,sd5203";
interrupt-parent = <&vic>;
#address-cells = <1>;
#size-cells = <1>;
chosen {
bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
};
aliases {
serial0 = &uart0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0 {
device_type = "cpu";
compatible = "arm,arm926ej-s";
reg = <0x0>;
};
};
memory@30000000 {
device_type = "memory";
reg = <0x30000000 0x8000000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
vic: interrupt-controller@10130000 {
compatible = "snps,dw-apb-ictl";
reg = <0x10130000 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
};
refclk125mhz: refclk125mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
timer0: timer@16002000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x16002000 0x1000>;
interrupts = <4>;
clocks = <&refclk125mhz>;
clock-names = "apb_pclk";
};
timer1: timer@16003000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x16003000 0x1000>;
interrupts = <5>;
clocks = <&refclk125mhz>;
clock-names = "apb_pclk";
};
uart0: serial@1600d000 {
compatible = "snps,dw-apb-uart";
reg = <0x1600d000 0x1000>;
bus_id = "uart0";
clocks = <&refclk125mhz>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
interrupts = <17>;
};
uart1: serial@1600c000 {
compatible = "snps,dw-apb-uart";
reg = <0x1600c000 0x1000>;
clocks = <&refclk125mhz>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
interrupts = <16>;
status = "disabled";
};
};
};