From 07caba966dee241cd6599618a243be721195de38 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 30 May 2012 12:18:57 +0200 Subject: [PATCH 1/3] ARM: davinci: cp_intc: Add irq domain support Add irq domain support for DaVinci cp_intc. Boot tested on AM18x EVM. Also tested with GPIO IRQ support on AM18x EVM. Signed-off-by: Heiko Schocher Cc: davinci-linux-open-source@linux.davincidsp.com Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree-discuss@lists.ozlabs.org Cc: Grant Likely Cc: Sekhar Nori Cc: Wolfgang Denk Cc: Sergei Shtylyov [nsekhar@ti.com: add commit description, select IRQ_DOMAIN for CP_INTC in Kconfig] Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/Kconfig | 1 + arch/arm/mach-davinci/cp_intc.c | 63 +++++++++++++++++++++++++-------- 2 files changed, 50 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 32d837d8eab9..2ce1ef07c13d 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -4,6 +4,7 @@ config AINTC bool config CP_INTC + select IRQ_DOMAIN bool config ARCH_DAVINCI_DMx diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c index f83152d643c5..45d52567ced7 100644 --- a/arch/arm/mach-davinci/cp_intc.c +++ b/arch/arm/mach-davinci/cp_intc.c @@ -9,8 +9,10 @@ * kind, whether express or implied. */ +#include #include #include +#include #include #include @@ -28,7 +30,7 @@ static inline void cp_intc_write(unsigned long value, unsigned offset) static void cp_intc_ack_irq(struct irq_data *d) { - cp_intc_write(d->irq, CP_INTC_SYS_STAT_IDX_CLR); + cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR); } /* Disable interrupt */ @@ -36,20 +38,20 @@ static void cp_intc_mask_irq(struct irq_data *d) { /* XXX don't know why we need to disable nIRQ here... */ cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR); - cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_CLR); + cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR); cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); } /* Enable interrupt */ static void cp_intc_unmask_irq(struct irq_data *d) { - cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_SET); + cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET); } static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type) { - unsigned reg = BIT_WORD(d->irq); - unsigned mask = BIT_MASK(d->irq); + unsigned reg = BIT_WORD(d->hwirq); + unsigned mask = BIT_MASK(d->hwirq); unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg)); unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg)); @@ -99,18 +101,36 @@ static struct irq_chip cp_intc_irq_chip = { .irq_set_wake = cp_intc_set_wake, }; -void __init cp_intc_init(void) +static struct irq_domain *cp_intc_domain; + +static int cp_intc_host_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) { - unsigned long num_irq = davinci_soc_info.intc_irq_num; + pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw); + + irq_set_chip(virq, &cp_intc_irq_chip); + set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); + irq_set_handler(virq, handle_edge_irq); + return 0; +} + +static const struct irq_domain_ops cp_intc_host_ops = { + .map = cp_intc_host_map, + .xlate = irq_domain_xlate_onetwocell, +}; + +int __init __cp_intc_init(struct device_node *node) +{ + u32 num_irq = davinci_soc_info.intc_irq_num; u8 *irq_prio = davinci_soc_info.intc_irq_prios; u32 *host_map = davinci_soc_info.intc_host_map; unsigned num_reg = BITS_TO_LONGS(num_irq); - int i; + int i, irq_base; davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC; davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); if (WARN_ON(!davinci_intc_base)) - return; + return -EINVAL; cp_intc_write(0, CP_INTC_GLOBAL_ENABLE); @@ -165,13 +185,28 @@ void __init cp_intc_init(void) for (i = 0; host_map[i] != -1; i++) cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i)); - /* Set up genirq dispatching for cp_intc */ - for (i = 0; i < num_irq; i++) { - irq_set_chip(i, &cp_intc_irq_chip); - set_irq_flags(i, IRQF_VALID | IRQF_PROBE); - irq_set_handler(i, handle_edge_irq); + irq_base = irq_alloc_descs(-1, 0, num_irq, 0); + if (irq_base < 0) { + pr_warn("Couldn't allocate IRQ numbers\n"); + irq_base = 0; + } + + /* create a legacy host */ + cp_intc_domain = irq_domain_add_legacy(node, num_irq, + irq_base, 0, &cp_intc_host_ops, NULL); + + if (!cp_intc_domain) { + pr_err("cp_intc: failed to allocate irq host!\n"); + return -EINVAL; } /* Enable global interrupt */ cp_intc_write(1, CP_INTC_GLOBAL_ENABLE); + + return 0; +} + +void __init cp_intc_init(void) +{ + __cp_intc_init(NULL); } From ce9dcb8784611c50974d1c6b600c71f5c0a29308 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Thu, 31 May 2012 09:59:53 -0700 Subject: [PATCH 2/3] ARM: davinci: add runtime PM support for clock management Add runtime PM core support to davinci by using the pm_clk infrastructure of the PM core. When runtime PM is enabled, the davinci runtime PM implementation will use the pm_clk layer to enable/disable clocks on demand. When runtime PM is disabled, the pm_clk core will automatically enable clocks when the driver is bound and disable clocks when the driver is unbound. Cc: Mark A. Greer Cc: Sekhar Nori Signed-off-by: Kevin Hilman [nsekhar@ti.com: pruned list of header file includes and removed some debug code] Signed-off-by: Sekhar Nori --- arch/arm/mach-davinci/Makefile | 1 + arch/arm/mach-davinci/pm_domain.c | 64 +++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 arch/arm/mach-davinci/pm_domain.c diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 2db78bd5c835..2227effcb0e9 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o obj-$(CONFIG_CPU_FREQ) += cpufreq.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_SUSPEND) += pm.o sleep.o +obj-$(CONFIG_HAVE_CLK) += pm_domain.o diff --git a/arch/arm/mach-davinci/pm_domain.c b/arch/arm/mach-davinci/pm_domain.c new file mode 100644 index 000000000000..00946e23c1ee --- /dev/null +++ b/arch/arm/mach-davinci/pm_domain.c @@ -0,0 +1,64 @@ +/* + * Runtime PM support code for DaVinci + * + * Author: Kevin Hilman + * + * Copyright (C) 2012 Texas Instruments, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include +#include +#include +#include + +#ifdef CONFIG_PM_RUNTIME +static int davinci_pm_runtime_suspend(struct device *dev) +{ + int ret; + + dev_dbg(dev, "%s\n", __func__); + + ret = pm_generic_runtime_suspend(dev); + if (ret) + return ret; + + ret = pm_clk_suspend(dev); + if (ret) { + pm_generic_runtime_resume(dev); + return ret; + } + + return 0; +} + +static int davinci_pm_runtime_resume(struct device *dev) +{ + dev_dbg(dev, "%s\n", __func__); + + pm_clk_resume(dev); + return pm_generic_runtime_resume(dev); +} +#endif + +static struct dev_pm_domain davinci_pm_domain = { + .ops = { + SET_RUNTIME_PM_OPS(davinci_pm_runtime_suspend, + davinci_pm_runtime_resume, NULL) + USE_PLATFORM_PM_SLEEP_OPS + }, +}; + +static struct pm_clk_notifier_block platform_bus_notifier = { + .pm_domain = &davinci_pm_domain, +}; + +static int __init davinci_pm_runtime_init(void) +{ + pm_clk_add_notifier(&platform_bus_type, &platform_bus_notifier); + + return 0; +} +core_initcall(davinci_pm_runtime_init); From 961e657f5a34e3f4ce2cb74cfab11f5c666b03e5 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 30 May 2012 12:18:58 +0200 Subject: [PATCH 3/3] ARM: davinci: cp_intc: Add OF support for TI interrupt controller Add a function to initialize the Common Platform Interrupt Controller (cp_intc) from TI used on OMAP-L1x SoCs using a device tree node. Signed-off-by: Heiko Schocher Cc: davinci-linux-open-source@linux.davincidsp.com Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree-discuss@lists.ozlabs.org Cc: Grant Likely Cc: Sekhar Nori Cc: Wolfgang Denk Cc: Sergei Shtylyov Signed-off-by: Sekhar Nori --- .../bindings/arm/davinci/cp-intc.txt | 27 +++++++++++++++++++ arch/arm/mach-davinci/cp_intc.c | 16 ++++++++--- arch/arm/mach-davinci/include/mach/cp_intc.h | 1 + 3 files changed, 41 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/davinci/cp-intc.txt diff --git a/Documentation/devicetree/bindings/arm/davinci/cp-intc.txt b/Documentation/devicetree/bindings/arm/davinci/cp-intc.txt new file mode 100644 index 000000000000..597e8a089fe4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/davinci/cp-intc.txt @@ -0,0 +1,27 @@ +* TI Common Platform Interrupt Controller + +Common Platform Interrupt Controller (cp_intc) is used on +OMAP-L1x SoCs and can support several configurable number +of interrupts. + +Main node required properties: + +- compatible : should be: + "ti,cp-intc" +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The type shall be a and the value shall be 1. + + The cell contains the interrupt number in the range [0-128]. +- ti,intc-size: Number of interrupts handled by the interrupt controller. +- reg: physical base address and size of the intc registers map. + +Example: + + intc: interrupt-controller@1 { + compatible = "ti,cp-intc"; + interrupt-controller; + #interrupt-cells = <1>; + ti,intc-size = <101>; + reg = <0xfffee000 0x2000>; + }; diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c index 45d52567ced7..006dae8dfe44 100644 --- a/arch/arm/mach-davinci/cp_intc.c +++ b/arch/arm/mach-davinci/cp_intc.c @@ -14,6 +14,9 @@ #include #include #include +#include +#include +#include #include #include @@ -119,7 +122,7 @@ static const struct irq_domain_ops cp_intc_host_ops = { .xlate = irq_domain_xlate_onetwocell, }; -int __init __cp_intc_init(struct device_node *node) +int __init cp_intc_of_init(struct device_node *node, struct device_node *parent) { u32 num_irq = davinci_soc_info.intc_irq_num; u8 *irq_prio = davinci_soc_info.intc_irq_prios; @@ -128,7 +131,14 @@ int __init __cp_intc_init(struct device_node *node) int i, irq_base; davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC; - davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); + if (node) { + davinci_intc_base = of_iomap(node, 0); + if (of_property_read_u32(node, "ti,intc-size", &num_irq)) + pr_warn("unable to get intc-size, default to %d\n", + num_irq); + } else { + davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); + } if (WARN_ON(!davinci_intc_base)) return -EINVAL; @@ -208,5 +218,5 @@ int __init __cp_intc_init(struct device_node *node) void __init cp_intc_init(void) { - __cp_intc_init(NULL); + cp_intc_of_init(NULL, NULL); } diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h index 4e8190eed673..d13d8dfa2b0d 100644 --- a/arch/arm/mach-davinci/include/mach/cp_intc.h +++ b/arch/arm/mach-davinci/include/mach/cp_intc.h @@ -52,5 +52,6 @@ #define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2)) void __init cp_intc_init(void); +int __init cp_intc_of_init(struct device_node *, struct device_node *); #endif /* __ASM_HARDWARE_CP_INTC_H */