mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-15 06:55:13 +08:00
spi/xilinx: Use cached value of register
The control register has not changed since the previous access. Therefore we can use the cached value and safe one bus access. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
parent
a87cbca0ac
commit
5b74d7a3b8
@ -271,7 +271,6 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
|
||||
* transmitter while the Isr refills the transmit register/FIFO,
|
||||
* or make sure it is stopped if we're done.
|
||||
*/
|
||||
cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
|
||||
xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
|
||||
xspi->regs + XSPI_CR_OFFSET);
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user