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drm/tegra: Move common plane code to separate file
Subsequent patches will add support for Tegra186 which has a different architecture and needs different plane code but which can share a lot of code with earlier Tegra support. Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
parent
b1415ff21d
commit
5acd351427
@ -5,6 +5,7 @@ tegra-drm-y := \
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drm.o \
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gem.o \
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fb.o \
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plane.o \
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dc.o \
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output.o \
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rgb.o \
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@ -19,38 +19,12 @@
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#include "dc.h"
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#include "drm.h"
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#include "gem.h"
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#include "plane.h"
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_plane_helper.h>
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struct tegra_plane {
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struct drm_plane base;
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unsigned int index;
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};
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static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
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{
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return container_of(plane, struct tegra_plane, base);
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}
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struct tegra_plane_state {
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struct drm_plane_state base;
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struct tegra_bo_tiling tiling;
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u32 format;
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u32 swap;
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};
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static inline struct tegra_plane_state *
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to_tegra_plane_state(struct drm_plane_state *state)
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{
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if (state)
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return container_of(state, struct tegra_plane_state, base);
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return NULL;
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}
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static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
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{
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stats->frames = 0;
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@ -97,81 +71,6 @@ void tegra_dc_commit(struct tegra_dc *dc)
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tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
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}
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static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
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{
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/* assume no swapping of fetched data */
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if (swap)
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*swap = BYTE_SWAP_NOSWAP;
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switch (fourcc) {
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case DRM_FORMAT_XBGR8888:
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*format = WIN_COLOR_DEPTH_R8G8B8A8;
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break;
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case DRM_FORMAT_XRGB8888:
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*format = WIN_COLOR_DEPTH_B8G8R8A8;
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break;
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case DRM_FORMAT_RGB565:
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*format = WIN_COLOR_DEPTH_B5G6R5;
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break;
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case DRM_FORMAT_UYVY:
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*format = WIN_COLOR_DEPTH_YCbCr422;
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break;
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case DRM_FORMAT_YUYV:
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if (swap)
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*swap = BYTE_SWAP_SWAP2;
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*format = WIN_COLOR_DEPTH_YCbCr422;
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break;
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case DRM_FORMAT_YUV420:
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*format = WIN_COLOR_DEPTH_YCbCr420P;
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break;
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case DRM_FORMAT_YUV422:
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*format = WIN_COLOR_DEPTH_YCbCr422P;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
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{
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switch (format) {
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case WIN_COLOR_DEPTH_YCbCr422:
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case WIN_COLOR_DEPTH_YUV422:
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if (planar)
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*planar = false;
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return true;
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case WIN_COLOR_DEPTH_YCbCr420P:
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case WIN_COLOR_DEPTH_YUV420P:
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case WIN_COLOR_DEPTH_YCbCr422P:
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case WIN_COLOR_DEPTH_YUV422P:
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case WIN_COLOR_DEPTH_YCbCr422R:
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case WIN_COLOR_DEPTH_YUV422R:
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case WIN_COLOR_DEPTH_YCbCr422RA:
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case WIN_COLOR_DEPTH_YUV422RA:
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if (planar)
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*planar = true;
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return true;
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}
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if (planar)
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*planar = false;
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return false;
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}
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static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
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unsigned int bpp)
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{
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@ -223,7 +122,7 @@ static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
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* For YUV planar modes, the number of bytes per pixel takes into
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* account only the luma component and therefore is 1.
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*/
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yuv = tegra_dc_format_is_yuv(window->format, &planar);
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yuv = tegra_plane_format_is_yuv(window->format, &planar);
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if (!yuv)
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bpp = window->bits_per_pixel / 8;
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else
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@ -385,101 +284,12 @@ static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
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spin_unlock_irqrestore(&dc->lock, flags);
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}
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static void tegra_plane_destroy(struct drm_plane *plane)
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{
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struct tegra_plane *p = to_tegra_plane(plane);
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drm_plane_cleanup(plane);
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kfree(p);
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}
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static const u32 tegra_primary_plane_formats[] = {
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_RGB565,
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};
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static void tegra_plane_reset(struct drm_plane *plane)
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{
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struct tegra_plane_state *state;
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if (plane->state)
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__drm_atomic_helper_plane_destroy_state(plane->state);
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kfree(plane->state);
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plane->state = NULL;
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state = kzalloc(sizeof(*state), GFP_KERNEL);
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if (state) {
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plane->state = &state->base;
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plane->state->plane = plane;
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}
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}
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static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
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{
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struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
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struct tegra_plane_state *copy;
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copy = kmalloc(sizeof(*copy), GFP_KERNEL);
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if (!copy)
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return NULL;
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__drm_atomic_helper_plane_duplicate_state(plane, ©->base);
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copy->tiling = state->tiling;
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copy->format = state->format;
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copy->swap = state->swap;
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return ©->base;
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}
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static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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__drm_atomic_helper_plane_destroy_state(state);
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kfree(state);
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}
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static const struct drm_plane_funcs tegra_plane_funcs = {
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.update_plane = drm_atomic_helper_update_plane,
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.disable_plane = drm_atomic_helper_disable_plane,
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.destroy = tegra_plane_destroy,
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.reset = tegra_plane_reset,
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.atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
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.atomic_destroy_state = tegra_plane_atomic_destroy_state,
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};
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static int tegra_plane_state_add(struct tegra_plane *plane,
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struct drm_plane_state *state)
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{
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struct drm_crtc_state *crtc_state;
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struct tegra_dc_state *tegra;
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struct drm_rect clip;
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int err;
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/* Propagate errors from allocation or locking failures. */
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crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
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if (IS_ERR(crtc_state))
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return PTR_ERR(crtc_state);
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clip.x1 = 0;
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clip.y1 = 0;
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clip.x2 = crtc_state->mode.hdisplay;
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clip.y2 = crtc_state->mode.vdisplay;
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/* Check plane state for visibility and calculate clipping bounds */
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err = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
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0, INT_MAX, true, true);
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if (err < 0)
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return err;
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tegra = to_dc_state(crtc_state);
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tegra->planes |= WIN_A_ACT_REQ << plane->index;
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return 0;
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}
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static int tegra_plane_atomic_check(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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@ -493,8 +303,9 @@ static int tegra_plane_atomic_check(struct drm_plane *plane,
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if (!state->crtc)
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return 0;
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err = tegra_dc_format(state->fb->format->format, &plane_state->format,
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&plane_state->swap);
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err = tegra_plane_format(state->fb->format->format,
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&plane_state->format,
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&plane_state->swap);
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if (err < 0)
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return err;
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180
drivers/gpu/drm/tegra/plane.c
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180
drivers/gpu/drm/tegra/plane.c
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@ -0,0 +1,180 @@
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/*
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* Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_plane_helper.h>
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#include "dc.h"
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#include "plane.h"
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static void tegra_plane_destroy(struct drm_plane *plane)
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{
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struct tegra_plane *p = to_tegra_plane(plane);
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drm_plane_cleanup(plane);
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kfree(p);
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}
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static void tegra_plane_reset(struct drm_plane *plane)
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{
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struct tegra_plane_state *state;
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if (plane->state)
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__drm_atomic_helper_plane_destroy_state(plane->state);
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kfree(plane->state);
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plane->state = NULL;
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state = kzalloc(sizeof(*state), GFP_KERNEL);
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if (state) {
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plane->state = &state->base;
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plane->state->plane = plane;
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}
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}
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static struct drm_plane_state *
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tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
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{
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struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
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struct tegra_plane_state *copy;
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copy = kmalloc(sizeof(*copy), GFP_KERNEL);
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if (!copy)
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return NULL;
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__drm_atomic_helper_plane_duplicate_state(plane, ©->base);
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copy->tiling = state->tiling;
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copy->format = state->format;
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copy->swap = state->swap;
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return ©->base;
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}
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static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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__drm_atomic_helper_plane_destroy_state(state);
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kfree(state);
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}
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const struct drm_plane_funcs tegra_plane_funcs = {
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.update_plane = drm_atomic_helper_update_plane,
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.disable_plane = drm_atomic_helper_disable_plane,
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.destroy = tegra_plane_destroy,
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.reset = tegra_plane_reset,
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.atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
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.atomic_destroy_state = tegra_plane_atomic_destroy_state,
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};
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int tegra_plane_state_add(struct tegra_plane *plane,
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struct drm_plane_state *state)
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{
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struct drm_crtc_state *crtc_state;
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struct tegra_dc_state *tegra;
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struct drm_rect clip;
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int err;
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/* Propagate errors from allocation or locking failures. */
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crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
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if (IS_ERR(crtc_state))
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return PTR_ERR(crtc_state);
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clip.x1 = 0;
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clip.y1 = 0;
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clip.x2 = crtc_state->mode.hdisplay;
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clip.y2 = crtc_state->mode.vdisplay;
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/* Check plane state for visibility and calculate clipping bounds */
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err = drm_atomic_helper_check_plane_state(state, crtc_state, &clip,
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0, INT_MAX, true, true);
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if (err < 0)
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return err;
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tegra = to_dc_state(crtc_state);
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tegra->planes |= WIN_A_ACT_REQ << plane->index;
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return 0;
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}
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int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap)
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{
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/* assume no swapping of fetched data */
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if (swap)
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*swap = BYTE_SWAP_NOSWAP;
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switch (fourcc) {
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case DRM_FORMAT_XBGR8888:
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*format = WIN_COLOR_DEPTH_R8G8B8A8;
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break;
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case DRM_FORMAT_XRGB8888:
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*format = WIN_COLOR_DEPTH_B8G8R8A8;
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break;
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case DRM_FORMAT_RGB565:
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*format = WIN_COLOR_DEPTH_B5G6R5;
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break;
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case DRM_FORMAT_UYVY:
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*format = WIN_COLOR_DEPTH_YCbCr422;
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break;
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case DRM_FORMAT_YUYV:
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if (!swap)
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return -EINVAL;
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*format = WIN_COLOR_DEPTH_YCbCr422;
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*swap = BYTE_SWAP_SWAP2;
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break;
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case DRM_FORMAT_YUV420:
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*format = WIN_COLOR_DEPTH_YCbCr420P;
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break;
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case DRM_FORMAT_YUV422:
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*format = WIN_COLOR_DEPTH_YCbCr422P;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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bool tegra_plane_format_is_yuv(unsigned int format, bool *planar)
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{
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switch (format) {
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case WIN_COLOR_DEPTH_YCbCr422:
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case WIN_COLOR_DEPTH_YUV422:
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if (planar)
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*planar = false;
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return true;
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case WIN_COLOR_DEPTH_YCbCr420P:
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case WIN_COLOR_DEPTH_YUV420P:
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case WIN_COLOR_DEPTH_YCbCr422P:
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case WIN_COLOR_DEPTH_YUV422P:
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case WIN_COLOR_DEPTH_YCbCr422R:
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case WIN_COLOR_DEPTH_YUV422R:
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case WIN_COLOR_DEPTH_YCbCr422RA:
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case WIN_COLOR_DEPTH_YUV422RA:
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if (planar)
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*planar = true;
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return true;
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}
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if (planar)
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*planar = false;
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return false;
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}
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59
drivers/gpu/drm/tegra/plane.h
Normal file
59
drivers/gpu/drm/tegra/plane.h
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@ -0,0 +1,59 @@
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/*
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* Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef TEGRA_PLANE_H
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#define TEGRA_PLANE_H 1
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#include <drm/drm_plane.h>
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struct tegra_bo;
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struct tegra_plane {
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struct drm_plane base;
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unsigned int index;
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};
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struct tegra_cursor {
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struct tegra_plane base;
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struct tegra_bo *bo;
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unsigned int width;
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unsigned int height;
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};
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static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
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{
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return container_of(plane, struct tegra_plane, base);
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}
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struct tegra_plane_state {
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struct drm_plane_state base;
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struct tegra_bo_tiling tiling;
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u32 format;
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u32 swap;
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};
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static inline struct tegra_plane_state *
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to_tegra_plane_state(struct drm_plane_state *state)
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{
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if (state)
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return container_of(state, struct tegra_plane_state, base);
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return NULL;
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}
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extern const struct drm_plane_funcs tegra_plane_funcs;
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int tegra_plane_state_add(struct tegra_plane *plane,
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struct drm_plane_state *state);
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int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap);
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bool tegra_plane_format_is_yuv(unsigned int format, bool *planar);
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#endif /* TEGRA_PLANE_H */
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