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[BNX2]: Add 5709 init code.
Add basic support to initialize the 5709 chip. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
David S. Miller
parent
9052a840ff
commit
59b47d8ad3
@ -236,8 +236,23 @@ static void
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bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
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{
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offset += cid_addr;
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REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
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REG_WR(bp, BNX2_CTX_DATA, val);
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if (CHIP_NUM(bp) == CHIP_NUM_5709) {
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int i;
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REG_WR(bp, BNX2_CTX_CTX_DATA, val);
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REG_WR(bp, BNX2_CTX_CTX_CTRL,
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offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
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for (i = 0; i < 5; i++) {
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u32 val;
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val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
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if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
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break;
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udelay(5);
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}
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} else {
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REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
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REG_WR(bp, BNX2_CTX_DATA, val);
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}
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}
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static int
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@ -403,6 +418,14 @@ bnx2_free_mem(struct bnx2 *bp)
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{
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int i;
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for (i = 0; i < bp->ctx_pages; i++) {
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if (bp->ctx_blk[i]) {
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pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
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bp->ctx_blk[i],
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bp->ctx_blk_mapping[i]);
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bp->ctx_blk[i] = NULL;
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}
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}
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if (bp->status_blk) {
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pci_free_consistent(bp->pdev, bp->status_stats_size,
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bp->status_blk, bp->status_blk_mapping);
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@ -481,6 +504,18 @@ bnx2_alloc_mem(struct bnx2 *bp)
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bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
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if (CHIP_NUM(bp) == CHIP_NUM_5709) {
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bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
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if (bp->ctx_pages == 0)
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bp->ctx_pages = 1;
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for (i = 0; i < bp->ctx_pages; i++) {
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bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
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BCM_PAGE_SIZE,
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&bp->ctx_blk_mapping[i]);
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if (bp->ctx_blk[i] == NULL)
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goto alloc_mem_err;
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}
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}
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return 0;
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alloc_mem_err:
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@ -803,13 +838,13 @@ bnx2_set_mac_link(struct bnx2 *bp)
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val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
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BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
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BNX2_EMAC_MODE_25G);
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BNX2_EMAC_MODE_25G_MODE);
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if (bp->link_up) {
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switch (bp->line_speed) {
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case SPEED_10:
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if (CHIP_NUM(bp) == CHIP_NUM_5708) {
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val |= BNX2_EMAC_MODE_PORT_MII_10;
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if (CHIP_NUM(bp) != CHIP_NUM_5706) {
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val |= BNX2_EMAC_MODE_PORT_MII_10M;
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break;
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}
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/* fall through */
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@ -817,7 +852,7 @@ bnx2_set_mac_link(struct bnx2 *bp)
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val |= BNX2_EMAC_MODE_PORT_MII;
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break;
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case SPEED_2500:
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val |= BNX2_EMAC_MODE_25G;
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val |= BNX2_EMAC_MODE_25G_MODE;
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/* fall through */
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case SPEED_1000:
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val |= BNX2_EMAC_MODE_PORT_GMII;
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@ -1263,9 +1298,8 @@ bnx2_init_5706s_phy(struct bnx2 *bp)
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{
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bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
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if (CHIP_NUM(bp) == CHIP_NUM_5706) {
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REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
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}
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if (CHIP_NUM(bp) == CHIP_NUM_5706)
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REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
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if (bp->dev->mtu > 1500) {
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u32 val;
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@ -1408,7 +1442,7 @@ bnx2_set_phy_loopback(struct bnx2 *bp)
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mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
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mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
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BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
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BNX2_EMAC_MODE_25G);
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BNX2_EMAC_MODE_25G_MODE);
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mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
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REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
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@ -1459,6 +1493,40 @@ bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
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return 0;
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}
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static int
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bnx2_init_5709_context(struct bnx2 *bp)
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{
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int i, ret = 0;
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u32 val;
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val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
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val |= (BCM_PAGE_BITS - 8) << 16;
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REG_WR(bp, BNX2_CTX_COMMAND, val);
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for (i = 0; i < bp->ctx_pages; i++) {
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int j;
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REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
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(bp->ctx_blk_mapping[i] & 0xffffffff) |
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BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
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REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
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(u64) bp->ctx_blk_mapping[i] >> 32);
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REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
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BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
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for (j = 0; j < 10; j++) {
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val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
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if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
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break;
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udelay(5);
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}
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if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
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ret = -EBUSY;
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break;
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}
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}
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return ret;
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}
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static void
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bnx2_init_context(struct bnx2 *bp)
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{
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@ -1581,9 +1649,8 @@ bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
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return -ENOMEM;
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}
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if (unlikely((align = (unsigned long) skb->data & 0x7))) {
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skb_reserve(skb, 8 - align);
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}
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if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
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skb_reserve(skb, BNX2_RX_ALIGN - align);
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mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
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PCI_DMA_FROMDEVICE);
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@ -3282,7 +3349,10 @@ bnx2_init_chip(struct bnx2 *bp)
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/* Initialize context mapping and zero out the quick contexts. The
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* context block must have already been enabled. */
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bnx2_init_context(bp);
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if (CHIP_NUM(bp) == CHIP_NUM_5709)
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bnx2_init_5709_context(bp);
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else
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bnx2_init_context(bp);
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if ((rc = bnx2_init_cpus(bp)) != 0)
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return rc;
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@ -3393,12 +3463,40 @@ bnx2_init_chip(struct bnx2 *bp)
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return rc;
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}
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static void
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bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
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{
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u32 val, offset0, offset1, offset2, offset3;
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if (CHIP_NUM(bp) == CHIP_NUM_5709) {
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offset0 = BNX2_L2CTX_TYPE_XI;
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offset1 = BNX2_L2CTX_CMD_TYPE_XI;
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offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
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offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
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} else {
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offset0 = BNX2_L2CTX_TYPE;
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offset1 = BNX2_L2CTX_CMD_TYPE;
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offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
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offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
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}
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val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
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CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
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val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
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CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
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val = (u64) bp->tx_desc_mapping >> 32;
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CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
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val = (u64) bp->tx_desc_mapping & 0xffffffff;
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CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
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}
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static void
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bnx2_init_tx_ring(struct bnx2 *bp)
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{
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struct tx_bd *txbd;
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u32 val;
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u32 cid;
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bp->tx_wake_thresh = bp->tx_ring_size / 2;
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@ -3412,19 +3510,11 @@ bnx2_init_tx_ring(struct bnx2 *bp)
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bp->hw_tx_cons = 0;
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bp->tx_prod_bseq = 0;
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val = BNX2_L2CTX_TYPE_TYPE_L2;
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val |= BNX2_L2CTX_TYPE_SIZE_L2;
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CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
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cid = TX_CID;
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bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
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bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
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val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
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val |= 8 << 16;
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CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
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val = (u64) bp->tx_desc_mapping >> 32;
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CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
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val = (u64) bp->tx_desc_mapping & 0xffffffff;
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CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
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bnx2_init_tx_context(bp, cid);
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}
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static void
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@ -3437,8 +3527,8 @@ bnx2_init_rx_ring(struct bnx2 *bp)
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/* 8 for CRC and VLAN */
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bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
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/* 8 for alignment */
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bp->rx_buf_size = bp->rx_buf_use_size + 8;
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/* hw alignment */
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bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
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ring_prod = prod = bp->rx_prod = 0;
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bp->rx_cons = 0;
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@ -5542,13 +5632,6 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
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goto err_out_release;
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}
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bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
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if (bp->pcix_cap == 0) {
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dev_err(&pdev->dev, "Cannot find PCIX capability, aborting.\n");
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rc = -EIO;
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goto err_out_release;
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}
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if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
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bp->flags |= USING_DAC_FLAG;
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if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
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@ -5571,7 +5654,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
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INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
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dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
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mem_len = MB_GET_CID_ADDR(17);
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mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
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dev->mem_end = dev->mem_start + mem_len;
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dev->irq = pdev->irq;
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@ -5595,6 +5678,16 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
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bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
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if (CHIP_NUM(bp) != CHIP_NUM_5709) {
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bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
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if (bp->pcix_cap == 0) {
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dev_err(&pdev->dev,
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"Cannot find PCIX capability, aborting.\n");
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rc = -EIO;
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goto err_out_unmap;
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}
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}
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/* Get bus information. */
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reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
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if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
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