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PCI/core: Use PCI Express Capability accessors

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Use PCI Express Capability access functions to simplify core.

Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Jiang Liu 2012-07-24 17:20:06 +08:00 committed by Bjorn Helgaas
parent 8c0d3a02c1
commit 59875ae489
3 changed files with 66 additions and 274 deletions
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314
drivers/pci/pci.c
View File

@ -253,38 +253,6 @@ int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
return pos;
}
/**
* pci_pcie_cap2 - query for devices' PCI_CAP_ID_EXP v2 capability structure
* @dev: PCI device to check
*
* Like pci_pcie_cap() but also checks that the PCIe capability version is
* >= 2. Note that v1 capability structures could be sparse in that not
* all register fields were required. v2 requires the entire structure to
* be present size wise, while still allowing for non-implemented registers
* to exist but they must be hardwired to 0.
*
* Due to the differences in the versions of capability structures, one
* must be careful not to try and access non-existant registers that may
* exist in early versions - v1 - of Express devices.
*
* Returns the offset of the PCIe capability structure as long as the
* capability version is >= 2; otherwise 0 is returned.
*/
static int pci_pcie_cap2(struct pci_dev *dev)
{
u16 flags;
int pos;
pos = pci_pcie_cap(dev);
if (pos) {
pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
if ((flags & PCI_EXP_FLAGS_VERS) < 2)
pos = 0;
}
return pos;
}
/**
* pci_find_ext_capability - Find an extended capability
* @dev: PCI device to query
@ -854,21 +822,6 @@ EXPORT_SYMBOL(pci_choose_state);
#define PCI_EXP_SAVE_REGS 7
#define pcie_cap_has_devctl(type, flags) 1
#define pcie_cap_has_lnkctl(type, flags) \
((flags & PCI_EXP_FLAGS_VERS) > 1 || \
(type == PCI_EXP_TYPE_ROOT_PORT || \
type == PCI_EXP_TYPE_ENDPOINT || \
type == PCI_EXP_TYPE_LEG_END))
#define pcie_cap_has_sltctl(type, flags) \
((flags & PCI_EXP_FLAGS_VERS) > 1 || \
((type == PCI_EXP_TYPE_ROOT_PORT) || \
(type == PCI_EXP_TYPE_DOWNSTREAM && \
(flags & PCI_EXP_FLAGS_SLOT))))
#define pcie_cap_has_rtctl(type, flags) \
((flags & PCI_EXP_FLAGS_VERS) > 1 || \
(type == PCI_EXP_TYPE_ROOT_PORT || \
type == PCI_EXP_TYPE_RC_EC))
static struct pci_cap_saved_state *pci_find_saved_cap(
struct pci_dev *pci_dev, char cap)
@ -885,13 +838,11 @@ static struct pci_cap_saved_state *pci_find_saved_cap(
static int pci_save_pcie_state(struct pci_dev *dev)
{
int type, pos, i = 0;
int i = 0;
struct pci_cap_saved_state *save_state;
u16 *cap;
u16 flags;
pos = pci_pcie_cap(dev);
if (!pos)
if (!pci_is_pcie(dev))
return 0;
save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
@ -899,62 +850,37 @@ static int pci_save_pcie_state(struct pci_dev *dev)
dev_err(&dev->dev, "buffer not found in %s\n", __func__);
return -ENOMEM;
}
cap = (u16 *)&save_state->cap.data[0];
pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
type = pci_pcie_type(dev);
if (pcie_cap_has_devctl(type, flags))
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
if (pcie_cap_has_lnkctl(type, flags))
pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
if (pcie_cap_has_sltctl(type, flags))
pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
if (pcie_cap_has_rtctl(type, flags))
pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
pos = pci_pcie_cap2(dev);
if (!pos)
return 0;
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
return 0;
}
static void pci_restore_pcie_state(struct pci_dev *dev)
{
int i = 0, pos, type;
int i = 0;
struct pci_cap_saved_state *save_state;
u16 *cap;
u16 flags;
save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
if (!save_state || pos <= 0)
if (!save_state)
return;
cap = (u16 *)&save_state->cap.data[0];
pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
type = pci_pcie_type(dev);
if (pcie_cap_has_devctl(type, flags))
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
if (pcie_cap_has_lnkctl(type, flags))
pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
if (pcie_cap_has_sltctl(type, flags))
pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
if (pcie_cap_has_rtctl(type, flags))
pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
pos = pci_pcie_cap2(dev);
if (!pos)
return;
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
}
@ -2068,35 +1994,24 @@ void pci_free_cap_save_buffers(struct pci_dev *dev)
*/
void pci_enable_ari(struct pci_dev *dev)
{
int pos;
u32 cap;
u16 ctrl;
struct pci_dev *bridge;
if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
return;
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
if (!pos)
if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI))
return;
bridge = dev->bus->self;
if (!bridge)
return;
/* ARI is a PCIe cap v2 feature */
pos = pci_pcie_cap2(bridge);
if (!pos)
return;
pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
if (!(cap & PCI_EXP_DEVCAP2_ARI))
return;
pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
ctrl |= PCI_EXP_DEVCTL2_ARI;
pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_ARI);
bridge->ari_enabled = 1;
}
@ -2111,20 +2026,14 @@ void pci_enable_ari(struct pci_dev *dev)
*/
void pci_enable_ido(struct pci_dev *dev, unsigned long type)
{
int pos;
u16 ctrl;
u16 ctrl = 0;
/* ID-based Ordering is a PCIe cap v2 feature */
pos = pci_pcie_cap2(dev);
if (!pos)
return;
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
if (type & PCI_EXP_IDO_REQUEST)
ctrl |= PCI_EXP_IDO_REQ_EN;
if (type & PCI_EXP_IDO_COMPLETION)
ctrl |= PCI_EXP_IDO_CMP_EN;
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
if (ctrl)
pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
}
EXPORT_SYMBOL(pci_enable_ido);
@ -2135,20 +2044,14 @@ EXPORT_SYMBOL(pci_enable_ido);
*/
void pci_disable_ido(struct pci_dev *dev, unsigned long type)
{
int pos;
u16 ctrl;
u16 ctrl = 0;
/* ID-based Ordering is a PCIe cap v2 feature */
pos = pci_pcie_cap2(dev);
if (!pos)
return;
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
if (type & PCI_EXP_IDO_REQUEST)
ctrl &= ~PCI_EXP_IDO_REQ_EN;
ctrl |= PCI_EXP_IDO_REQ_EN;
if (type & PCI_EXP_IDO_COMPLETION)
ctrl &= ~PCI_EXP_IDO_CMP_EN;
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
ctrl |= PCI_EXP_IDO_CMP_EN;
if (ctrl)
pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
}
EXPORT_SYMBOL(pci_disable_ido);
@ -2173,17 +2076,11 @@ EXPORT_SYMBOL(pci_disable_ido);
*/
int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
{
int pos;
u32 cap;
u16 ctrl;
int ret;
/* OBFF is a PCIe cap v2 feature */
pos = pci_pcie_cap2(dev);
if (!pos)
return -ENOTSUPP;
pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
if (!(cap & PCI_EXP_OBFF_MASK))
return -ENOTSUPP; /* no OBFF support at all */
@ -2194,7 +2091,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
return ret;
}
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
if (cap & PCI_EXP_OBFF_WAKE)
ctrl |= PCI_EXP_OBFF_WAKE_EN;
else {
@ -2212,7 +2109,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
return -ENOTSUPP;
}
}
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
return 0;
}
@ -2226,17 +2123,7 @@ EXPORT_SYMBOL(pci_enable_obff);
*/
void pci_disable_obff(struct pci_dev *dev)
{
int pos;
u16 ctrl;
/* OBFF is a PCIe cap v2 feature */
pos = pci_pcie_cap2(dev);
if (!pos)
return;
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_OBFF_WAKE_EN);
}
EXPORT_SYMBOL(pci_disable_obff);
@ -2249,15 +2136,9 @@ EXPORT_SYMBOL(pci_disable_obff);
*/
static bool pci_ltr_supported(struct pci_dev *dev)
{
int pos;
u32 cap;
/* LTR is a PCIe cap v2 feature */
pos = pci_pcie_cap2(dev);
if (!pos)
return false;
pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
return cap & PCI_EXP_DEVCAP2_LTR;
}
@ -2274,22 +2155,15 @@ static bool pci_ltr_supported(struct pci_dev *dev)
*/
int pci_enable_ltr(struct pci_dev *dev)
{
int pos;
u16 ctrl;
int ret;
if (!pci_ltr_supported(dev))
return -ENOTSUPP;
/* LTR is a PCIe cap v2 feature */
pos = pci_pcie_cap2(dev);
if (!pos)
return -ENOTSUPP;
/* Only primary function can enable/disable LTR */
if (PCI_FUNC(dev->devfn) != 0)
return -EINVAL;
if (!pci_ltr_supported(dev))
return -ENOTSUPP;
/* Enable upstream ports first */
if (dev->bus->self) {
ret = pci_enable_ltr(dev->bus->self);
@ -2297,11 +2171,7 @@ int pci_enable_ltr(struct pci_dev *dev)
return ret;
}
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
ctrl |= PCI_EXP_LTR_EN;
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
return 0;
return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
}
EXPORT_SYMBOL(pci_enable_ltr);
@ -2311,24 +2181,14 @@ EXPORT_SYMBOL(pci_enable_ltr);
*/
void pci_disable_ltr(struct pci_dev *dev)
{
int pos;
u16 ctrl;
if (!pci_ltr_supported(dev))
return;
/* LTR is a PCIe cap v2 feature */
pos = pci_pcie_cap2(dev);
if (!pos)
return;
/* Only primary function can enable/disable LTR */
if (PCI_FUNC(dev->devfn) != 0)
return;
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
ctrl &= ~PCI_EXP_LTR_EN;
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
if (!pci_ltr_supported(dev))
return;
pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_LTR_EN);
}
EXPORT_SYMBOL(pci_disable_ltr);
@ -2411,9 +2271,6 @@ void pci_enable_acs(struct pci_dev *dev)
if (!pci_acs_enable)
return;
if (!pci_is_pcie(dev))
return;
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
if (!pos)
return;
@ -3178,15 +3035,10 @@ EXPORT_SYMBOL(pci_set_dma_seg_boundary);
static int pcie_flr(struct pci_dev *dev, int probe)
{
int i;
int pos;
u32 cap;
u16 status, control;
u16 status;
pos = pci_pcie_cap(dev);
if (!pos)
return -ENOTTY;
pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
if (!(cap & PCI_EXP_DEVCAP_FLR))
return -ENOTTY;
@ -3198,7 +3050,7 @@ static int pcie_flr(struct pci_dev *dev, int probe)
if (i)
msleep((1 << (i - 1)) * 100);
pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
if (!(status & PCI_EXP_DEVSTA_TRPND))
goto clear;
}
@ -3207,9 +3059,7 @@ static int pcie_flr(struct pci_dev *dev, int probe)
"proceeding with reset anyway\n");
clear:
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
control |= PCI_EXP_DEVCTL_BCR_FLR;
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
msleep(100);
@ -3577,18 +3427,11 @@ EXPORT_SYMBOL(pcix_set_mmrbc);
*/
int pcie_get_readrq(struct pci_dev *dev)
{
int ret, cap;
u16 ctl;
cap = pci_pcie_cap(dev);
if (!cap)
return -EINVAL;
pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
if (!ret)
ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
return ret;
return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
}
EXPORT_SYMBOL(pcie_get_readrq);
@ -3602,19 +3445,11 @@ EXPORT_SYMBOL(pcie_get_readrq);
*/
int pcie_set_readrq(struct pci_dev *dev, int rq)
{
int cap, err = -EINVAL;
u16 ctl, v;
u16 v;
if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
goto out;
return -EINVAL;
cap = pci_pcie_cap(dev);
if (!cap)
goto out;
err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
if (err)
goto out;
/*
* If using the "performance" PCIe config, we clamp the
* read rq size to the max packet size to prevent the
@ -3632,14 +3467,8 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
v = (ffs(rq) - 8) << 12;
if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
ctl &= ~PCI_EXP_DEVCTL_READRQ;
ctl |= v;
err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
}
out:
return err;
return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_READRQ, v);
}
EXPORT_SYMBOL(pcie_set_readrq);
@ -3652,18 +3481,11 @@ EXPORT_SYMBOL(pcie_set_readrq);
*/
int pcie_get_mps(struct pci_dev *dev)
{
int ret, cap;
u16 ctl;
cap = pci_pcie_cap(dev);
if (!cap)
return -EINVAL;
pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
if (!ret)
ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
return ret;
return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
}
/**
@ -3676,32 +3498,18 @@ int pcie_get_mps(struct pci_dev *dev)
*/
int pcie_set_mps(struct pci_dev *dev, int mps)
{
int cap, err = -EINVAL;
u16 ctl, v;
u16 v;
if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
goto out;
return -EINVAL;
v = ffs(mps) - 8;
if (v > dev->pcie_mpss)
goto out;
return -EINVAL;
v <<= 5;
cap = pci_pcie_cap(dev);
if (!cap)
goto out;
err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
if (err)
goto out;
if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) {
ctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
ctl |= v;
err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
}
out:
return err;
return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_PAYLOAD, v);
}
/**

17
drivers/pci/probe.c
View File

@ -603,10 +603,10 @@ static void pci_set_bus_speed(struct pci_bus *bus)
u32 linkcap;
u16 linksta;
pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
pcie_update_link_speed(bus, linksta);
}
}
@ -936,17 +936,9 @@ void set_pcie_port_type(struct pci_dev *pdev)
void set_pcie_hotplug_bridge(struct pci_dev *pdev)
{
int pos;
u16 reg16;
u32 reg32;
pos = pci_pcie_cap(pdev);
if (!pos)
return;
pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
if (!(reg16 & PCI_EXP_FLAGS_SLOT))
return;
pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, &reg32);
pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
if (reg32 & PCI_EXP_SLTCAP_HPC)
pdev->is_hotplug_bridge = 1;
}
@ -1160,8 +1152,7 @@ int pci_cfg_space_size(struct pci_dev *dev)
if (class == PCI_CLASS_BRIDGE_HOST)
return pci_cfg_space_size_ext(dev);
pos = pci_pcie_cap(dev);
if (!pos) {
if (!pci_is_pcie(dev)) {
pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
if (!pos)
goto fail;

9
drivers/pci/quirks.c
View File

@ -3081,17 +3081,10 @@ static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
{
int pos;
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
if (!pos)
return -ENOTTY;
if (probe)
return 0;
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
PCI_EXP_DEVCTL_BCR_FLR);
pcie_capability_write_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
msleep(100);
return 0;