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Merge branch 'shifts-cleanup'
Jiong Wang says: ==================== NFP JIT back-end is missing several ALU32 logic shifts support. Also, shifts with shift amount be zero are not handled properly. This set cleans up these issues. ==================== Signed-off-by: Alexei Starovoitov <ast@kernel.org>
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commit
5974b7c1e4
@ -1967,6 +1967,9 @@ static int neg_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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*/
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static int __shl_imm64(struct nfp_prog *nfp_prog, u8 dst, u8 shift_amt)
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{
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if (!shift_amt)
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return 0;
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if (shift_amt < 32) {
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emit_shf(nfp_prog, reg_both(dst + 1), reg_a(dst + 1),
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SHF_OP_NONE, reg_b(dst), SHF_SC_R_DSHF,
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@ -2079,6 +2082,9 @@ static int shl_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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*/
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static int __shr_imm64(struct nfp_prog *nfp_prog, u8 dst, u8 shift_amt)
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{
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if (!shift_amt)
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return 0;
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if (shift_amt < 32) {
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emit_shf(nfp_prog, reg_both(dst), reg_a(dst + 1), SHF_OP_NONE,
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reg_b(dst), SHF_SC_R_DSHF, shift_amt);
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@ -2180,6 +2186,9 @@ static int shr_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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*/
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static int __ashr_imm64(struct nfp_prog *nfp_prog, u8 dst, u8 shift_amt)
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{
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if (!shift_amt)
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return 0;
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if (shift_amt < 32) {
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emit_shf(nfp_prog, reg_both(dst), reg_a(dst + 1), SHF_OP_NONE,
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reg_b(dst), SHF_SC_R_DSHF, shift_amt);
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@ -2388,10 +2397,13 @@ static int neg_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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static int __ashr_imm(struct nfp_prog *nfp_prog, u8 dst, u8 shift_amt)
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{
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/* Set signedness bit (MSB of result). */
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emit_alu(nfp_prog, reg_none(), reg_a(dst), ALU_OP_OR, reg_imm(0));
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emit_shf(nfp_prog, reg_both(dst), reg_none(), SHF_OP_ASHR, reg_b(dst),
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SHF_SC_R_SHF, shift_amt);
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if (shift_amt) {
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/* Set signedness bit (MSB of result). */
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emit_alu(nfp_prog, reg_none(), reg_a(dst), ALU_OP_OR,
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reg_imm(0));
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emit_shf(nfp_prog, reg_both(dst), reg_none(), SHF_OP_ASHR,
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reg_b(dst), SHF_SC_R_SHF, shift_amt);
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}
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wrp_immed(nfp_prog, reg_both(dst + 1), 0);
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return 0;
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@ -2429,18 +2441,75 @@ static int ashr_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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return __ashr_imm(nfp_prog, dst, insn->imm);
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}
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static int __shr_imm(struct nfp_prog *nfp_prog, u8 dst, u8 shift_amt)
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{
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if (shift_amt)
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emit_shf(nfp_prog, reg_both(dst), reg_none(), SHF_OP_NONE,
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reg_b(dst), SHF_SC_R_SHF, shift_amt);
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wrp_immed(nfp_prog, reg_both(dst + 1), 0);
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return 0;
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}
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static int shr_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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{
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const struct bpf_insn *insn = &meta->insn;
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u8 dst = insn->dst_reg * 2;
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return __shr_imm(nfp_prog, dst, insn->imm);
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}
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static int shr_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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{
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const struct bpf_insn *insn = &meta->insn;
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u64 umin, umax;
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u8 dst, src;
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dst = insn->dst_reg * 2;
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umin = meta->umin_src;
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umax = meta->umax_src;
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if (umin == umax)
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return __shr_imm(nfp_prog, dst, umin);
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src = insn->src_reg * 2;
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emit_alu(nfp_prog, reg_none(), reg_a(src), ALU_OP_OR, reg_imm(0));
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emit_shf_indir(nfp_prog, reg_both(dst), reg_none(), SHF_OP_NONE,
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reg_b(dst), SHF_SC_R_SHF);
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wrp_immed(nfp_prog, reg_both(dst + 1), 0);
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return 0;
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}
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static int __shl_imm(struct nfp_prog *nfp_prog, u8 dst, u8 shift_amt)
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{
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if (shift_amt)
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emit_shf(nfp_prog, reg_both(dst), reg_none(), SHF_OP_NONE,
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reg_b(dst), SHF_SC_L_SHF, shift_amt);
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wrp_immed(nfp_prog, reg_both(dst + 1), 0);
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return 0;
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}
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static int shl_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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{
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const struct bpf_insn *insn = &meta->insn;
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u8 dst = insn->dst_reg * 2;
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if (!insn->imm)
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return 1; /* TODO: zero shift means indirect */
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return __shl_imm(nfp_prog, dst, insn->imm);
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}
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emit_shf(nfp_prog, reg_both(insn->dst_reg * 2),
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reg_none(), SHF_OP_NONE, reg_b(insn->dst_reg * 2),
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SHF_SC_L_SHF, insn->imm);
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wrp_immed(nfp_prog, reg_both(insn->dst_reg * 2 + 1), 0);
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static int shl_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
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{
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const struct bpf_insn *insn = &meta->insn;
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u64 umin, umax;
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u8 dst, src;
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dst = insn->dst_reg * 2;
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umin = meta->umin_src;
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umax = meta->umax_src;
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if (umin == umax)
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return __shl_imm(nfp_prog, dst, umin);
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src = insn->src_reg * 2;
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shl_reg64_lt32_low(nfp_prog, dst, src);
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wrp_immed(nfp_prog, reg_both(dst + 1), 0);
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return 0;
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}
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@ -3350,7 +3419,10 @@ static const instr_cb_t instr_cb[256] = {
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[BPF_ALU | BPF_DIV | BPF_X] = div_reg,
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[BPF_ALU | BPF_DIV | BPF_K] = div_imm,
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[BPF_ALU | BPF_NEG] = neg_reg,
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[BPF_ALU | BPF_LSH | BPF_X] = shl_reg,
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[BPF_ALU | BPF_LSH | BPF_K] = shl_imm,
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[BPF_ALU | BPF_RSH | BPF_X] = shr_reg,
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[BPF_ALU | BPF_RSH | BPF_K] = shr_imm,
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[BPF_ALU | BPF_ARSH | BPF_X] = ashr_reg,
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[BPF_ALU | BPF_ARSH | BPF_K] = ashr_imm,
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[BPF_ALU | BPF_END | BPF_X] = end_reg32,
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