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drm fixes for 6.8

Browse Source 
qaic:
 - fix GEM import
 - add quirk for soc version
 
 bridge:
 - parade-ps8640, ti-sn65dsi86: fix aux reads bounds
 
 mgag200:
 - fix gamma LUT init
 
 i915:
 - Fix bogus DPCD rev usage for DP phy test pattern setup
 - Fix handling of MMIO triggered reports in the OA buffer
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Merge tag 'drm-fixes-2024-01-04' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "These were from over the holiday period, mainly i915, a couple of
  qaic, bridge and an mgag200.

  qaic:
   - fix GEM import
   - add quirk for soc version

  bridge:
   - parade-ps8640, ti-sn65dsi86: fix aux reads bounds

  mgag200:
   - fix gamma LUT init

  i915:
   - Fix bogus DPCD rev usage for DP phy test pattern setup
   - Fix handling of MMIO triggered reports in the OA buffer"

* tag 'drm-fixes-2024-01-04' of git://anongit.freedesktop.org/drm/drm:
  drm/i915/perf: Update handling of MMIO triggered reports
  drm/i915/dp: Fix passing the correct DPCD_REV for drm_dp_set_phy_test_pattern
  drm/mgag200: Fix gamma lut not initialized for G200ER, G200EV, G200SE
  drm/bridge: ps8640: Fix size mismatch warning w/ len
  drm/bridge: ti-sn65dsi86: Never store more than msg->size bytes in AUX xfer
  drm/bridge: parade-ps8640: Never store more than msg->size bytes in AUX xfer
  accel/qaic: Implement quirk for SOC_HW_VERSION
  accel/qaic: Fix GEM import path code
This commit is contained in:
Linus Torvalds 2024-01-04 10:48:03 -08:00
commit 5939a693dc
11 changed files with 83 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/accel/qaic/mhi_controller.c
View File

@ -404,8 +404,21 @@ static struct mhi_controller_config aic100_config = {
static int mhi_read_reg(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 *out)
{
u32 tmp = readl_relaxed(addr);
u32 tmp;
/*
* SOC_HW_VERSION quirk
* The SOC_HW_VERSION register (offset 0x224) is not reliable and
* may contain uninitialized values, including 0xFFFFFFFF. This could
* cause a false positive link down error. Instead, intercept any
* reads and provide the correct value of the register.
*/
if (addr - mhi_cntrl->regs == 0x224) {
*out = 0x60110200;
return 0;
}
tmp = readl_relaxed(addr);
if (tmp == U32_MAX)
return -EIO;

6
drivers/accel/qaic/qaic_data.c
View File

@ -777,7 +777,6 @@ struct drm_gem_object *qaic_gem_prime_import(struct drm_device *dev, struct dma_
struct dma_buf_attachment *attach;
struct drm_gem_object *obj;
struct qaic_bo *bo;
size_t size;
int ret;
bo = qaic_alloc_init_bo();
@ -795,13 +794,12 @@ struct drm_gem_object *qaic_gem_prime_import(struct drm_device *dev, struct dma_
goto attach_fail;
}
size = PAGE_ALIGN(attach->dmabuf->size);
if (size == 0) {
if (!attach->dmabuf->size) {
ret = -EINVAL;
goto size_align_fail;
}
drm_gem_private_object_init(dev, obj, size);
drm_gem_private_object_init(dev, obj, attach->dmabuf->size);
/*
* skipping dma_buf_map_attachment() as we do not know the direction
* just yet. Once the direction is known in the subsequent IOCTL to

5
drivers/gpu/drm/bridge/parade-ps8640.c
View File

@ -210,7 +210,7 @@ static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux,
struct ps8640 *ps_bridge = aux_to_ps8640(aux);
struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL];
struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
unsigned int len = msg->size;
size_t len = msg->size;
unsigned int data;
unsigned int base;
int ret;
@ -330,11 +330,12 @@ static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux,
return ret;
}
if (i < msg->size)
buf[i] = data;
}
}
return len;
return min(len, msg->size);
}
static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux,

4
drivers/gpu/drm/bridge/ti-sn65dsi86.c
View File

@ -527,6 +527,7 @@ static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
u32 request_val = AUX_CMD_REQ(msg->request);
u8 *buf = msg->buffer;
unsigned int len = msg->size;
unsigned int short_len;
unsigned int val;
int ret;
u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
@ -600,7 +601,8 @@ static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
}
if (val & AUX_IRQ_STATUS_AUX_SHORT) {
ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &len);
ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &short_len);
len = min(len, short_len);
if (ret)
goto exit;
} else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) {

2
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -4496,7 +4496,7 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
intel_dp->train_set, crtc_state->lane_count);
drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
link_status[DP_DPCD_REV]);
intel_dp->dpcd[DP_DPCD_REV]);
}
static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)

39
drivers/gpu/drm/i915/i915_perf.c
View File

@ -772,10 +772,6 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
* The reason field includes flags identifying what
* triggered this specific report (mostly timer
* triggered or e.g. due to a context switch).
*
* In MMIO triggered reports, some platforms do not set the
* reason bit in this field and it is valid to have a reason
* field of zero.
*/
reason = oa_report_reason(stream, report);
ctx_id = oa_context_id(stream, report32);
@ -787,8 +783,41 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
*
* Note: that we don't clear the valid_ctx_bit so userspace can
* understand that the ID has been squashed by the kernel.
*
* Update:
*
* On XEHP platforms the behavior of context id valid bit has
* changed compared to prior platforms. To describe this, we
* define a few terms:
*
* context-switch-report: This is a report with the reason type
* being context-switch. It is generated when a context switches
* out.
*
* context-valid-bit: A bit that is set in the report ID field
* to indicate that a valid context has been loaded.
*
* gpu-idle: A condition characterized by a
* context-switch-report with context-valid-bit set to 0.
*
* On prior platforms, context-id-valid bit is set to 0 only
* when GPU goes idle. In all other reports, it is set to 1.
*
* On XEHP platforms, context-valid-bit is set to 1 in a context
* switch report if a new context switched in. For all other
* reports it is set to 0.
*
* This change in behavior causes an issue with MMIO triggered
* reports. MMIO triggered reports have the markers in the
* context ID field and the context-valid-bit is 0. The logic
* below to squash the context ID would render the report
* useless since the user will not be able to find it in the OA
* buffer. Since MMIO triggered reports exist only on XEHP,
* we should avoid squashing these for XEHP platforms.
*/
if (oa_report_ctx_invalid(stream, report)) {
if (oa_report_ctx_invalid(stream, report) &&
GRAPHICS_VER_FULL(stream->engine->i915) < IP_VER(12, 50)) {
ctx_id = INVALID_CTX_ID;
oa_context_id_squash(stream, report32);
}

5
drivers/gpu/drm/mgag200/mgag200_drv.h
View File

@ -392,6 +392,11 @@ void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane,
.destroy = drm_plane_cleanup, \
DRM_GEM_SHADOW_PLANE_FUNCS
void mgag200_crtc_set_gamma_linear(struct mga_device *mdev, const struct drm_format_info *format);
void mgag200_crtc_set_gamma(struct mga_device *mdev,
const struct drm_format_info *format,
struct drm_color_lut *lut);
enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc,
const struct drm_display_mode *mode);
int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state);

5
drivers/gpu/drm/mgag200/mgag200_g200er.c
View File

@ -202,6 +202,11 @@ static void mgag200_g200er_crtc_helper_atomic_enable(struct drm_crtc *crtc,
mgag200_g200er_reset_tagfifo(mdev);
if (crtc_state->gamma_lut)
mgag200_crtc_set_gamma(mdev, format, crtc_state->gamma_lut->data);
else
mgag200_crtc_set_gamma_linear(mdev, format);
mgag200_enable_display(mdev);
if (funcs->enable_vidrst)

5
drivers/gpu/drm/mgag200/mgag200_g200ev.c
View File

@ -203,6 +203,11 @@ static void mgag200_g200ev_crtc_helper_atomic_enable(struct drm_crtc *crtc,
mgag200_g200ev_set_hiprilvl(mdev);
if (crtc_state->gamma_lut)
mgag200_crtc_set_gamma(mdev, format, crtc_state->gamma_lut->data);
else
mgag200_crtc_set_gamma_linear(mdev, format);
mgag200_enable_display(mdev);
if (funcs->enable_vidrst)

5
drivers/gpu/drm/mgag200/mgag200_g200se.c
View File

@ -334,6 +334,11 @@ static void mgag200_g200se_crtc_helper_atomic_enable(struct drm_crtc *crtc,
mgag200_g200se_set_hiprilvl(mdev, adjusted_mode, format);
if (crtc_state->gamma_lut)
mgag200_crtc_set_gamma(mdev, format, crtc_state->gamma_lut->data);
else
mgag200_crtc_set_gamma_linear(mdev, format);
mgag200_enable_display(mdev);
if (funcs->enable_vidrst)

4
drivers/gpu/drm/mgag200/mgag200_mode.c
View File

@ -28,7 +28,7 @@
* This file contains setup code for the CRTC.
*/
static void mgag200_crtc_set_gamma_linear(struct mga_device *mdev,
void mgag200_crtc_set_gamma_linear(struct mga_device *mdev,
const struct drm_format_info *format)
{
int i;
@ -65,7 +65,7 @@ static void mgag200_crtc_set_gamma_linear(struct mga_device *mdev,
}
}
static void mgag200_crtc_set_gamma(struct mga_device *mdev,
void mgag200_crtc_set_gamma(struct mga_device *mdev,
const struct drm_format_info *format,
struct drm_color_lut *lut)
{