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RISC-V Patches for 4.20-rc2
This pull request contains a for unrelated patches that fix various issues in the RISC-V port: * A patch that enables printk timestamps in the RISC-V defconfig. * A whitespace fix to "struct pt_regs". * A patch that adds a "vdso_install" target for RISC-V. * A pair of build fixes: one to fix a typo in our makefile, and one to clean up some warnings. There will probably be more patches from us for 4.20, but I don't have anything that's ready to go right now so I'm going to hold off a bit. Right now the only concrete thing I know I want to make sure gets sorted out is our 32-bit stat interface, which I don't want sitting in limbo for another cycle as we have to get RV32I glibc sone. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEAM520YNJYN/OiG3470yhUCzLq0EFAlvrBuYTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRDvTKFQLMurQXe+D/0bR8OPyYdKjAaS08pbFaa+LCyvEqm+ cXJzzY1dLL2VUe3EHP907qgBRY1A1jMrk0P3WtID28lUioDwJ6qmS7zn5+QLpoMs U5LQX6DCkF/Y3a1rMrt6Roqpp9f2AVKqnU3/rkzkquB8JGc/iv1hKlAWJL+7MYV3 LmgFhZMXC7B3oabKiy6NVqPB5c4WX2854bW7uzxTxbxEMxJNtYuzgBXFNqZB2Szn vr3KarQU1oMwL4eboN5wiwHdJifiFOvHGpcJktNH8yBWDWmXhDh9/UWp7piN4bds 09ESHFdxjYtvI+sG9mPCjQFzI5vGV6Pw0M1hBL5DP6tXPwu3cb0e/DugBuGFUWzD GtrXLE89SWiwEEkJkEV3W9BOpaRvfrONZZKrq3RW/NgdVHD1r06oT9+sK2AosFEE vgu4bDbdJKXiBbPPCKPaGUzvVPsPbbG7HUab2/lagNX9opleAX9pGDlFUxsicKgC 7XGcwVut39Vt54SEC0aRYK/KYV1aEOP7pKzVLVkkwJUvNR2uksnZpr/vHXn/NW77 7Oq7icJhYerysD3UDEf3u2NdAXJUFB39dCntCbNx2qWHwJfmNZjRLmFCTB7185he EqFekd8easxMNd4Sok1CJ/Gdsp+rNbxkirI6Z6ay47azXaRog90zL8uW3xN92zgI jNErjZym0j24tg== =62VX -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-4.20-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux Pull RISC-V fixes from Palmer Dabbelt: "This contains a few patches that fix various issues in the RISC-V port: - enable printk timestamps in the RISC-V defconfig. - a whitespace fix to "struct pt_regs". - add a "vdso_install" target for RISC-V. - a pair of build fixes: one to fix a typo in our makefile, and one to clean up some warnings. There will probably be more patches from us for 4.20, but I don't have anything that's ready to go right now so I'm going to hold off a bit. Right now the only concrete thing I know I want to make sure gets sorted out is our 32-bit stat interface, which I don't want sitting in limbo for another cycle as we have to get RV32I glibc sone" * tag 'riscv-for-linus-4.20-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux: RISC-V: Silence some module warnings on 32-bit RISC-V: lib: Fix build error for 64-bit riscv: add missing vdso_install target riscv: fix spacing in struct pt_regs RISC-V: defconfig: Enable printk timestamps
This commit is contained in:
commit
5929a1f0ff
@ -77,4 +77,8 @@ core-y += arch/riscv/kernel/ arch/riscv/mm/
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libs-y += arch/riscv/lib/
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libs-y += arch/riscv/lib/
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PHONY += vdso_install
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vdso_install:
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$(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso $@
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all: vmlinux
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all: vmlinux
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@ -76,4 +76,5 @@ CONFIG_NFS_V4_1=y
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CONFIG_NFS_V4_2=y
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CONFIG_NFS_V4_2=y
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CONFIG_ROOT_NFS=y
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CONFIG_ROOT_NFS=y
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CONFIG_CRYPTO_USER_API_HASH=y
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CONFIG_CRYPTO_USER_API_HASH=y
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CONFIG_PRINTK_TIME=y
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# CONFIG_RCU_TRACE is not set
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# CONFIG_RCU_TRACE is not set
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@ -21,7 +21,7 @@ static int apply_r_riscv_32_rela(struct module *me, u32 *location, Elf_Addr v)
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{
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{
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if (v != (u32)v) {
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if (v != (u32)v) {
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pr_err("%s: value %016llx out of range for 32-bit field\n",
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pr_err("%s: value %016llx out of range for 32-bit field\n",
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me->name, v);
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me->name, (long long)v);
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return -EINVAL;
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return -EINVAL;
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}
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}
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*location = v;
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*location = v;
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@ -102,7 +102,7 @@ static int apply_r_riscv_pcrel_hi20_rela(struct module *me, u32 *location,
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if (offset != (s32)offset) {
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if (offset != (s32)offset) {
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pr_err(
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pr_err(
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"%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n",
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"%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n",
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me->name, v, location);
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me->name, (long long)v, location);
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return -EINVAL;
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return -EINVAL;
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}
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}
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@ -144,7 +144,7 @@ static int apply_r_riscv_hi20_rela(struct module *me, u32 *location,
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if (IS_ENABLED(CMODEL_MEDLOW)) {
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if (IS_ENABLED(CMODEL_MEDLOW)) {
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pr_err(
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pr_err(
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"%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n",
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"%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n",
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me->name, v, location);
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me->name, (long long)v, location);
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return -EINVAL;
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return -EINVAL;
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}
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}
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@ -188,7 +188,7 @@ static int apply_r_riscv_got_hi20_rela(struct module *me, u32 *location,
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} else {
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} else {
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pr_err(
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pr_err(
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"%s: can not generate the GOT entry for symbol = %016llx from PC = %p\n",
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"%s: can not generate the GOT entry for symbol = %016llx from PC = %p\n",
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me->name, v, location);
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me->name, (long long)v, location);
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return -EINVAL;
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return -EINVAL;
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}
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}
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@ -212,7 +212,7 @@ static int apply_r_riscv_call_plt_rela(struct module *me, u32 *location,
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} else {
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} else {
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pr_err(
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pr_err(
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"%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n",
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"%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n",
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me->name, v, location);
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me->name, (long long)v, location);
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return -EINVAL;
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return -EINVAL;
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}
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}
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}
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}
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@ -234,7 +234,7 @@ static int apply_r_riscv_call_rela(struct module *me, u32 *location,
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if (offset != fill_v) {
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if (offset != fill_v) {
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pr_err(
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pr_err(
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"%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n",
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"%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n",
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me->name, v, location);
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me->name, (long long)v, location);
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return -EINVAL;
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return -EINVAL;
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}
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}
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@ -3,6 +3,6 @@ lib-y += memcpy.o
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lib-y += memset.o
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lib-y += memset.o
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lib-y += uaccess.o
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lib-y += uaccess.o
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lib-(CONFIG_64BIT) += tishift.o
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lib-$(CONFIG_64BIT) += tishift.o
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lib-$(CONFIG_32BIT) += udivdi3.o
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lib-$(CONFIG_32BIT) += udivdi3.o
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