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clk: ti: move OMAP4+ DPLL implementation under drivers/clk
With the legacy clock support gone, the OMAP4 specific DPLL implementations can be moved under the clock driver. Change some of the function prototypes to be static at the same time, and remove some exports from the global TI clock driver header. Signed-off-by: Tero Kristo <t-kristo@ti.com>
This commit is contained in:
Tero Kristo
parent
b138b0283d
commit
59245ce01a
@ -193,12 +193,12 @@ obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
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obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
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obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
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obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o
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obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
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obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
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obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
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obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o
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obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
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obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o
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obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o
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obj-$(CONFIG_SOC_AM43XX) += $(clock-common) dpll3xxx.o
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# OMAP2 clock rate set data (old "OPP" data)
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@ -183,8 +183,6 @@ struct clksel {
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u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
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void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
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void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
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void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
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void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
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void __init omap2_clk_disable_clkdm_control(void);
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@ -204,8 +202,6 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
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extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
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extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
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unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
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void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
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void __iomem **other_reg,
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u8 *other_bit);
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@ -7,10 +7,10 @@ obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o
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obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
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clk-3xxx.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o
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obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o dpll44xx.o
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obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o dpll44xx.o
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obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
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clk-dra7-atl.o
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clk-dra7-atl.o dpll44xx.o
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obj-$(CONFIG_SOC_AM43XX) += $(clk-common) clk-43xx.o
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ifdef CONFIG_ATAGS
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@ -169,6 +169,20 @@ void ti_clk_patch_legacy_clks(struct ti_clk **patch);
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struct clk *ti_clk_register_clk(struct ti_clk *setup);
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int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
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extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
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u8 omap2_init_dpll_parent(struct clk_hw *hw);
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unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
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unsigned long target_rate,
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unsigned long *parent_rate);
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long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long min_rate,
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unsigned long max_rate,
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unsigned long *best_parent_rate,
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struct clk_hw **best_parent_clk);
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#endif
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@ -14,6 +14,7 @@
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/clk/ti.h>
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#include "clock.h"
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@ -29,14 +30,14 @@
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/*
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* Bitfield declarations
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*/
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#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
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#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
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#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
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#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BIT(8)
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#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BIT(10)
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#define OMAP4430_DPLL_REGM4XEN_MASK BIT(11)
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/* Static rate multiplier for OMAP4 REGM4XEN clocks */
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#define OMAP4430_REGM4XEN_MULT 4
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void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
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static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
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{
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u32 v;
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u32 mask;
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@ -48,13 +49,13 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
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OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
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OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
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v = omap2_clk_readl(clk, clk->clksel_reg);
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v = ti_clk_ll_ops->clk_readl(clk->clksel_reg);
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/* Clear the bit to allow gatectrl */
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v &= ~mask;
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omap2_clk_writel(v, clk, clk->clksel_reg);
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ti_clk_ll_ops->clk_writel(v, clk->clksel_reg);
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}
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void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
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static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
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{
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u32 v;
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u32 mask;
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@ -66,10 +67,10 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
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OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
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OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
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v = omap2_clk_readl(clk, clk->clksel_reg);
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v = ti_clk_ll_ops->clk_readl(clk->clksel_reg);
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/* Set the bit to deny gatectrl */
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v |= mask;
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omap2_clk_writel(v, clk, clk->clksel_reg);
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ti_clk_ll_ops->clk_writel(v, clk->clksel_reg);
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}
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const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
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@ -112,7 +113,7 @@ static void omap4_dpll_lpmode_recalc(struct dpll_data *dd)
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* upon success, or 0 upon error.
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*/
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unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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unsigned long parent_rate)
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{
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struct clk_hw_omap *clk = to_clk_hw_omap(hw);
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u32 v;
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@ -127,7 +128,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
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rate = omap2_get_dpll_rate(clk);
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/* regm4xen adds a multiplier of 4 to DPLL calculations */
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v = omap2_clk_readl(clk, dd->control_reg);
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v = ti_clk_ll_ops->clk_readl(dd->control_reg);
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if (v & OMAP4430_DPLL_REGM4XEN_MASK)
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rate *= OMAP4430_REGM4XEN_MULT;
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@ -275,17 +275,6 @@ long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
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unsigned long max_rate,
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unsigned long *best_parent_rate,
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struct clk_hw **best_parent_clk);
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unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
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unsigned long target_rate,
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unsigned long *parent_rate);
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long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long min_rate,
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unsigned long max_rate,
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unsigned long *best_parent_rate,
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struct clk_hw **best_parent_clk);
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unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
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long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
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unsigned long *parent_rate);
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@ -314,6 +303,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
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unsigned long parent_rate);
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void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
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void omap2xxx_clkt_vps_init(void);
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unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
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void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
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void ti_dt_clocks_register(struct ti_dt_clk *oclks);
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@ -364,7 +354,6 @@ static inline void of_ti_clk_deny_autoidle_all(void) { }
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extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
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extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
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extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
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extern const struct clk_hw_omap_ops clkhwops_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
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extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
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