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Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, cacheinfo: Enable L3 CID only on AMD x86, cacheinfo: Remove NUMA dependency, fix for AMD Fam10h rev D1 x86, cpu: Print AMD virtualization features in /proc/cpuinfo x86, cacheinfo: Calculate L3 indices x86, cacheinfo: Add cache index disable sysfs attrs only to L3 caches x86, cacheinfo: Fix disabling of L3 cache indices intel-agp: Switch to wbinvd_on_all_cpus x86, lib: Add wbinvd smp helpers
This commit is contained in:
Linus Torvalds
commit
58f02db466
@ -168,6 +168,10 @@
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#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
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#define X86_FEATURE_EPT (8*32+ 3) /* Intel Extended Page Table */
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#define X86_FEATURE_VPID (8*32+ 4) /* Intel Virtual Processor ID */
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#define X86_FEATURE_NPT (8*32+5) /* AMD Nested Page Table support */
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#define X86_FEATURE_LBRV (8*32+6) /* AMD LBR Virtualization support */
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#define X86_FEATURE_SVML (8*32+7) /* "svm_lock" AMD SVM locking MSR */
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#define X86_FEATURE_NRIPS (8*32+8) /* "nrip_save" AMD SVM next_rip save */
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#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
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@ -135,6 +135,8 @@ int native_cpu_disable(void);
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void native_cpu_die(unsigned int cpu);
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void native_play_dead(void);
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void play_dead_common(void);
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void wbinvd_on_cpu(int cpu);
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int wbinvd_on_all_cpus(void);
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void native_send_call_func_ipi(const struct cpumask *mask);
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void native_send_call_func_single_ipi(int cpu);
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@ -147,6 +149,13 @@ static inline int num_booting_cpus(void)
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{
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return cpumask_weight(cpu_callout_mask);
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}
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#else /* !CONFIG_SMP */
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#define wbinvd_on_cpu(cpu) wbinvd()
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static inline int wbinvd_on_all_cpus(void)
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{
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wbinvd();
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return 0;
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}
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#endif /* CONFIG_SMP */
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extern unsigned disabled_cpus __cpuinitdata;
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@ -32,6 +32,10 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
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static const struct cpuid_bit __cpuinitconst cpuid_bits[] = {
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{ X86_FEATURE_IDA, CR_EAX, 1, 0x00000006 },
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{ X86_FEATURE_ARAT, CR_EAX, 2, 0x00000006 },
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{ X86_FEATURE_NPT, CR_EDX, 0, 0x8000000a },
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{ X86_FEATURE_LBRV, CR_EDX, 1, 0x8000000a },
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{ X86_FEATURE_SVML, CR_EDX, 2, 0x8000000a },
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{ X86_FEATURE_NRIPS, CR_EDX, 3, 0x8000000a },
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{ 0, 0, 0, 0 }
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};
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@ -18,6 +18,7 @@
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#include <asm/processor.h>
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#include <linux/smp.h>
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#include <asm/k8.h>
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#include <asm/smp.h>
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#define LVL_1_INST 1
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#define LVL_1_DATA 2
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@ -152,7 +153,8 @@ struct _cpuid4_info {
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union _cpuid4_leaf_ebx ebx;
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union _cpuid4_leaf_ecx ecx;
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unsigned long size;
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unsigned long can_disable;
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bool can_disable;
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unsigned int l3_indices;
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DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
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};
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@ -162,7 +164,8 @@ struct _cpuid4_info_regs {
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union _cpuid4_leaf_ebx ebx;
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union _cpuid4_leaf_ecx ecx;
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unsigned long size;
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unsigned long can_disable;
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bool can_disable;
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unsigned int l3_indices;
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};
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unsigned short num_cache_leaves;
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@ -292,6 +295,36 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
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(ebx->split.ways_of_associativity + 1) - 1;
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}
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struct _cache_attr {
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struct attribute attr;
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ssize_t (*show)(struct _cpuid4_info *, char *);
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ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
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};
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#ifdef CONFIG_CPU_SUP_AMD
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static unsigned int __cpuinit amd_calc_l3_indices(void)
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{
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/*
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* We're called over smp_call_function_single() and therefore
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* are on the correct cpu.
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*/
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int cpu = smp_processor_id();
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int node = cpu_to_node(cpu);
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struct pci_dev *dev = node_to_k8_nb_misc(node);
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unsigned int sc0, sc1, sc2, sc3;
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u32 val = 0;
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pci_read_config_dword(dev, 0x1C4, &val);
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/* calculate subcache sizes */
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sc0 = !(val & BIT(0));
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sc1 = !(val & BIT(4));
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sc2 = !(val & BIT(8)) + !(val & BIT(9));
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sc3 = !(val & BIT(12)) + !(val & BIT(13));
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return (max(max(max(sc0, sc1), sc2), sc3) << 10) - 1;
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}
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static void __cpuinit
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amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
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{
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@ -301,13 +334,104 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
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if (boot_cpu_data.x86 == 0x11)
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return;
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/* see erratum #382 */
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if ((boot_cpu_data.x86 == 0x10) && (boot_cpu_data.x86_model < 0x8))
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/* see errata #382 and #388 */
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if ((boot_cpu_data.x86 == 0x10) &&
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((boot_cpu_data.x86_model < 0x8) ||
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(boot_cpu_data.x86_mask < 0x1)))
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return;
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this_leaf->can_disable = 1;
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this_leaf->can_disable = true;
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this_leaf->l3_indices = amd_calc_l3_indices();
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}
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static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
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unsigned int index)
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{
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int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
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int node = amd_get_nb_id(cpu);
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struct pci_dev *dev = node_to_k8_nb_misc(node);
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unsigned int reg = 0;
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if (!this_leaf->can_disable)
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return -EINVAL;
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if (!dev)
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return -EINVAL;
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pci_read_config_dword(dev, 0x1BC + index * 4, ®);
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return sprintf(buf, "0x%08x\n", reg);
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}
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#define SHOW_CACHE_DISABLE(index) \
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static ssize_t \
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show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf) \
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{ \
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return show_cache_disable(this_leaf, buf, index); \
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}
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SHOW_CACHE_DISABLE(0)
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SHOW_CACHE_DISABLE(1)
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static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
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const char *buf, size_t count, unsigned int index)
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{
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int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
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int node = amd_get_nb_id(cpu);
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struct pci_dev *dev = node_to_k8_nb_misc(node);
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unsigned long val = 0;
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#define SUBCACHE_MASK (3UL << 20)
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#define SUBCACHE_INDEX 0xfff
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if (!this_leaf->can_disable)
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return -EINVAL;
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if (!capable(CAP_SYS_ADMIN))
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return -EPERM;
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if (!dev)
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return -EINVAL;
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if (strict_strtoul(buf, 10, &val) < 0)
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return -EINVAL;
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/* do not allow writes outside of allowed bits */
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if ((val & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
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((val & SUBCACHE_INDEX) > this_leaf->l3_indices))
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return -EINVAL;
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val |= BIT(30);
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pci_write_config_dword(dev, 0x1BC + index * 4, val);
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/*
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* We need to WBINVD on a core on the node containing the L3 cache which
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* indices we disable therefore a simple wbinvd() is not sufficient.
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*/
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wbinvd_on_cpu(cpu);
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pci_write_config_dword(dev, 0x1BC + index * 4, val | BIT(31));
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return count;
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}
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#define STORE_CACHE_DISABLE(index) \
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static ssize_t \
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store_cache_disable_##index(struct _cpuid4_info *this_leaf, \
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const char *buf, size_t count) \
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{ \
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return store_cache_disable(this_leaf, buf, count, index); \
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}
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STORE_CACHE_DISABLE(0)
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STORE_CACHE_DISABLE(1)
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static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
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show_cache_disable_0, store_cache_disable_0);
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static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
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show_cache_disable_1, store_cache_disable_1);
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#else /* CONFIG_CPU_SUP_AMD */
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static void __cpuinit
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amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
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{
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};
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#endif /* CONFIG_CPU_SUP_AMD */
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static int
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__cpuinit cpuid4_cache_lookup_regs(int index,
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struct _cpuid4_info_regs *this_leaf)
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@ -713,82 +837,6 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
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#define to_object(k) container_of(k, struct _index_kobject, kobj)
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#define to_attr(a) container_of(a, struct _cache_attr, attr)
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static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
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unsigned int index)
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{
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int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
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int node = cpu_to_node(cpu);
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struct pci_dev *dev = node_to_k8_nb_misc(node);
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unsigned int reg = 0;
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if (!this_leaf->can_disable)
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return -EINVAL;
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if (!dev)
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return -EINVAL;
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pci_read_config_dword(dev, 0x1BC + index * 4, ®);
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return sprintf(buf, "%x\n", reg);
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}
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#define SHOW_CACHE_DISABLE(index) \
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static ssize_t \
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show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf) \
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{ \
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return show_cache_disable(this_leaf, buf, index); \
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}
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SHOW_CACHE_DISABLE(0)
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SHOW_CACHE_DISABLE(1)
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static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
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const char *buf, size_t count, unsigned int index)
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{
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int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
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int node = cpu_to_node(cpu);
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struct pci_dev *dev = node_to_k8_nb_misc(node);
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unsigned long val = 0;
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unsigned int scrubber = 0;
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if (!this_leaf->can_disable)
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return -EINVAL;
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if (!capable(CAP_SYS_ADMIN))
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return -EPERM;
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if (!dev)
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return -EINVAL;
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if (strict_strtoul(buf, 10, &val) < 0)
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return -EINVAL;
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val |= 0xc0000000;
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pci_read_config_dword(dev, 0x58, &scrubber);
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scrubber &= ~0x1f000000;
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pci_write_config_dword(dev, 0x58, scrubber);
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pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
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wbinvd();
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pci_write_config_dword(dev, 0x1BC + index * 4, val);
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return count;
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}
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#define STORE_CACHE_DISABLE(index) \
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static ssize_t \
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store_cache_disable_##index(struct _cpuid4_info *this_leaf, \
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const char *buf, size_t count) \
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{ \
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return store_cache_disable(this_leaf, buf, count, index); \
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}
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STORE_CACHE_DISABLE(0)
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STORE_CACHE_DISABLE(1)
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struct _cache_attr {
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struct attribute attr;
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ssize_t (*show)(struct _cpuid4_info *, char *);
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ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
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};
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#define define_one_ro(_name) \
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static struct _cache_attr _name = \
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__ATTR(_name, 0444, show_##_name, NULL)
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@ -803,23 +851,28 @@ define_one_ro(size);
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define_one_ro(shared_cpu_map);
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define_one_ro(shared_cpu_list);
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static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
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show_cache_disable_0, store_cache_disable_0);
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static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
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show_cache_disable_1, store_cache_disable_1);
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#define DEFAULT_SYSFS_CACHE_ATTRS \
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&type.attr, \
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&level.attr, \
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&coherency_line_size.attr, \
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&physical_line_partition.attr, \
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&ways_of_associativity.attr, \
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&number_of_sets.attr, \
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&size.attr, \
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&shared_cpu_map.attr, \
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&shared_cpu_list.attr
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static struct attribute *default_attrs[] = {
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&type.attr,
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&level.attr,
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&coherency_line_size.attr,
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&physical_line_partition.attr,
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&ways_of_associativity.attr,
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&number_of_sets.attr,
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&size.attr,
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&shared_cpu_map.attr,
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&shared_cpu_list.attr,
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DEFAULT_SYSFS_CACHE_ATTRS,
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NULL
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};
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static struct attribute *default_l3_attrs[] = {
|
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DEFAULT_SYSFS_CACHE_ATTRS,
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#ifdef CONFIG_CPU_SUP_AMD
|
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&cache_disable_0.attr,
|
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&cache_disable_1.attr,
|
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#endif
|
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NULL
|
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};
|
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@ -910,6 +963,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
|
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unsigned int cpu = sys_dev->id;
|
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unsigned long i, j;
|
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struct _index_kobject *this_object;
|
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struct _cpuid4_info *this_leaf;
|
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int retval;
|
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|
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retval = cpuid4_cache_sysfs_init(cpu);
|
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@ -928,6 +982,14 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
|
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this_object = INDEX_KOBJECT_PTR(cpu, i);
|
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this_object->cpu = cpu;
|
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this_object->index = i;
|
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|
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this_leaf = CPUID4_INFO_IDX(cpu, i);
|
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|
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if (this_leaf->can_disable)
|
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ktype_cache.default_attrs = default_l3_attrs;
|
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else
|
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ktype_cache.default_attrs = default_attrs;
|
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|
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retval = kobject_init_and_add(&(this_object->kobj),
|
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&ktype_cache,
|
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per_cpu(ici_cache_kobject, cpu),
|
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|
||||
@ -14,7 +14,7 @@ $(obj)/inat.o: $(obj)/inat-tables.c
|
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|
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clean-files := inat-tables.c
|
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|
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obj-$(CONFIG_SMP) += msr-smp.o
|
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obj-$(CONFIG_SMP) += msr-smp.o cache-smp.o
|
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|
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lib-y := delay.o
|
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lib-y += thunk_$(BITS).o
|
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|
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19
arch/x86/lib/cache-smp.c
Normal file
19
arch/x86/lib/cache-smp.c
Normal file
@ -0,0 +1,19 @@
|
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#include <linux/smp.h>
|
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#include <linux/module.h>
|
||||
|
||||
static void __wbinvd(void *dummy)
|
||||
{
|
||||
wbinvd();
|
||||
}
|
||||
|
||||
void wbinvd_on_cpu(int cpu)
|
||||
{
|
||||
smp_call_function_single(cpu, __wbinvd, NULL, 1);
|
||||
}
|
||||
EXPORT_SYMBOL(wbinvd_on_cpu);
|
||||
|
||||
int wbinvd_on_all_cpus(void)
|
||||
{
|
||||
return on_each_cpu(__wbinvd, NULL, 1);
|
||||
}
|
||||
EXPORT_SYMBOL(wbinvd_on_all_cpus);
|
||||
@ -8,6 +8,7 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pagemap.h>
|
||||
#include <linux/agp_backend.h>
|
||||
#include <asm/smp.h>
|
||||
#include "agp.h"
|
||||
|
||||
/*
|
||||
@ -815,12 +816,6 @@ static void intel_i830_setup_flush(void)
|
||||
intel_i830_fini_flush();
|
||||
}
|
||||
|
||||
static void
|
||||
do_wbinvd(void *null)
|
||||
{
|
||||
wbinvd();
|
||||
}
|
||||
|
||||
/* The chipset_flush interface needs to get data that has already been
|
||||
* flushed out of the CPU all the way out to main memory, because the GPU
|
||||
* doesn't snoop those buffers.
|
||||
@ -837,12 +832,10 @@ static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
|
||||
|
||||
memset(pg, 0, 1024);
|
||||
|
||||
if (cpu_has_clflush) {
|
||||
if (cpu_has_clflush)
|
||||
clflush_cache_range(pg, 1024);
|
||||
} else {
|
||||
if (on_each_cpu(do_wbinvd, NULL, 1) != 0)
|
||||
printk(KERN_ERR "Timed out waiting for cache flush.\n");
|
||||
}
|
||||
else if (wbinvd_on_all_cpus() != 0)
|
||||
printk(KERN_ERR "Timed out waiting for cache flush.\n");
|
||||
}
|
||||
|
||||
/* The intel i830 automatically initializes the agp aperture during POST.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user