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drm/i915/dp: stylistic cleanup around hdcp2_msg_data

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Split struct declaration and array definition. Fix indents and
whitespace. No functional changes.

Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190820134019.13229-1-jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2019-08-20 16:40:15 +03:00
parent ff17501013
commit 57bf7f43ba
1 changed files with 36 additions and 34 deletions
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70
drivers/gpu/drm/i915/display/intel_dp.c
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@ -5812,47 +5812,49 @@ struct hdcp2_dp_errata_stream_type {
u8 stream_type; u8 stream_type;
} __packed; } __packed;
static struct hdcp2_dp_msg_data { struct hdcp2_dp_msg_data {
u8 msg_id; u8 msg_id;
u32 offset; u32 offset;
bool msg_detectable; bool msg_detectable;
u32 timeout; u32 timeout;
u32 timeout2; /* Added for non_paired situation */ u32 timeout2; /* Added for non_paired situation */
} hdcp2_msg_data[] = { };
{HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0},
{HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET, static struct hdcp2_dp_msg_data hdcp2_msg_data[] = {
false, HDCP_2_2_CERT_TIMEOUT_MS, 0}, { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
{HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET, { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
false, 0, 0}, false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
{HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET, { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
false, 0, 0}, false, 0, 0 },
{HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET, { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, false, 0, 0 },
HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS}, { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
{HDCP_2_2_AKE_SEND_PAIRING_INFO, true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true, HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
HDCP_2_2_PAIRING_TIMEOUT_MS, 0}, { HDCP_2_2_AKE_SEND_PAIRING_INFO,
{HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0}, DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
{HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET, HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0}, { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
{HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false, { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
0, 0}, false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
{HDCP_2_2_REP_SEND_RECVID_LIST, { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true, 0, 0 },
HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0}, { HDCP_2_2_REP_SEND_RECVID_LIST,
{HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false, DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
0, 0}, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
{HDCP_2_2_REP_STREAM_MANAGE, { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false, 0, 0 },
0, 0}, { HDCP_2_2_REP_STREAM_MANAGE,
{HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET, DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0}, 0, 0 },
{ HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
/* local define to shovel this through the write_2_2 interface */ /* local define to shovel this through the write_2_2 interface */
#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
{HDCP_2_2_ERRATA_DP_STREAM_TYPE, { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false, DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
0, 0}, 0, 0 },
}; };
static inline static inline
int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,