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[media] drx-j: Don't use CamelCase

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There's no reason at all to use CamelCase here. Convert all of
them to normal case.

Acked-by: Devin Heitmueller <dheitmueller@kernellabs.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
This commit is contained in:
Mauro Carvalho Chehab 2014-01-16 11:24:57 -03:00
parent 7ef66759a3
commit 57afe2f0bb
13 changed files with 6765 additions and 6765 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

64
drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h
View File

@ -48,13 +48,13 @@
#include "bsp_types.h" #include "bsp_types.h"
/* /*
* This structure contains the I2C address, the device ID and a userData pointer. * This structure contains the I2C address, the device ID and a user_data pointer.
* The userData pointer can be used for application specific purposes. * The user_data pointer can be used for application specific purposes.
*/ */
struct i2c_device_addr { struct i2c_device_addr {
u16 i2cAddr; /* The I2C address of the device. */ u16 i2c_addr; /* The I2C address of the device. */
u16 i2cDevId; /* The device identifier. */ u16 i2c_dev_id; /* The device identifier. */
void *userData; /* User data pointer */ void *user_data; /* User data pointer */
}; };
@ -74,44 +74,44 @@ Exported FUNCTIONS
------------------------------------------------------------------------------*/ ------------------------------------------------------------------------------*/
/** /**
* \fn DRXBSP_I2C_Init() * \fn drxbsp_i2c_init()
* \brief Initialize I2C communication module. * \brief Initialize I2C communication module.
* \return DRXStatus_t Return status. * \return drx_status_t Return status.
* \retval DRX_STS_OK Initialization successful. * \retval DRX_STS_OK Initialization successful.
* \retval DRX_STS_ERROR Initialization failed. * \retval DRX_STS_ERROR Initialization failed.
*/ */
DRXStatus_t DRXBSP_I2C_Init(void); drx_status_t drxbsp_i2c_init(void);
/** /**
* \fn DRXBSP_I2C_Term() * \fn drxbsp_i2c_term()
* \brief Terminate I2C communication module. * \brief Terminate I2C communication module.
* \return DRXStatus_t Return status. * \return drx_status_t Return status.
* \retval DRX_STS_OK Termination successful. * \retval DRX_STS_OK Termination successful.
* \retval DRX_STS_ERROR Termination failed. * \retval DRX_STS_ERROR Termination failed.
*/ */
DRXStatus_t DRXBSP_I2C_Term(void); drx_status_t drxbsp_i2c_term(void);
/** /**
* \fn DRXStatus_t DRXBSP_I2C_WriteRead( struct i2c_device_addr *wDevAddr, * \fn drx_status_t drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr,
* u16 wCount, * u16 w_count,
* u8 *wData, * u8 *wData,
* struct i2c_device_addr *rDevAddr, * struct i2c_device_addr *r_dev_addr,
* u16 rCount, * u16 r_count,
* u8 *rData) * u8 *r_data)
* \brief Read and/or write count bytes from I2C bus, store them in data[]. * \brief Read and/or write count bytes from I2C bus, store them in data[].
* \param wDevAddr The device i2c address and the device ID to write to * \param w_dev_addr The device i2c address and the device ID to write to
* \param wCount The number of bytes to write * \param w_count The number of bytes to write
* \param wData The array to write the data to * \param wData The array to write the data to
* \param rDevAddr The device i2c address and the device ID to read from * \param r_dev_addr The device i2c address and the device ID to read from
* \param rCount The number of bytes to read * \param r_count The number of bytes to read
* \param rData The array to read the data from * \param r_data The array to read the data from
* \return DRXStatus_t Return status. * \return drx_status_t Return status.
* \retval DRX_STS_OK Succes. * \retval DRX_STS_OK Succes.
* \retval DRX_STS_ERROR Failure. * \retval DRX_STS_ERROR Failure.
* \retval DRX_STS_INVALID_ARG Parameter 'wcount' is not zero but parameter * \retval DRX_STS_INVALID_ARG Parameter 'wcount' is not zero but parameter
* 'wdata' contains NULL. * 'wdata' contains NULL.
* Idem for 'rcount' and 'rdata'. * Idem for 'rcount' and 'rdata'.
* Both wDevAddr and rDevAddr are NULL. * Both w_dev_addr and r_dev_addr are NULL.
* *
* This function must implement an atomic write and/or read action on the I2C bus * This function must implement an atomic write and/or read action on the I2C bus
* No other process may use the I2C bus when this function is executing. * No other process may use the I2C bus when this function is executing.
@ -121,25 +121,25 @@ Exported FUNCTIONS
* The device ID can be useful if several devices share an I2C address. * The device ID can be useful if several devices share an I2C address.
* It can be used to control a "switch" on the I2C bus to the correct device. * It can be used to control a "switch" on the I2C bus to the correct device.
*/ */
DRXStatus_t DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, drx_status_t drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
u16 wCount, u16 w_count,
u8 *wData, u8 *wData,
struct i2c_device_addr *rDevAddr, struct i2c_device_addr *r_dev_addr,
u16 rCount, u8 *rData); u16 r_count, u8 *r_data);
/** /**
* \fn DRXBSP_I2C_ErrorText() * \fn drxbsp_i2c_error_text()
* \brief Returns a human readable error. * \brief Returns a human readable error.
* Counter part of numerical DRX_I2C_Error_g. * Counter part of numerical drx_i2c_error_g.
* *
* \return char* Pointer to human readable error text. * \return char* Pointer to human readable error text.
*/ */
char *DRXBSP_I2C_ErrorText(void); char *drxbsp_i2c_error_text(void);
/** /**
* \var DRX_I2C_Error_g; * \var drx_i2c_error_g;
* \brief I2C specific error codes, platform dependent. * \brief I2C specific error codes, platform dependent.
*/ */
extern int DRX_I2C_Error_g; extern int drx_i2c_error_g;
#endif /* __BSPI2C_H__ */ #endif /* __BSPI2C_H__ */

122
drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h
View File

@ -79,90 +79,90 @@ DEFINES
TYPEDEFS TYPEDEFS
------------------------------------------------------------------------------*/ ------------------------------------------------------------------------------*/
typedef u32 TUNERMode_t; typedef u32 tuner_mode_t;
typedef u32 *pTUNERMode_t; typedef u32 *ptuner_mode_t;
typedef char *TUNERSubMode_t; /* description of submode */ typedef char *tuner_sub_mode_t; /* description of submode */
typedef TUNERSubMode_t *pTUNERSubMode_t; typedef tuner_sub_mode_t *ptuner_sub_mode_t;
typedef enum { typedef enum {
TUNER_LOCKED, TUNER_LOCKED,
TUNER_NOT_LOCKED TUNER_NOT_LOCKED
} TUNERLockStatus_t, *pTUNERLockStatus_t; } tuner_lock_status_t, *ptuner_lock_status_t;
typedef struct { typedef struct {
char *name; /* Tuner brand & type name */ char *name; /* Tuner brand & type name */
s32 minFreqRF; /* Lowest RF input frequency, in kHz */ s32 min_freq_rf; /* Lowest RF input frequency, in kHz */
s32 maxFreqRF; /* Highest RF input frequency, in kHz */ s32 max_freq_rf; /* Highest RF input frequency, in kHz */
u8 subMode; /* Index to sub-mode in use */ u8 sub_mode; /* Index to sub-mode in use */
pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes */ ptuner_sub_mode_t sub_modeDescriptions; /* Pointer to description of sub-modes */
u8 subModes; /* Number of available sub-modes */ u8 sub_modes; /* Number of available sub-modes */
/* The following fields will be either 0, NULL or false and do not need /* The following fields will be either 0, NULL or false and do not need
initialisation */ initialisation */
void *selfCheck; /* gives proof of initialization */ void *self_check; /* gives proof of initialization */
bool programmed; /* only valid if selfCheck is OK */ bool programmed; /* only valid if self_check is OK */
s32 RFfrequency; /* only valid if programmed */ s32 r_ffrequency; /* only valid if programmed */
s32 IFfrequency; /* only valid if programmed */ s32 i_ffrequency; /* only valid if programmed */
void *myUserData; /* pointer to associated demod instance */ void *myUser_data; /* pointer to associated demod instance */
u16 myCapabilities; /* value for storing application flags */ u16 my_capabilities; /* value for storing application flags */
} TUNERCommonAttr_t, *pTUNERCommonAttr_t; } tuner_common_attr_t, *ptuner_common_attr_t;
/* /*
* Generic functions for DRX devices. * Generic functions for DRX devices.
*/ */
typedef struct TUNERInstance_s *pTUNERInstance_t; typedef struct tuner_instance_s *p_tuner_instance_t;
typedef DRXStatus_t(*TUNEROpenFunc_t) (pTUNERInstance_t tuner); typedef drx_status_t(*tuner_open_func_t) (p_tuner_instance_t tuner);
typedef DRXStatus_t(*TUNERCloseFunc_t) (pTUNERInstance_t tuner); typedef drx_status_t(*tuner_close_func_t) (p_tuner_instance_t tuner);
typedef DRXStatus_t(*TUNERSetFrequencyFunc_t) (pTUNERInstance_t tuner, typedef drx_status_t(*tuner_set_frequency_func_t) (p_tuner_instance_t tuner,
TUNERMode_t mode, tuner_mode_t mode,
s32 s32
frequency); frequency);
typedef DRXStatus_t(*TUNERGetFrequencyFunc_t) (pTUNERInstance_t tuner, typedef drx_status_t(*tuner_get_frequency_func_t) (p_tuner_instance_t tuner,
TUNERMode_t mode, tuner_mode_t mode,
s32 * s32 *
RFfrequency, r_ffrequency,
s32 * s32 *
IFfrequency); i_ffrequency);
typedef DRXStatus_t(*TUNERLockStatusFunc_t) (pTUNERInstance_t tuner, typedef drx_status_t(*tuner_lock_status_func_t) (p_tuner_instance_t tuner,
pTUNERLockStatus_t ptuner_lock_status_t
lockStat); lock_stat);
typedef DRXStatus_t(*TUNERi2cWriteReadFunc_t) (pTUNERInstance_t tuner, typedef drx_status_t(*tune_ri2c_write_read_func_t) (p_tuner_instance_t tuner,
struct i2c_device_addr * struct i2c_device_addr *
wDevAddr, u16 wCount, w_dev_addr, u16 w_count,
u8 *wData, u8 *wData,
struct i2c_device_addr * struct i2c_device_addr *
rDevAddr, u16 rCount, r_dev_addr, u16 r_count,
u8 *rData); u8 *r_data);
typedef struct { typedef struct {
TUNEROpenFunc_t openFunc; tuner_open_func_t open_func;
TUNERCloseFunc_t closeFunc; tuner_close_func_t close_func;
TUNERSetFrequencyFunc_t setFrequencyFunc; tuner_set_frequency_func_t set_frequency_func;
TUNERGetFrequencyFunc_t getFrequencyFunc; tuner_get_frequency_func_t get_frequency_func;
TUNERLockStatusFunc_t lockStatusFunc; tuner_lock_status_func_t lock_statusFunc;
TUNERi2cWriteReadFunc_t i2cWriteReadFunc; tune_ri2c_write_read_func_t i2c_write_read_func;
} TUNERFunc_t, *pTUNERFunc_t; } tuner_func_t, *ptuner_func_t;
typedef struct TUNERInstance_s { typedef struct tuner_instance_s {
struct i2c_device_addr myI2CDevAddr; struct i2c_device_addr my_i2c_dev_addr;
pTUNERCommonAttr_t myCommonAttr; ptuner_common_attr_t my_common_attr;
void *myExtAttr; void *my_ext_attr;
pTUNERFunc_t myFunct; ptuner_func_t my_funct;
} TUNERInstance_t; } tuner_instance_t;
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
ENUM ENUM
@ -176,28 +176,28 @@ STRUCTS
Exported FUNCTIONS Exported FUNCTIONS
------------------------------------------------------------------------------*/ ------------------------------------------------------------------------------*/
DRXStatus_t DRXBSP_TUNER_Open(pTUNERInstance_t tuner); drx_status_t drxbsp_tuner_open(p_tuner_instance_t tuner);
DRXStatus_t DRXBSP_TUNER_Close(pTUNERInstance_t tuner); drx_status_t drxbsp_tuner_close(p_tuner_instance_t tuner);
DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner, drx_status_t drxbsp_tuner_set_frequency(p_tuner_instance_t tuner,
TUNERMode_t mode, tuner_mode_t mode,
s32 frequency); s32 frequency);
DRXStatus_t DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner, drx_status_t drxbsp_tuner_get_frequency(p_tuner_instance_t tuner,
TUNERMode_t mode, tuner_mode_t mode,
s32 *RFfrequency, s32 *r_ffrequency,
s32 *IFfrequency); s32 *i_ffrequency);
DRXStatus_t DRXBSP_TUNER_LockStatus(pTUNERInstance_t tuner, drx_status_t drxbsp_tuner_lock_status(p_tuner_instance_t tuner,
pTUNERLockStatus_t lockStat); ptuner_lock_status_t lock_stat);
DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead(pTUNERInstance_t tuner, drx_status_t drxbsp_tuner_default_i2c_write_read(p_tuner_instance_t tuner,
struct i2c_device_addr *wDevAddr, struct i2c_device_addr *w_dev_addr,
u16 wCount, u16 w_count,
u8 *wData, u8 *wData,
struct i2c_device_addr *rDevAddr, struct i2c_device_addr *r_dev_addr,
u16 rCount, u8 *rData); u16 r_count, u8 *r_data);
/*------------------------------------------------------------------------------ /*------------------------------------------------------------------------------
THE END THE END

138
drivers/media/dvb-frontends/drx39xyj/drx39xxj.c
View File

@ -33,16 +33,16 @@
static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable) static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable)
{ {
struct drx39xxj_state *state = fe->demodulator_priv; struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod; drx_demod_instance_t *demod = state->demod;
int result; int result;
DRXPowerMode_t powerMode; drx_power_mode_t power_mode;
if (enable) if (enable)
powerMode = DRX_POWER_UP; power_mode = DRX_POWER_UP;
else else
powerMode = DRX_POWER_DOWN; power_mode = DRX_POWER_DOWN;
result = DRX_Ctrl(demod, DRX_CTRL_POWER_MODE, &powerMode); result = drx_ctrl(demod, DRX_CTRL_POWER_MODE, &power_mode);
if (result != DRX_STS_OK) { if (result != DRX_STS_OK) {
printk(KERN_ERR "Power state change failed\n"); printk(KERN_ERR "Power state change failed\n");
return 0; return 0;
@ -55,13 +55,13 @@ static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable)
static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status) static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status)
{ {
struct drx39xxj_state *state = fe->demodulator_priv; struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod; drx_demod_instance_t *demod = state->demod;
int result; int result;
DRXLockStatus_t lock_status; drx_lock_status_t lock_status;
*status = 0; *status = 0;
result = DRX_Ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status); result = drx_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status);
if (result != DRX_STS_OK) { if (result != DRX_STS_OK) {
printk(KERN_ERR "drx39xxj: could not get lock status!\n"); printk(KERN_ERR "drx39xxj: could not get lock status!\n");
*status = 0; *status = 0;
@ -102,18 +102,18 @@ static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status)
static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber) static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber)
{ {
struct drx39xxj_state *state = fe->demodulator_priv; struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod; drx_demod_instance_t *demod = state->demod;
int result; int result;
DRXSigQuality_t sig_quality; drx_sig_quality_t sig_quality;
result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
if (result != DRX_STS_OK) { if (result != DRX_STS_OK) {
printk(KERN_ERR "drx39xxj: could not get ber!\n"); printk(KERN_ERR "drx39xxj: could not get ber!\n");
*ber = 0; *ber = 0;
return 0; return 0;
} }
*ber = sig_quality.postReedSolomonBER; *ber = sig_quality.post_reed_solomon_ber;
return 0; return 0;
} }
@ -121,11 +121,11 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe,
u16 *strength) u16 *strength)
{ {
struct drx39xxj_state *state = fe->demodulator_priv; struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod; drx_demod_instance_t *demod = state->demod;
int result; int result;
DRXSigQuality_t sig_quality; drx_sig_quality_t sig_quality;
result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
if (result != DRX_STS_OK) { if (result != DRX_STS_OK) {
printk(KERN_ERR "drx39xxj: could not get signal strength!\n"); printk(KERN_ERR "drx39xxj: could not get signal strength!\n");
*strength = 0; *strength = 0;
@ -140,11 +140,11 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe,
static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr) static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr)
{ {
struct drx39xxj_state *state = fe->demodulator_priv; struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod; drx_demod_instance_t *demod = state->demod;
int result; int result;
DRXSigQuality_t sig_quality; drx_sig_quality_t sig_quality;
result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
if (result != DRX_STS_OK) { if (result != DRX_STS_OK) {
printk(KERN_ERR "drx39xxj: could not read snr!\n"); printk(KERN_ERR "drx39xxj: could not read snr!\n");
*snr = 0; *snr = 0;
@ -158,18 +158,18 @@ static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr)
static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{ {
struct drx39xxj_state *state = fe->demodulator_priv; struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod; drx_demod_instance_t *demod = state->demod;
int result; int result;
DRXSigQuality_t sig_quality; drx_sig_quality_t sig_quality;
result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality); result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
if (result != DRX_STS_OK) { if (result != DRX_STS_OK) {
printk(KERN_ERR "drx39xxj: could not get uc blocks!\n"); printk(KERN_ERR "drx39xxj: could not get uc blocks!\n");
*ucblocks = 0; *ucblocks = 0;
return 0; return 0;
} }
*ucblocks = sig_quality.packetError; *ucblocks = sig_quality.packet_error;
return 0; return 0;
} }
@ -180,12 +180,12 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe)
#endif #endif
struct dtv_frontend_properties *p = &fe->dtv_property_cache; struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct drx39xxj_state *state = fe->demodulator_priv; struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod; drx_demod_instance_t *demod = state->demod;
enum drx_standard standard = DRX_STANDARD_8VSB; enum drx_standard standard = DRX_STANDARD_8VSB;
DRXChannel_t channel; drx_channel_t channel;
int result; int result;
DRXUIOData_t uioData; drxuio_data_t uio_data;
DRXChannel_t defChannel = { /* frequency */ 0, drx_channel_t def_channel = { /* frequency */ 0,
/* bandwidth */ DRX_BANDWIDTH_6MHZ, /* bandwidth */ DRX_BANDWIDTH_6MHZ,
/* mirror */ DRX_MIRROR_NO, /* mirror */ DRX_MIRROR_NO,
/* constellation */ DRX_CONSTELLATION_AUTO, /* constellation */ DRX_CONSTELLATION_AUTO,
@ -216,7 +216,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe)
if (standard != state->current_standard || state->powered_up == 0) { if (standard != state->current_standard || state->powered_up == 0) {
/* Set the standard (will be powered up if necessary */ /* Set the standard (will be powered up if necessary */
result = DRX_Ctrl(demod, DRX_CTRL_SET_STANDARD, &standard); result = drx_ctrl(demod, DRX_CTRL_SET_STANDARD, &standard);
if (result != DRX_STS_OK) { if (result != DRX_STS_OK) {
printk(KERN_ERR "Failed to set standard! result=%02x\n", printk(KERN_ERR "Failed to set standard! result=%02x\n",
result); result);
@ -227,21 +227,21 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe)
} }
/* set channel parameters */ /* set channel parameters */
channel = defChannel; channel = def_channel;
channel.frequency = p->frequency / 1000; channel.frequency = p->frequency / 1000;
channel.bandwidth = DRX_BANDWIDTH_6MHZ; channel.bandwidth = DRX_BANDWIDTH_6MHZ;
channel.constellation = DRX_CONSTELLATION_AUTO; channel.constellation = DRX_CONSTELLATION_AUTO;
/* program channel */ /* program channel */
result = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel); result = drx_ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel);
if (result != DRX_STS_OK) { if (result != DRX_STS_OK) {
printk(KERN_ERR "Failed to set channel!\n"); printk(KERN_ERR "Failed to set channel!\n");
return -EINVAL; return -EINVAL;
} }
/* Just for giggles, let's shut off the LNA again.... */ /* Just for giggles, let's shut off the LNA again.... */
uioData.uio = DRX_UIO1; uio_data.uio = DRX_UIO1;
uioData.value = false; uio_data.value = false;
result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData); result = drx_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data);
if (result != DRX_STS_OK) { if (result != DRX_STS_OK) {
printk(KERN_ERR "Failed to disable LNA!\n"); printk(KERN_ERR "Failed to disable LNA!\n");
return 0; return 0;
@ -268,7 +268,7 @@ static int drx39xxj_sleep(struct dvb_frontend *fe)
static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{ {
struct drx39xxj_state *state = fe->demodulator_priv; struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod; drx_demod_instance_t *demod = state->demod;
bool i2c_gate_state; bool i2c_gate_state;
int result; int result;
@ -287,7 +287,7 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
return 0; return 0;
} }
result = DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state); result = drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state);
if (result != DRX_STS_OK) { if (result != DRX_STS_OK) {
printk(KERN_ERR "drx39xxj: could not open i2c gate [%d]\n", printk(KERN_ERR "drx39xxj: could not open i2c gate [%d]\n",
result); result);
@ -325,12 +325,12 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
{ {
struct drx39xxj_state *state = NULL; struct drx39xxj_state *state = NULL;
struct i2c_device_addr *demodAddr = NULL; struct i2c_device_addr *demod_addr = NULL;
DRXCommonAttr_t *demodCommAttr = NULL; drx_common_attr_t *demod_comm_attr = NULL;
DRXJData_t *demodExtAttr = NULL; drxj_data_t *demod_ext_attr = NULL;
DRXDemodInstance_t *demod = NULL; drx_demod_instance_t *demod = NULL;
DRXUIOCfg_t uioCfg; drxuio_cfg_t uio_cfg;
DRXUIOData_t uioData; drxuio_data_t uio_data;
int result; int result;
/* allocate memory for the internal state */ /* allocate memory for the internal state */
@ -338,50 +338,50 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
if (state == NULL) if (state == NULL)
goto error; goto error;
demod = kmalloc(sizeof(DRXDemodInstance_t), GFP_KERNEL); demod = kmalloc(sizeof(drx_demod_instance_t), GFP_KERNEL);
if (demod == NULL) if (demod == NULL)
goto error; goto error;
demodAddr = kmalloc(sizeof(struct i2c_device_addr), GFP_KERNEL); demod_addr = kmalloc(sizeof(struct i2c_device_addr), GFP_KERNEL);
if (demodAddr == NULL) if (demod_addr == NULL)
goto error; goto error;
demodCommAttr = kmalloc(sizeof(DRXCommonAttr_t), GFP_KERNEL); demod_comm_attr = kmalloc(sizeof(drx_common_attr_t), GFP_KERNEL);
if (demodCommAttr == NULL) if (demod_comm_attr == NULL)
goto error; goto error;
demodExtAttr = kmalloc(sizeof(DRXJData_t), GFP_KERNEL); demod_ext_attr = kmalloc(sizeof(drxj_data_t), GFP_KERNEL);
if (demodExtAttr == NULL) if (demod_ext_attr == NULL)
goto error; goto error;
/* setup the state */ /* setup the state */
state->i2c = i2c; state->i2c = i2c;
state->demod = demod; state->demod = demod;
memcpy(demod, &DRXJDefaultDemod_g, sizeof(DRXDemodInstance_t)); memcpy(demod, &drxj_default_demod_g, sizeof(drx_demod_instance_t));
demod->myI2CDevAddr = demodAddr; demod->my_i2c_dev_addr = demod_addr;
memcpy(demod->myI2CDevAddr, &DRXJDefaultAddr_g, memcpy(demod->my_i2c_dev_addr, &drxj_default_addr_g,
sizeof(struct i2c_device_addr)); sizeof(struct i2c_device_addr));
demod->myI2CDevAddr->userData = state; demod->my_i2c_dev_addr->user_data = state;
demod->myCommonAttr = demodCommAttr; demod->my_common_attr = demod_comm_attr;
memcpy(demod->myCommonAttr, &DRXJDefaultCommAttr_g, memcpy(demod->my_common_attr, &drxj_default_comm_attr_g,
sizeof(DRXCommonAttr_t)); sizeof(drx_common_attr_t));
demod->myCommonAttr->microcode = DRXJ_MC_MAIN; demod->my_common_attr->microcode = DRXJ_MC_MAIN;
#if 0 #if 0
demod->myCommonAttr->verifyMicrocode = false; demod->my_common_attr->verify_microcode = false;
#endif #endif
demod->myCommonAttr->verifyMicrocode = true; demod->my_common_attr->verify_microcode = true;
demod->myCommonAttr->intermediateFreq = 5000; demod->my_common_attr->intermediate_freq = 5000;
demod->myExtAttr = demodExtAttr; demod->my_ext_attr = demod_ext_attr;
memcpy(demod->myExtAttr, &DRXJData_g, sizeof(DRXJData_t)); memcpy(demod->my_ext_attr, &drxj_data_g, sizeof(drxj_data_t));
((DRXJData_t *) demod->myExtAttr)->uioSmaTxMode = ((drxj_data_t *) demod->my_ext_attr)->uio_sma_tx_mode =
DRX_UIO_MODE_READWRITE; DRX_UIO_MODE_READWRITE;
demod->myTuner = NULL; demod->my_tuner = NULL;
result = DRX_Open(demod); result = drx_open(demod);
if (result != DRX_STS_OK) { if (result != DRX_STS_OK) {
printk(KERN_ERR "DRX open failed! Aborting\n"); printk(KERN_ERR "DRX open failed! Aborting\n");
kfree(state); kfree(state);
@ -389,18 +389,18 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
} }
/* Turn off the LNA */ /* Turn off the LNA */
uioCfg.uio = DRX_UIO1; uio_cfg.uio = DRX_UIO1;
uioCfg.mode = DRX_UIO_MODE_READWRITE; uio_cfg.mode = DRX_UIO_MODE_READWRITE;
/* Configure user-I/O #3: enable read/write */ /* Configure user-I/O #3: enable read/write */
result = DRX_Ctrl(demod, DRX_CTRL_UIO_CFG, &uioCfg); result = drx_ctrl(demod, DRX_CTRL_UIO_CFG, &uio_cfg);
if (result != DRX_STS_OK) { if (result != DRX_STS_OK) {
printk(KERN_ERR "Failed to setup LNA GPIO!\n"); printk(KERN_ERR "Failed to setup LNA GPIO!\n");
return NULL; return NULL;
} }
uioData.uio = DRX_UIO1; uio_data.uio = DRX_UIO1;
uioData.value = false; uio_data.value = false;
result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData); result = drx_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data);
if (result != DRX_STS_OK) { if (result != DRX_STS_OK) {
printk(KERN_ERR "Failed to disable LNA!\n"); printk(KERN_ERR "Failed to disable LNA!\n");
return NULL; return NULL;

2
drivers/media/dvb-frontends/drx39xyj/drx39xxj.h
View File

@ -28,7 +28,7 @@
struct drx39xxj_state { struct drx39xxj_state {
struct i2c_adapter *i2c; struct i2c_adapter *i2c;
DRXDemodInstance_t *demod; drx_demod_instance_t *demod;
enum drx_standard current_standard; enum drx_standard current_standard;
struct dvb_frontend frontend; struct dvb_frontend frontend;
int powered_up:1; int powered_up:1;

72
drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c
View File

@ -11,90 +11,90 @@
#include "drx39xxj.h" #include "drx39xxj.h"
/* Dummy function to satisfy drxj.c */ /* Dummy function to satisfy drxj.c */
int DRXBSP_TUNER_Open(struct tuner_instance *tuner) int drxbsp_tuner_open(struct tuner_instance *tuner)
{ {
return DRX_STS_OK; return DRX_STS_OK;
} }
int DRXBSP_TUNER_Close(struct tuner_instance *tuner) int drxbsp_tuner_close(struct tuner_instance *tuner)
{ {
return DRX_STS_OK; return DRX_STS_OK;
} }
int DRXBSP_TUNER_SetFrequency(struct tuner_instance *tuner, int drxbsp_tuner_set_frequency(struct tuner_instance *tuner,
u32 mode, u32 mode,
s32 centerFrequency) s32 center_frequency)
{ {
return DRX_STS_OK; return DRX_STS_OK;
} }
int int
DRXBSP_TUNER_GetFrequency(struct tuner_instance *tuner, drxbsp_tuner_get_frequency(struct tuner_instance *tuner,
u32 mode, u32 mode,
s32 *RFfrequency, s32 *r_ffrequency,
s32 *IFfrequency) s32 *i_ffrequency)
{ {
return DRX_STS_OK; return DRX_STS_OK;
} }
int DRXBSP_HST_Sleep(u32 n) int drxbsp_hst_sleep(u32 n)
{ {
msleep(n); msleep(n);
return DRX_STS_OK; return DRX_STS_OK;
} }
u32 DRXBSP_HST_Clock(void) u32 drxbsp_hst_clock(void)
{ {
return jiffies_to_msecs(jiffies); return jiffies_to_msecs(jiffies);
} }
int DRXBSP_HST_Memcmp(void *s1, void *s2, u32 n) int drxbsp_hst_memcmp(void *s1, void *s2, u32 n)
{ {
return (memcmp(s1, s2, (size_t) n)); return (memcmp(s1, s2, (size_t) n));
} }
void *DRXBSP_HST_Memcpy(void *to, void *from, u32 n) void *drxbsp_hst_memcpy(void *to, void *from, u32 n)
{ {
return (memcpy(to, from, (size_t) n)); return (memcpy(to, from, (size_t) n));
} }
int DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr, int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
u16 wCount, u16 w_count,
u8 *wData, u8 *wData,
struct i2c_device_addr *rDevAddr, struct i2c_device_addr *r_dev_addr,
u16 rCount, u8 *rData) u16 r_count, u8 *r_data)
{ {
struct drx39xxj_state *state; struct drx39xxj_state *state;
struct i2c_msg msg[2]; struct i2c_msg msg[2];
unsigned int num_msgs; unsigned int num_msgs;
if (wDevAddr == NULL) { if (w_dev_addr == NULL) {
/* Read only */ /* Read only */
state = rDevAddr->userData; state = r_dev_addr->user_data;
msg[0].addr = rDevAddr->i2cAddr >> 1; msg[0].addr = r_dev_addr->i2c_addr >> 1;
msg[0].flags = I2C_M_RD; msg[0].flags = I2C_M_RD;
msg[0].buf = rData; msg[0].buf = r_data;
msg[0].len = rCount; msg[0].len = r_count;
num_msgs = 1; num_msgs = 1;
} else if (rDevAddr == NULL) { } else if (r_dev_addr == NULL) {
/* Write only */ /* Write only */
state = wDevAddr->userData; state = w_dev_addr->user_data;
msg[0].addr = wDevAddr->i2cAddr >> 1; msg[0].addr = w_dev_addr->i2c_addr >> 1;
msg[0].flags = 0; msg[0].flags = 0;
msg[0].buf = wData; msg[0].buf = wData;
msg[0].len = wCount; msg[0].len = w_count;
num_msgs = 1; num_msgs = 1;
} else { } else {
/* Both write and read */ /* Both write and read */
state = wDevAddr->userData; state = w_dev_addr->user_data;
msg[0].addr = wDevAddr->i2cAddr >> 1; msg[0].addr = w_dev_addr->i2c_addr >> 1;
msg[0].flags = 0; msg[0].flags = 0;
msg[0].buf = wData; msg[0].buf = wData;
msg[0].len = wCount; msg[0].len = w_count;
msg[1].addr = rDevAddr->i2cAddr >> 1; msg[1].addr = r_dev_addr->i2c_addr >> 1;
msg[1].flags = I2C_M_RD; msg[1].flags = I2C_M_RD;
msg[1].buf = rData; msg[1].buf = r_data;
msg[1].len = rCount; msg[1].len = r_count;
num_msgs = 2; num_msgs = 2;
} }
@ -110,17 +110,17 @@ int DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr,
return DRX_STS_OK; return DRX_STS_OK;
#ifdef DJH_DEBUG #ifdef DJH_DEBUG
struct drx39xxj_state *state = wDevAddr->userData; struct drx39xxj_state *state = w_dev_addr->user_data;
struct i2c_msg msg[2] = { struct i2c_msg msg[2] = {
{.addr = wDevAddr->i2cAddr, {.addr = w_dev_addr->i2c_addr,
.flags = 0, .buf = wData, .len = wCount}, .flags = 0, .buf = wData, .len = w_count},
{.addr = rDevAddr->i2cAddr, {.addr = r_dev_addr->i2c_addr,
.flags = I2C_M_RD, .buf = rData, .len = rCount}, .flags = I2C_M_RD, .buf = r_data, .len = r_count},
}; };
printk("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", printk("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
wDevAddr->i2cAddr, state->i2c, wCount, rCount); w_dev_addr->i2c_addr, state->i2c, w_count, r_count);
if (i2c_transfer(state->i2c, msg, 2) != 2) { if (i2c_transfer(state->i2c, msg, 2) != 2) {
printk(KERN_WARNING "drx3933: I2C write/read failed\n"); printk(KERN_WARNING "drx3933: I2C write/read failed\n");

302
drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c
View File

@ -50,133 +50,133 @@
*******************************************************************************/ *******************************************************************************/
#include "drx_dap_fasi.h" #include "drx_dap_fasi.h"
#include "drx_driver.h" /* for DRXBSP_HST_Memcpy() */ #include "drx_driver.h" /* for drxbsp_hst_memcpy() */
/*============================================================================*/ /*============================================================================*/
/* Function prototypes */ /* Function prototypes */
static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, /* address of I2C device */ static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */ dr_xaddr_t addr, /* address of register/memory */
u16 datasize, /* size of data */ u16 datasize, /* size of data */
u8 *data, /* data to send */ u8 *data, /* data to send */
DRXflags_t flags); /* special device flags */ dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, /* address of I2C device */ static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */ dr_xaddr_t addr, /* address of register/memory */
u16 datasize, /* size of data */ u16 datasize, /* size of data */
u8 *data, /* data to send */ u8 *data, /* data to send */
DRXflags_t flags); /* special device flags */ dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ static int drxdap_fasi_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */
DRXaddr_t addr, /* address of register */ dr_xaddr_t addr, /* address of register */
u8 data, /* data to write */ u8 data, /* data to write */
DRXflags_t flags); /* special device flags */ dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */
DRXaddr_t addr, /* address of register */ dr_xaddr_t addr, /* address of register */
u8 *data, /* buffer to receive data */ u8 *data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */ dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */ dr_xaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */ dr_xaddr_t raddr, /* address to read back from */
u8 datain, /* data to send */ u8 datain, /* data to send */
u8 *dataout); /* data to receive back */ u8 *dataout); /* data to receive back */
static int DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, /* address of I2C device */
DRXaddr_t addr, /* address of register */ dr_xaddr_t addr, /* address of register */
u16 data, /* data to write */ u16 data, /* data to write */
DRXflags_t flags); /* special device flags */ dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, /* address of I2C device */
DRXaddr_t addr, /* address of register */ dr_xaddr_t addr, /* address of register */
u16 *data, /* buffer to receive data */ u16 *data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */ dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, /* address of I2C device */ static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */ dr_xaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */ dr_xaddr_t raddr, /* address to read back from */
u16 datain, /* data to send */ u16 datain, /* data to send */
u16 *dataout); /* data to receive back */ u16 *dataout); /* data to receive back */
static int DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */
DRXaddr_t addr, /* address of register */ dr_xaddr_t addr, /* address of register */
u32 data, /* data to write */ u32 data, /* data to write */
DRXflags_t flags); /* special device flags */ dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */
DRXaddr_t addr, /* address of register */ dr_xaddr_t addr, /* address of register */
u32 *data, /* buffer to receive data */ u32 *data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */ dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */ dr_xaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */ dr_xaddr_t raddr, /* address to read back from */
u32 datain, /* data to send */ u32 datain, /* data to send */
u32 *dataout); /* data to receive back */ u32 *dataout); /* data to receive back */
/* The version structure of this protocol implementation */ /* The version structure of this protocol implementation */
char drxDapFASIModuleName[] = "FASI Data Access Protocol"; char drx_dap_fasi_module_name[] = "FASI Data Access Protocol";
char drxDapFASIVersionText[] = ""; char drx_dap_fasi_version_text[] = "";
DRXVersion_t drxDapFASIVersion = { drx_version_t drx_dap_fasi_version = {
DRX_MODULE_DAP, /**< type identifier of the module */ DRX_MODULE_DAP, /**< type identifier of the module */
drxDapFASIModuleName, /**< name or description of module */ drx_dap_fasi_module_name, /**< name or description of module */
0, /**< major version number */ 0, /**< major version number */
0, /**< minor version number */ 0, /**< minor version number */
0, /**< patch version number */ 0, /**< patch version number */
drxDapFASIVersionText /**< version as text string */ drx_dap_fasi_version_text /**< version as text string */
}; };
/* The structure containing the protocol interface */ /* The structure containing the protocol interface */
DRXAccessFunc_t drxDapFASIFunct_g = { drx_access_func_t drx_dap_fasi_funct_g = {
&drxDapFASIVersion, &drx_dap_fasi_version,
DRXDAP_FASI_WriteBlock, /* Supported */ drxdap_fasi_write_block, /* Supported */
DRXDAP_FASI_ReadBlock, /* Supported */ drxdap_fasi_read_block, /* Supported */
DRXDAP_FASI_WriteReg8, /* Not supported */ drxdap_fasi_write_reg8, /* Not supported */
DRXDAP_FASI_ReadReg8, /* Not supported */ drxdap_fasi_read_reg8, /* Not supported */
DRXDAP_FASI_ReadModifyWriteReg8, /* Not supported */ drxdap_fasi_read_modify_write_reg8, /* Not supported */
DRXDAP_FASI_WriteReg16, /* Supported */ drxdap_fasi_write_reg16, /* Supported */
DRXDAP_FASI_ReadReg16, /* Supported */ drxdap_fasi_read_reg16, /* Supported */
DRXDAP_FASI_ReadModifyWriteReg16, /* Supported */ drxdap_fasi_read_modify_write_reg16, /* Supported */
DRXDAP_FASI_WriteReg32, /* Supported */ drxdap_fasi_write_reg32, /* Supported */
DRXDAP_FASI_ReadReg32, /* Supported */ drxdap_fasi_read_reg32, /* Supported */
DRXDAP_FASI_ReadModifyWriteReg32 /* Not supported */ drxdap_fasi_read_modify_write_reg32 /* Not supported */
}; };
/*============================================================================*/ /*============================================================================*/
/* Functions not supported by protocol*/ /* Functions not supported by protocol*/
static int DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ static int drxdap_fasi_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */
DRXaddr_t addr, /* address of register */ dr_xaddr_t addr, /* address of register */
u8 data, /* data to write */ u8 data, /* data to write */
DRXflags_t flags) dr_xflags_t flags)
{ /* special device flags */ { /* special device flags */
return DRX_STS_ERROR; return DRX_STS_ERROR;
} }
static int DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */
DRXaddr_t addr, /* address of register */ dr_xaddr_t addr, /* address of register */
u8 *data, /* buffer to receive data */ u8 *data, /* buffer to receive data */
DRXflags_t flags) dr_xflags_t flags)
{ /* special device flags */ { /* special device flags */
return DRX_STS_ERROR; return DRX_STS_ERROR;
} }
static int DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */ static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */ dr_xaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */ dr_xaddr_t raddr, /* address to read back from */
u8 datain, /* data to send */ u8 datain, /* data to send */
u8 *dataout) u8 *dataout)
{ /* data to receive back */ { /* data to receive back */
return DRX_STS_ERROR; return DRX_STS_ERROR;
} }
static int DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */ static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */ dr_xaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */ dr_xaddr_t raddr, /* address to read back from */
u32 datain, /* data to send */ u32 datain, /* data to send */
u32 *dataout) u32 *dataout)
{ /* data to receive back */ { /* data to receive back */
@ -187,12 +187,12 @@ static int DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /*
/****************************** /******************************
* *
* int DRXDAP_FASI_ReadBlock ( * int drxdap_fasi_read_block (
* struct i2c_device_addr *devAddr, -- address of I2C device * struct i2c_device_addr *dev_addr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory * dr_xaddr_t addr, -- address of chip register/memory
* u16 datasize, -- number of bytes to read * u16 datasize, -- number of bytes to read
* u8 *data, -- data to receive * u8 *data, -- data to receive
* DRXflags_t flags) -- special device flags * dr_xflags_t flags) -- special device flags
* *
* Read block data from chip address. Because the chip is word oriented, * Read block data from chip address. Because the chip is word oriented,
* the number of bytes to read must be even. * the number of bytes to read must be even.
@ -210,28 +210,28 @@ static int DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /*
* *
******************************/ ******************************/
static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
DRXaddr_t addr, dr_xaddr_t addr,
u16 datasize, u16 datasize,
u8 *data, DRXflags_t flags) u8 *data, dr_xflags_t flags)
{ {
u8 buf[4]; u8 buf[4];
u16 bufx; u16 bufx;
int rc; int rc;
u16 overheadSize = 0; u16 overhead_size = 0;
/* Check parameters ******************************************************* */ /* Check parameters ******************************************************* */
if (devAddr == NULL) { if (dev_addr == NULL) {
return DRX_STS_INVALID_ARG; return DRX_STS_INVALID_ARG;
} }
overheadSize = (IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1) + overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
DRXDAP_FASI_LONG_FORMAT(addr)) || DRXDAP_FASI_LONG_FORMAT(addr)) ||
(overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) || (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) { ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
return DRX_STS_INVALID_ARG; return DRX_STS_INVALID_ARG;
} }
@ -283,13 +283,13 @@ static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr,
* In single master mode, split the read and write actions. * In single master mode, split the read and write actions.
* No special action is needed for write chunks here. * No special action is needed for write chunks here.
*/ */
rc = DRXBSP_I2C_WriteRead(devAddr, bufx, buf, 0, 0, 0); rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, 0, 0, 0);
if (rc == DRX_STS_OK) { if (rc == DRX_STS_OK) {
rc = DRXBSP_I2C_WriteRead(0, 0, 0, devAddr, todo, data); rc = drxbsp_i2c_write_read(0, 0, 0, dev_addr, todo, data);
} }
#else #else
/* In multi master mode, do everything in one RW action */ /* In multi master mode, do everything in one RW action */
rc = DRXBSP_I2C_WriteRead(devAddr, bufx, buf, devAddr, todo, rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo,
data); data);
#endif #endif
data += todo; data += todo;
@ -302,10 +302,10 @@ static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr,
/****************************** /******************************
* *
* int DRXDAP_FASI_ReadModifyWriteReg16 ( * int drxdap_fasi_read_modify_write_reg16 (
* struct i2c_device_addr *devAddr, -- address of I2C device * struct i2c_device_addr *dev_addr, -- address of I2C device
* DRXaddr_t waddr, -- address of chip register/memory * dr_xaddr_t waddr, -- address of chip register/memory
* DRXaddr_t raddr, -- chip address to read back from * dr_xaddr_t raddr, -- chip address to read back from
* u16 wdata, -- data to send * u16 wdata, -- data to send
* u16 *rdata) -- data to receive back * u16 *rdata) -- data to receive back
* *
@ -325,9 +325,9 @@ static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr,
* *
******************************/ ******************************/
static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
DRXaddr_t waddr, dr_xaddr_t waddr,
DRXaddr_t raddr, dr_xaddr_t raddr,
u16 wdata, u16 *rdata) u16 wdata, u16 *rdata)
{ {
int rc = DRX_STS_ERROR; int rc = DRX_STS_ERROR;
@ -337,9 +337,9 @@ static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr,
return DRX_STS_INVALID_ARG; return DRX_STS_INVALID_ARG;
} }
rc = DRXDAP_FASI_WriteReg16(devAddr, waddr, wdata, DRXDAP_FASI_RMW); rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW);
if (rc == DRX_STS_OK) { if (rc == DRX_STS_OK) {
rc = DRXDAP_FASI_ReadReg16(devAddr, raddr, rdata, 0); rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0);
} }
#endif #endif
@ -348,11 +348,11 @@ static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr,
/****************************** /******************************
* *
* int DRXDAP_FASI_ReadReg16 ( * int drxdap_fasi_read_reg16 (
* struct i2c_device_addr *devAddr, -- address of I2C device * struct i2c_device_addr *dev_addr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory * dr_xaddr_t addr, -- address of chip register/memory
* u16 *data, -- data to receive * u16 *data, -- data to receive
* DRXflags_t flags) -- special device flags * dr_xflags_t flags) -- special device flags
* *
* Read one 16-bit register or memory location. The data received back is * Read one 16-bit register or memory location. The data received back is
* converted back to the target platform's endianness. * converted back to the target platform's endianness.
@ -364,9 +364,9 @@ static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr,
* *
******************************/ ******************************/
static int DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr,
DRXaddr_t addr, dr_xaddr_t addr,
u16 *data, DRXflags_t flags) u16 *data, dr_xflags_t flags)
{ {
u8 buf[sizeof(*data)]; u8 buf[sizeof(*data)];
int rc; int rc;
@ -374,18 +374,18 @@ static int DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr,
if (!data) { if (!data) {
return DRX_STS_INVALID_ARG; return DRX_STS_INVALID_ARG;
} }
rc = DRXDAP_FASI_ReadBlock(devAddr, addr, sizeof(*data), buf, flags); rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
*data = buf[0] + (((u16) buf[1]) << 8); *data = buf[0] + (((u16) buf[1]) << 8);
return rc; return rc;
} }
/****************************** /******************************
* *
* int DRXDAP_FASI_ReadReg32 ( * int drxdap_fasi_read_reg32 (
* struct i2c_device_addr *devAddr, -- address of I2C device * struct i2c_device_addr *dev_addr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory * dr_xaddr_t addr, -- address of chip register/memory
* u32 *data, -- data to receive * u32 *data, -- data to receive
* DRXflags_t flags) -- special device flags * dr_xflags_t flags) -- special device flags
* *
* Read one 32-bit register or memory location. The data received back is * Read one 32-bit register or memory location. The data received back is
* converted back to the target platform's endianness. * converted back to the target platform's endianness.
@ -397,9 +397,9 @@ static int DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr,
* *
******************************/ ******************************/
static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
DRXaddr_t addr, dr_xaddr_t addr,
u32 *data, DRXflags_t flags) u32 *data, dr_xflags_t flags)
{ {
u8 buf[sizeof(*data)]; u8 buf[sizeof(*data)];
int rc; int rc;
@ -407,7 +407,7 @@ static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr,
if (!data) { if (!data) {
return DRX_STS_INVALID_ARG; return DRX_STS_INVALID_ARG;
} }
rc = DRXDAP_FASI_ReadBlock(devAddr, addr, sizeof(*data), buf, flags); rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
*data = (((u32) buf[0]) << 0) + *data = (((u32) buf[0]) << 0) +
(((u32) buf[1]) << 8) + (((u32) buf[1]) << 8) +
(((u32) buf[2]) << 16) + (((u32) buf[3]) << 24); (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
@ -416,12 +416,12 @@ static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr,
/****************************** /******************************
* *
* int DRXDAP_FASI_WriteBlock ( * int drxdap_fasi_write_block (
* struct i2c_device_addr *devAddr, -- address of I2C device * struct i2c_device_addr *dev_addr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory * dr_xaddr_t addr, -- address of chip register/memory
* u16 datasize, -- number of bytes to read * u16 datasize, -- number of bytes to read
* u8 *data, -- data to receive * u8 *data, -- data to receive
* DRXflags_t flags) -- special device flags * dr_xflags_t flags) -- special device flags
* *
* Write block data to chip address. Because the chip is word oriented, * Write block data to chip address. Because the chip is word oriented,
* the number of bytes to write must be even. * the number of bytes to write must be even.
@ -436,29 +436,29 @@ static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr,
* *
******************************/ ******************************/
static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
DRXaddr_t addr, dr_xaddr_t addr,
u16 datasize, u16 datasize,
u8 *data, DRXflags_t flags) u8 *data, dr_xflags_t flags)
{ {
u8 buf[DRXDAP_MAX_WCHUNKSIZE]; u8 buf[DRXDAP_MAX_WCHUNKSIZE];
int st = DRX_STS_ERROR; int st = DRX_STS_ERROR;
int firstErr = DRX_STS_OK; int first_err = DRX_STS_OK;
u16 overheadSize = 0; u16 overhead_size = 0;
u16 blockSize = 0; u16 block_size = 0;
/* Check parameters ******************************************************* */ /* Check parameters ******************************************************* */
if (devAddr == NULL) { if (dev_addr == NULL) {
return DRX_STS_INVALID_ARG; return DRX_STS_INVALID_ARG;
} }
overheadSize = (IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1) + overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2); (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) || if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) && ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
DRXDAP_FASI_LONG_FORMAT(addr)) || DRXDAP_FASI_LONG_FORMAT(addr)) ||
(overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) || (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) { ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
return DRX_STS_INVALID_ARG; return DRX_STS_INVALID_ARG;
} }
@ -470,7 +470,7 @@ static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr,
#endif #endif
/* Write block to I2C ***************************************************** */ /* Write block to I2C ***************************************************** */
blockSize = ((DRXDAP_MAX_WCHUNKSIZE) - overheadSize) & ~1; block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1;
do { do {
u16 todo = 0; u16 todo = 0;
u16 bufx = 0; u16 bufx = 0;
@ -505,66 +505,66 @@ static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr,
#endif #endif
/* /*
In single master mode blockSize can be 0. In such a case this I2C In single master mode block_size can be 0. In such a case this I2C
sequense will be visible: (1) write address {i2c addr, sequense will be visible: (1) write address {i2c addr,
4 bytes chip address} (2) write data {i2c addr, 4 bytes data } 4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
(3) write address (4) write data etc... (3) write address (4) write data etc...
Addres must be rewriten because HI is reset after data transport and Addres must be rewriten because HI is reset after data transport and
expects an address. expects an address.
*/ */
todo = (blockSize < datasize ? blockSize : datasize); todo = (block_size < datasize ? block_size : datasize);
if (todo == 0) { if (todo == 0) {
u16 overheadSizeI2cAddr = 0; u16 overhead_sizeI2cAddr = 0;
u16 dataBlockSize = 0; u16 data_block_size = 0;
overheadSizeI2cAddr = overhead_sizeI2cAddr =
(IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1); (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1);
dataBlockSize = data_block_size =
(DRXDAP_MAX_WCHUNKSIZE - overheadSizeI2cAddr) & ~1; (DRXDAP_MAX_WCHUNKSIZE - overhead_sizeI2cAddr) & ~1;
/* write device address */ /* write device address */
st = DRXBSP_I2C_WriteRead(devAddr, st = drxbsp_i2c_write_read(dev_addr,
(u16) (bufx), (u16) (bufx),
buf, buf,
(struct i2c_device_addr *) (NULL), (struct i2c_device_addr *) (NULL),
0, (u8 *) (NULL)); 0, (u8 *) (NULL));
if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) { if ((st != DRX_STS_OK) && (first_err == DRX_STS_OK)) {
/* at the end, return the first error encountered */ /* at the end, return the first error encountered */
firstErr = st; first_err = st;
} }
bufx = 0; bufx = 0;
todo = todo =
(dataBlockSize < (data_block_size <
datasize ? dataBlockSize : datasize); datasize ? data_block_size : datasize);
} }
DRXBSP_HST_Memcpy(&buf[bufx], data, todo); drxbsp_hst_memcpy(&buf[bufx], data, todo);
/* write (address if can do and) data */ /* write (address if can do and) data */
st = DRXBSP_I2C_WriteRead(devAddr, st = drxbsp_i2c_write_read(dev_addr,
(u16) (bufx + todo), (u16) (bufx + todo),
buf, buf,
(struct i2c_device_addr *) (NULL), (struct i2c_device_addr *) (NULL),
0, (u8 *) (NULL)); 0, (u8 *) (NULL));
if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) { if ((st != DRX_STS_OK) && (first_err == DRX_STS_OK)) {
/* at the end, return the first error encountered */ /* at the end, return the first error encountered */
firstErr = st; first_err = st;
} }
datasize -= todo; datasize -= todo;
data += todo; data += todo;
addr += (todo >> 1); addr += (todo >> 1);
} while (datasize); } while (datasize);
return firstErr; return first_err;
} }
/****************************** /******************************
* *
* int DRXDAP_FASI_WriteReg16 ( * int drxdap_fasi_write_reg16 (
* struct i2c_device_addr *devAddr, -- address of I2C device * struct i2c_device_addr *dev_addr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory * dr_xaddr_t addr, -- address of chip register/memory
* u16 data, -- data to send * u16 data, -- data to send
* DRXflags_t flags) -- special device flags * dr_xflags_t flags) -- special device flags
* *
* Write one 16-bit register or memory location. The data being written is * Write one 16-bit register or memory location. The data being written is
* converted from the target platform's endianness to little endian. * converted from the target platform's endianness to little endian.
@ -575,25 +575,25 @@ static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr,
* *
******************************/ ******************************/
static int DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr,
DRXaddr_t addr, dr_xaddr_t addr,
u16 data, DRXflags_t flags) u16 data, dr_xflags_t flags)
{ {
u8 buf[sizeof(data)]; u8 buf[sizeof(data)];
buf[0] = (u8) ((data >> 0) & 0xFF); buf[0] = (u8) ((data >> 0) & 0xFF);
buf[1] = (u8) ((data >> 8) & 0xFF); buf[1] = (u8) ((data >> 8) & 0xFF);
return DRXDAP_FASI_WriteBlock(devAddr, addr, sizeof(data), buf, flags); return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
} }
/****************************** /******************************
* *
* int DRXDAP_FASI_WriteReg32 ( * int drxdap_fasi_write_reg32 (
* struct i2c_device_addr *devAddr, -- address of I2C device * struct i2c_device_addr *dev_addr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory * dr_xaddr_t addr, -- address of chip register/memory
* u32 data, -- data to send * u32 data, -- data to send
* DRXflags_t flags) -- special device flags * dr_xflags_t flags) -- special device flags
* *
* Write one 32-bit register or memory location. The data being written is * Write one 32-bit register or memory location. The data being written is
* converted from the target platform's endianness to little endian. * converted from the target platform's endianness to little endian.
@ -604,9 +604,9 @@ static int DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr,
* *
******************************/ ******************************/
static int DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr, static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
DRXaddr_t addr, dr_xaddr_t addr,
u32 data, DRXflags_t flags) u32 data, dr_xflags_t flags)
{ {
u8 buf[sizeof(data)]; u8 buf[sizeof(data)];
@ -615,5 +615,5 @@ static int DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr,
buf[2] = (u8) ((data >> 16) & 0xFF); buf[2] = (u8) ((data >> 16) & 0xFF);
buf[3] = (u8) ((data >> 24) & 0xFF); buf[3] = (u8) ((data >> 24) & 0xFF);
return DRXDAP_FASI_WriteBlock(devAddr, addr, sizeof(data), buf, flags); return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
} }

2
drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h
View File

@ -238,7 +238,7 @@
extern "C" { extern "C" {
#endif #endif
extern DRXAccessFunc_t drxDapFASIFunct_g; extern drx_access_func_t drx_dap_fasi_funct_g;
#define DRXDAP_FASI_RMW 0x10000000 #define DRXDAP_FASI_RMW 0x10000000
#define DRXDAP_FASI_BROADCAST 0x20000000 #define DRXDAP_FASI_BROADCAST 0x20000000

914
drivers/media/dvb-frontends/drx39xyj/drx_driver.c
View File

File diff suppressed because it is too large Load Diff

966
drivers/media/dvb-frontends/drx39xyj/drx_driver.h
View File

File diff suppressed because it is too large Load Diff

4
drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h
View File

@ -53,8 +53,8 @@ extern "C" {
#ifdef _REGISTERTABLE_ #ifdef _REGISTERTABLE_
#include <registertable.h> #include <registertable.h>
extern RegisterTable_t drx_driver_version[]; extern register_table_t drx_driver_version[];
extern RegisterTableInfo_t drx_driver_version_info[]; extern register_table_info_t drx_driver_version_info[];
#endif /* _REGISTERTABLE_ */ #endif /* _REGISTERTABLE_ */
/* /*

10598
drivers/media/dvb-frontends/drx39xyj/drxj.c
View File

File diff suppressed because it is too large Load Diff

342
drivers/media/dvb-frontends/drx39xyj/drxj.h
View File

@ -77,15 +77,15 @@ TYPEDEFS
typedef struct { typedef struct {
u16 command; u16 command;
/**< Command number */ /**< Command number */
u16 parameterLen; u16 parameter_len;
/**< Data length in byte */ /**< Data length in byte */
u16 resultLen; u16 result_len;
/**< result length in byte */ /**< result length in byte */
u16 *parameter; u16 *parameter;
/**< General purpous param */ /**< General purpous param */
u16 *result; u16 *result;
/**< General purpous param */ /**< General purpous param */
} DRXJSCUCmd_t, *pDRXJSCUCmd_t; } drxjscu_cmd_t, *p_drxjscu_cmd_t;
/*============================================================================*/ /*============================================================================*/
/*============================================================================*/ /*============================================================================*/
@ -137,25 +137,25 @@ TYPEDEFS
DRXJ_CFG_OOB_LO_POW, DRXJ_CFG_OOB_LO_POW,
DRXJ_CFG_MAX /* dummy, never to be used */ DRXJ_CFG_MAX /* dummy, never to be used */
} DRXJCfgType_t, *pDRXJCfgType_t; } drxj_cfg_type_t, *pdrxj_cfg_type_t;
/** /**
* /struct DRXJCfgSmartAntIO_t * /struct drxj_cfg_smart_ant_io_t
* smart antenna i/o. * smart antenna i/o.
*/ */
typedef enum DRXJCfgSmartAntIO_t { typedef enum drxj_cfg_smart_ant_io_t {
DRXJ_SMT_ANT_OUTPUT = 0, DRXJ_SMT_ANT_OUTPUT = 0,
DRXJ_SMT_ANT_INPUT DRXJ_SMT_ANT_INPUT
} DRXJCfgSmartAntIO_t, *pDRXJCfgSmartAntIO_t; } drxj_cfg_smart_ant_io_t, *pdrxj_cfg_smart_ant_io_t;
/** /**
* /struct DRXJCfgSmartAnt_t * /struct drxj_cfg_smart_ant_t
* Set smart antenna. * Set smart antenna.
*/ */
typedef struct { typedef struct {
DRXJCfgSmartAntIO_t io; drxj_cfg_smart_ant_io_t io;
u16 ctrlData; u16 ctrl_data;
} DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t; } drxj_cfg_smart_ant_t, *p_drxj_cfg_smart_ant_t;
/** /**
* /struct DRXJAGCSTATUS_t * /struct DRXJAGCSTATUS_t
@ -164,101 +164,101 @@ TYPEDEFS
typedef struct { typedef struct {
u16 IFAGC; u16 IFAGC;
u16 RFAGC; u16 RFAGC;
u16 DigitalAGC; u16 digital_agc;
} DRXJAgcStatus_t, *pDRXJAgcStatus_t; } drxj_agc_status_t, *pdrxj_agc_status_t;
/* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */ /* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */
/** /**
* /struct DRXJAgcCtrlMode_t * /struct drxj_agc_ctrl_mode_t
* Available AGCs modes in the DRXJ. * Available AGCs modes in the DRXJ.
*/ */
typedef enum { typedef enum {
DRX_AGC_CTRL_AUTO = 0, DRX_AGC_CTRL_AUTO = 0,
DRX_AGC_CTRL_USER, DRX_AGC_CTRL_USER,
DRX_AGC_CTRL_OFF DRX_AGC_CTRL_OFF
} DRXJAgcCtrlMode_t, *pDRXJAgcCtrlMode_t; } drxj_agc_ctrl_mode_t, *pdrxj_agc_ctrl_mode_t;
/** /**
* /struct DRXJCfgAgc_t * /struct drxj_cfg_agc_t
* Generic interface for all AGCs present on the DRXJ. * Generic interface for all AGCs present on the DRXJ.
*/ */
typedef struct { typedef struct {
enum drx_standard standard; /* standard for which these settings apply */ enum drx_standard standard; /* standard for which these settings apply */
DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */ drxj_agc_ctrl_mode_t ctrl_mode; /* off, user, auto */
u16 outputLevel; /* range dependent on AGC */ u16 output_level; /* range dependent on AGC */
u16 minOutputLevel; /* range dependent on AGC */ u16 min_output_level; /* range dependent on AGC */
u16 maxOutputLevel; /* range dependent on AGC */ u16 max_output_level; /* range dependent on AGC */
u16 speed; /* range dependent on AGC */ u16 speed; /* range dependent on AGC */
u16 top; /* rf-agc take over point */ u16 top; /* rf-agc take over point */
u16 cutOffCurrent; /* rf-agc is accelerated if output current u16 cut_off_current; /* rf-agc is accelerated if output current
is below cut-off current */ is below cut-off current */
} DRXJCfgAgc_t, *pDRXJCfgAgc_t; } drxj_cfg_agc_t, *p_drxj_cfg_agc_t;
/* DRXJ_CFG_PRE_SAW */ /* DRXJ_CFG_PRE_SAW */
/** /**
* /struct DRXJCfgPreSaw_t * /struct drxj_cfg_pre_saw_t
* Interface to configure pre SAW sense. * Interface to configure pre SAW sense.
*/ */
typedef struct { typedef struct {
enum drx_standard standard; /* standard to which these settings apply */ enum drx_standard standard; /* standard to which these settings apply */
u16 reference; /* pre SAW reference value, range 0 .. 31 */ u16 reference; /* pre SAW reference value, range 0 .. 31 */
bool usePreSaw; /* true algorithms must use pre SAW sense */ bool use_pre_saw; /* true algorithms must use pre SAW sense */
} DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t; } drxj_cfg_pre_saw_t, *p_drxj_cfg_pre_saw_t;
/* DRXJ_CFG_AFE_GAIN */ /* DRXJ_CFG_AFE_GAIN */
/** /**
* /struct DRXJCfgAfeGain_t * /struct drxj_cfg_afe_gain_t
* Interface to configure gain of AFE (LNA + PGA). * Interface to configure gain of AFE (LNA + PGA).
*/ */
typedef struct { typedef struct {
enum drx_standard standard; /* standard to which these settings apply */ enum drx_standard standard; /* standard to which these settings apply */
u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */ u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */
} DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t; } drxj_cfg_afe_gain_t, *p_drxj_cfg_afe_gain_t;
/** /**
* /struct DRXJRSErrors_t * /struct DRXJrs_errors_t
* Available failure information in DRXJ_FEC_RS. * Available failure information in DRXJ_FEC_RS.
* *
* Container for errors that are received in the most recently finished measurment period * Container for errors that are received in the most recently finished measurment period
* *
*/ */
typedef struct { typedef struct {
u16 nrBitErrors; u16 nr_bit_errors;
/**< no of pre RS bit errors */ /**< no of pre RS bit errors */
u16 nrSymbolErrors; u16 nr_symbol_errors;
/**< no of pre RS symbol errors */ /**< no of pre RS symbol errors */
u16 nrPacketErrors; u16 nr_packet_errors;
/**< no of pre RS packet errors */ /**< no of pre RS packet errors */
u16 nrFailures; u16 nr_failures;
/**< no of post RS failures to decode */ /**< no of post RS failures to decode */
u16 nrSncParFailCount; u16 nr_snc_par_fail_count;
/**< no of post RS bit erros */ /**< no of post RS bit erros */
} DRXJRSErrors_t, *pDRXJRSErrors_t; } DRXJrs_errors_t, *p_drxjrs_errors_t;
/** /**
* /struct DRXJCfgVSBMisc_t * /struct drxj_cfg_vsb_misc_t
* symbol error rate * symbol error rate
*/ */
typedef struct { typedef struct {
u32 symbError; u32 symb_error;
/**< symbol error rate sps */ /**< symbol error rate sps */
} DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t; } drxj_cfg_vsb_misc_t, *p_drxj_cfg_vsb_misc_t;
/** /**
* /enum DRXJMpegOutputClockRate_t * /enum drxj_mpeg_output_clock_rate_t
* Mpeg output clock rate. * Mpeg output clock rate.
* *
*/ */
typedef enum { typedef enum {
DRXJ_MPEG_START_WIDTH_1CLKCYC, DRXJ_MPEG_START_WIDTH_1CLKCYC,
DRXJ_MPEG_START_WIDTH_8CLKCYC DRXJ_MPEG_START_WIDTH_8CLKCYC
} DRXJMpegStartWidth_t, *pDRXJMpegStartWidth_t; } drxj_mpeg_start_width_t, *pdrxj_mpeg_start_width_t;
/** /**
* /enum DRXJMpegOutputClockRate_t * /enum drxj_mpeg_output_clock_rate_t
* Mpeg output clock rate. * Mpeg output clock rate.
* *
*/ */
@ -270,7 +270,7 @@ TYPEDEFS
DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K, DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K, DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K
} DRXJMpegOutputClockRate_t, *pDRXJMpegOutputClockRate_t; } drxj_mpeg_output_clock_rate_t, *pdrxj_mpeg_output_clock_rate_t;
/** /**
* /struct DRXJCfgMisc_t * /struct DRXJCfgMisc_t
@ -279,15 +279,15 @@ TYPEDEFS
* set MPEG output clock rate * set MPEG output clock rate
*/ */
typedef struct { typedef struct {
bool disableTEIHandling; /**< if true pass (not change) TEI bit */ bool disable_tei_handling; /**< if true pass (not change) TEI bit */
bool bitReverseMpegOutout; /**< if true, parallel: msb on MD0; serial: lsb out first */ bool bit_reverse_mpeg_outout; /**< if true, parallel: msb on MD0; serial: lsb out first */
DRXJMpegOutputClockRate_t mpegOutputClockRate; drxj_mpeg_output_clock_rate_t mpeg_output_clock_rate;
/**< set MPEG output clock rate that overwirtes the derived one from symbol rate */ /**< set MPEG output clock rate that overwirtes the derived one from symbol rate */
DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output start width */ drxj_mpeg_start_width_t mpeg_start_width; /**< set MPEG output start width */
} DRXJCfgMpegOutputMisc_t, *pDRXJCfgMpegOutputMisc_t; } drxj_cfg_mpeg_output_misc_t, *p_drxj_cfg_mpeg_output_misc_t;
/** /**
* /enum DRXJXtalFreq_t * /enum drxj_xtal_freq_t
* Supported external crystal reference frequency. * Supported external crystal reference frequency.
*/ */
typedef enum { typedef enum {
@ -295,38 +295,38 @@ TYPEDEFS
DRXJ_XTAL_FREQ_27MHZ, DRXJ_XTAL_FREQ_27MHZ,
DRXJ_XTAL_FREQ_20P25MHZ, DRXJ_XTAL_FREQ_20P25MHZ,
DRXJ_XTAL_FREQ_4MHZ DRXJ_XTAL_FREQ_4MHZ
} DRXJXtalFreq_t, *pDRXJXtalFreq_t; } drxj_xtal_freq_t, *pdrxj_xtal_freq_t;
/** /**
* /enum DRXJXtalFreq_t * /enum drxj_xtal_freq_t
* Supported external crystal reference frequency. * Supported external crystal reference frequency.
*/ */
typedef enum { typedef enum {
DRXJ_I2C_SPEED_400KBPS, DRXJ_I2C_SPEED_400KBPS,
DRXJ_I2C_SPEED_100KBPS DRXJ_I2C_SPEED_100KBPS
} DRXJI2CSpeed_t, *pDRXJI2CSpeed_t; } drxji2c_speed_t, *pdrxji2c_speed_t;
/** /**
* /struct DRXJCfgHwCfg_t * /struct drxj_cfg_hw_cfg_t
* Get hw configuration, such as crystal reference frequency, I2C speed, etc... * Get hw configuration, such as crystal reference frequency, I2C speed, etc...
*/ */
typedef struct { typedef struct {
DRXJXtalFreq_t xtalFreq; drxj_xtal_freq_t xtal_freq;
/**< crystal reference frequency */ /**< crystal reference frequency */
DRXJI2CSpeed_t i2cSpeed; drxji2c_speed_t i2c_speed;
/**< 100 or 400 kbps */ /**< 100 or 400 kbps */
} DRXJCfgHwCfg_t, *pDRXJCfgHwCfg_t; } drxj_cfg_hw_cfg_t, *p_drxj_cfg_hw_cfg_t;
/* /*
* DRXJ_CFG_ATV_MISC * DRXJ_CFG_ATV_MISC
*/ */
typedef struct { typedef struct {
s16 peakFilter; /* -8 .. 15 */ s16 peak_filter; /* -8 .. 15 */
u16 noiseFilter; /* 0 .. 15 */ u16 noise_filter; /* 0 .. 15 */
} DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t; } drxj_cfg_atv_misc_t, *p_drxj_cfg_atv_misc_t;
/* /*
* DRXJCfgOOBMisc_t * drxj_cfg_oob_misc_t
*/ */
#define DRXJ_OOB_STATE_RESET 0x0 #define DRXJ_OOB_STATE_RESET 0x0
#define DRXJ_OOB_STATE_AGN_HUNT 0x1 #define DRXJ_OOB_STATE_AGN_HUNT 0x1
@ -340,15 +340,15 @@ TYPEDEFS
#define DRXJ_OOB_STATE_SYNC 0x40 #define DRXJ_OOB_STATE_SYNC 0x40
typedef struct { typedef struct {
DRXJAgcStatus_t agc; drxj_agc_status_t agc;
bool eqLock; bool eq_lock;
bool symTimingLock; bool sym_timing_lock;
bool phaseLock; bool phase_lock;
bool freqLock; bool freq_lock;
bool digGainLock; bool dig_gain_lock;
bool anaGainLock; bool ana_gain_lock;
u8 state; u8 state;
} DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t; } drxj_cfg_oob_misc_t, *p_drxj_cfg_oob_misc_t;
/* /*
* Index of in array of coef * Index of in array of coef
@ -359,7 +359,7 @@ TYPEDEFS
DRXJ_OOB_LO_POW_MINUS10DB, DRXJ_OOB_LO_POW_MINUS10DB,
DRXJ_OOB_LO_POW_MINUS15DB, DRXJ_OOB_LO_POW_MINUS15DB,
DRXJ_OOB_LO_POW_MAX DRXJ_OOB_LO_POW_MAX
} DRXJCfgOobLoPower_t, *pDRXJCfgOobLoPower_t; } drxj_cfg_oob_lo_power_t, *p_drxj_cfg_oob_lo_power_t;
/* /*
* DRXJ_CFG_ATV_EQU_COEF * DRXJ_CFG_ATV_EQU_COEF
@ -369,7 +369,7 @@ TYPEDEFS
s16 coef1; /* -256 .. 255 */ s16 coef1; /* -256 .. 255 */
s16 coef2; /* -256 .. 255 */ s16 coef2; /* -256 .. 255 */
s16 coef3; /* -256 .. 255 */ s16 coef3; /* -256 .. 255 */
} DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t; } drxj_cfg_atv_equ_coef_t, *p_drxj_cfg_atv_equ_coef_t;
/* /*
* Index of in array of coef * Index of in array of coef
@ -383,7 +383,7 @@ TYPEDEFS
DRXJ_COEF_IDX_DK, DRXJ_COEF_IDX_DK,
DRXJ_COEF_IDX_I, DRXJ_COEF_IDX_I,
DRXJ_COEF_IDX_MAX DRXJ_COEF_IDX_MAX
} DRXJCoefArrayIndex_t, *pDRXJCoefArrayIndex_t; } drxj_coef_array_index_t, *pdrxj_coef_array_index_t;
/* /*
* DRXJ_CFG_ATV_OUTPUT * DRXJ_CFG_ATV_OUTPUT
@ -399,32 +399,32 @@ TYPEDEFS
DRXJ_SIF_ATTENUATION_3DB, DRXJ_SIF_ATTENUATION_3DB,
DRXJ_SIF_ATTENUATION_6DB, DRXJ_SIF_ATTENUATION_6DB,
DRXJ_SIF_ATTENUATION_9DB DRXJ_SIF_ATTENUATION_9DB
} DRXJSIFAttenuation_t, *pDRXJSIFAttenuation_t; } drxjsif_attenuation_t, *pdrxjsif_attenuation_t;
/** /**
* /struct DRXJCfgAtvOutput_t * /struct drxj_cfg_atv_output_t
* SIF attenuation setting. * SIF attenuation setting.
* *
*/ */
typedef struct { typedef struct {
bool enableCVBSOutput; /* true= enabled */ bool enable_cvbs_output; /* true= enabled */
bool enableSIFOutput; /* true= enabled */ bool enable_sif_output; /* true= enabled */
DRXJSIFAttenuation_t sifAttenuation; drxjsif_attenuation_t sif_attenuation;
} DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t; } drxj_cfg_atv_output_t, *p_drxj_cfg_atv_output_t;
/* /*
DRXJ_CFG_ATV_AGC_STATUS (get only) DRXJ_CFG_ATV_AGC_STATUS (get only)
*/ */
/* TODO : AFE interface not yet finished, subject to change */ /* TODO : AFE interface not yet finished, subject to change */
typedef struct { typedef struct {
u16 rfAgcGain; /* 0 .. 877 uA */ u16 rf_agc_gain; /* 0 .. 877 uA */
u16 ifAgcGain; /* 0 .. 877 uA */ u16 if_agc_gain; /* 0 .. 877 uA */
s16 videoAgcGain; /* -75 .. 1972 in 0.1 dB steps */ s16 video_agc_gain; /* -75 .. 1972 in 0.1 dB steps */
s16 audioAgcGain; /* -4 .. 1020 in 0.1 dB steps */ s16 audio_agc_gain; /* -4 .. 1020 in 0.1 dB steps */
u16 rfAgcLoopGain; /* 0 .. 7 */ u16 rf_agc_loop_gain; /* 0 .. 7 */
u16 ifAgcLoopGain; /* 0 .. 7 */ u16 if_agc_loop_gain; /* 0 .. 7 */
u16 videoAgcLoopGain; /* 0 .. 7 */ u16 video_agc_loop_gain; /* 0 .. 7 */
} DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t; } drxj_cfg_atv_agc_status_t, *p_drxj_cfg_atv_agc_status_t;
/*============================================================================*/ /*============================================================================*/
/*============================================================================*/ /*============================================================================*/
@ -439,142 +439,142 @@ TYPEDEFS
/*========================================*/ /*========================================*/
/** /**
* /struct DRXJData_t * /struct drxj_data_t
* DRXJ specific attributes. * DRXJ specific attributes.
* *
* Global data container for DRXJ specific data. * Global data container for DRXJ specific data.
* *
*/ */
typedef struct { typedef struct {
/* device capabilties (determined during DRX_Open()) */ /* device capabilties (determined during drx_open()) */
bool hasLNA; /**< true if LNA (aka PGA) present */ bool has_lna; /**< true if LNA (aka PGA) present */
bool hasOOB; /**< true if OOB supported */ bool has_oob; /**< true if OOB supported */
bool hasNTSC; /**< true if NTSC supported */ bool has_ntsc; /**< true if NTSC supported */
bool hasBTSC; /**< true if BTSC supported */ bool has_btsc; /**< true if BTSC supported */
bool hasSMATX; /**< true if mat_tx is available */ bool has_smatx; /**< true if mat_tx is available */
bool hasSMARX; /**< true if mat_rx is available */ bool has_smarx; /**< true if mat_rx is available */
bool hasGPIO; /**< true if GPIO is available */ bool has_gpio; /**< true if GPIO is available */
bool hasIRQN; /**< true if IRQN is available */ bool has_irqn; /**< true if IRQN is available */
/* A1/A2/A... */ /* A1/A2/A... */
u8 mfx; /**< metal fix */ u8 mfx; /**< metal fix */
/* tuner settings */ /* tuner settings */
bool mirrorFreqSpectOOB;/**< tuner inversion (true = tuner mirrors the signal */ bool mirror_freq_spectOOB;/**< tuner inversion (true = tuner mirrors the signal */
/* standard/channel settings */ /* standard/channel settings */
enum drx_standard standard; /**< current standard information */ enum drx_standard standard; /**< current standard information */
enum drx_modulation constellation; enum drx_modulation constellation;
/**< current constellation */ /**< current constellation */
s32 frequency; /**< center signal frequency in KHz */ s32 frequency; /**< center signal frequency in KHz */
enum drx_bandwidth currBandwidth; enum drx_bandwidth curr_bandwidth;
/**< current channel bandwidth */ /**< current channel bandwidth */
enum drx_mirror mirror; /**< current channel mirror */ enum drx_mirror mirror; /**< current channel mirror */
/* signal quality information */ /* signal quality information */
u32 fecBitsDesired; /**< BER accounting period */ u32 fec_bits_desired; /**< BER accounting period */
u16 fecVdPlen; /**< no of trellis symbols: VD SER measurement period */ u16 fec_vd_plen; /**< no of trellis symbols: VD SER measurement period */
u16 qamVdPrescale; /**< Viterbi Measurement Prescale */ u16 qam_vd_prescale; /**< Viterbi Measurement Prescale */
u16 qamVdPeriod; /**< Viterbi Measurement period */ u16 qam_vd_period; /**< Viterbi Measurement period */
u16 fecRsPlen; /**< defines RS BER measurement period */ u16 fec_rs_plen; /**< defines RS BER measurement period */
u16 fecRsPrescale; /**< ReedSolomon Measurement Prescale */ u16 fec_rs_prescale; /**< ReedSolomon Measurement Prescale */
u16 fecRsPeriod; /**< ReedSolomon Measurement period */ u16 fec_rs_period; /**< ReedSolomon Measurement period */
bool resetPktErrAcc; /**< Set a flag to reset accumulated packet error */ bool reset_pkt_err_acc; /**< Set a flag to reset accumulated packet error */
u16 pktErrAccStart; /**< Set a flag to reset accumulated packet error */ u16 pkt_errAccStart; /**< Set a flag to reset accumulated packet error */
/* HI configuration */ /* HI configuration */
u16 HICfgTimingDiv; /**< HI Configure() parameter 2 */ u16 hi_cfg_timing_div; /**< HI Configure() parameter 2 */
u16 HICfgBridgeDelay; /**< HI Configure() parameter 3 */ u16 hi_cfg_bridge_delay; /**< HI Configure() parameter 3 */
u16 HICfgWakeUpKey; /**< HI Configure() parameter 4 */ u16 hi_cfg_wake_up_key; /**< HI Configure() parameter 4 */
u16 HICfgCtrl; /**< HI Configure() parameter 5 */ u16 hi_cfg_ctrl; /**< HI Configure() parameter 5 */
u16 HICfgTransmit; /**< HI Configure() parameter 6 */ u16 hi_cfg_transmit; /**< HI Configure() parameter 6 */
/* UIO configuartion */ /* UIO configuartion */
DRXUIOMode_t uioSmaRxMode;/**< current mode of SmaRx pin */ drxuio_mode_t uio_sma_rx_mode;/**< current mode of SmaRx pin */
DRXUIOMode_t uioSmaTxMode;/**< current mode of SmaTx pin */ drxuio_mode_t uio_sma_tx_mode;/**< current mode of SmaTx pin */
DRXUIOMode_t uioGPIOMode; /**< current mode of ASEL pin */ drxuio_mode_t uio_gpio_mode; /**< current mode of ASEL pin */
DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */ drxuio_mode_t uio_irqn_mode; /**< current mode of IRQN pin */
/* IQM fs frequecy shift and inversion */ /* IQM fs frequecy shift and inversion */
u32 iqmFsRateOfs; /**< frequency shifter setting after setchannel */ u32 iqm_fs_rate_ofs; /**< frequency shifter setting after setchannel */
bool posImage; /**< Ture: positive image */ bool pos_image; /**< Ture: positive image */
/* IQM RC frequecy shift */ /* IQM RC frequecy shift */
u32 iqmRcRateOfs; /**< frequency shifter setting after setchannel */ u32 iqm_rc_rate_ofs; /**< frequency shifter setting after setchannel */
/* ATV configuartion */ /* ATV configuartion */
u32 atvCfgChangedFlags; /**< flag: flags cfg changes */ u32 atv_cfg_changed_flags; /**< flag: flags cfg changes */
s16 atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */ s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */
s16 atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */ s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */
s16 atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */ s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */
s16 atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */ s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */
bool phaseCorrectionBypass;/**< flag: true=bypass */ bool phase_correction_bypass;/**< flag: true=bypass */
s16 atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */ s16 atv_top_vid_peak; /**< shadow of ATV_TOP_VID_PEAK__A */
u16 atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */ u16 atv_top_noise_th; /**< shadow of ATV_TOP_NOISE_TH__A */
bool enableCVBSOutput; /**< flag CVBS ouput enable */ bool enable_cvbs_output; /**< flag CVBS ouput enable */
bool enableSIFOutput; /**< flag SIF ouput enable */ bool enable_sif_output; /**< flag SIF ouput enable */
DRXJSIFAttenuation_t sifAttenuation; drxjsif_attenuation_t sif_attenuation;
/**< current SIF att setting */ /**< current SIF att setting */
/* Agc configuration for QAM and VSB */ /* Agc configuration for QAM and VSB */
DRXJCfgAgc_t qamRfAgcCfg; /**< qam RF AGC config */ drxj_cfg_agc_t qam_rf_agc_cfg; /**< qam RF AGC config */
DRXJCfgAgc_t qamIfAgcCfg; /**< qam IF AGC config */ drxj_cfg_agc_t qam_if_agc_cfg; /**< qam IF AGC config */
DRXJCfgAgc_t vsbRfAgcCfg; /**< vsb RF AGC config */ drxj_cfg_agc_t vsb_rf_agc_cfg; /**< vsb RF AGC config */
DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */ drxj_cfg_agc_t vsb_if_agc_cfg; /**< vsb IF AGC config */
/* PGA gain configuration for QAM and VSB */ /* PGA gain configuration for QAM and VSB */
u16 qamPgaCfg; /**< qam PGA config */ u16 qam_pga_cfg; /**< qam PGA config */
u16 vsbPgaCfg; /**< vsb PGA config */ u16 vsb_pga_cfg; /**< vsb PGA config */
/* Pre SAW configuration for QAM and VSB */ /* Pre SAW configuration for QAM and VSB */
DRXJCfgPreSaw_t qamPreSawCfg; drxj_cfg_pre_saw_t qam_pre_saw_cfg;
/**< qam pre SAW config */ /**< qam pre SAW config */
DRXJCfgPreSaw_t vsbPreSawCfg; drxj_cfg_pre_saw_t vsb_pre_saw_cfg;
/**< qam pre SAW config */ /**< qam pre SAW config */
/* Version information */ /* Version information */
char vText[2][12]; /**< allocated text versions */ char v_text[2][12]; /**< allocated text versions */
DRXVersion_t vVersion[2]; /**< allocated versions structs */ drx_version_t v_version[2]; /**< allocated versions structs */
DRXVersionList_t vListElements[2]; drx_version_list_t v_list_elements[2];
/**< allocated version list */ /**< allocated version list */
/* smart antenna configuration */ /* smart antenna configuration */
bool smartAntInverted; bool smart_ant_inverted;
/* Tracking filter setting for OOB */ /* Tracking filter setting for OOB */
u16 oobTrkFilterCfg[8]; u16 oob_trk_filter_cfg[8];
bool oobPowerOn; bool oob_power_on;
/* MPEG static bitrate setting */ /* MPEG static bitrate setting */
u32 mpegTsStaticBitrate; /**< bitrate static MPEG output */ u32 mpeg_ts_static_bitrate; /**< bitrate static MPEG output */
bool disableTEIhandling; /**< MPEG TS TEI handling */ bool disable_te_ihandling; /**< MPEG TS TEI handling */
bool bitReverseMpegOutout;/**< MPEG output bit order */ bool bit_reverse_mpeg_outout;/**< MPEG output bit order */
DRXJMpegOutputClockRate_t mpegOutputClockRate; drxj_mpeg_output_clock_rate_t mpeg_output_clock_rate;
/**< MPEG output clock rate */ /**< MPEG output clock rate */
DRXJMpegStartWidth_t mpegStartWidth; drxj_mpeg_start_width_t mpeg_start_width;
/**< MPEG Start width */ /**< MPEG Start width */
/* Pre SAW & Agc configuration for ATV */ /* Pre SAW & Agc configuration for ATV */
DRXJCfgPreSaw_t atvPreSawCfg; drxj_cfg_pre_saw_t atv_pre_saw_cfg;
/**< atv pre SAW config */ /**< atv pre SAW config */
DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */ drxj_cfg_agc_t atv_rf_agc_cfg; /**< atv RF AGC config */
DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */ drxj_cfg_agc_t atv_if_agc_cfg; /**< atv IF AGC config */
u16 atvPgaCfg; /**< atv pga config */ u16 atv_pga_cfg; /**< atv pga config */
u32 currSymbolRate; u32 curr_symbol_rate;
/* pin-safe mode */ /* pin-safe mode */
bool pdrSafeMode; /**< PDR safe mode activated */ bool pdr_safe_mode; /**< PDR safe mode activated */
u16 pdrSafeRestoreValGpio; u16 pdr_safe_restore_val_gpio;
u16 pdrSafeRestoreValVSync; u16 pdr_safe_restore_val_v_sync;
u16 pdrSafeRestoreValSmaRx; u16 pdr_safe_restore_val_sma_rx;
u16 pdrSafeRestoreValSmaTx; u16 pdr_safe_restore_val_sma_tx;
/* OOB pre-saw value */ /* OOB pre-saw value */
u16 oobPreSaw; u16 oob_pre_saw;
DRXJCfgOobLoPower_t oobLoPow; drxj_cfg_oob_lo_power_t oob_lo_pow;
DRXAudData_t audData; drx_aud_data_t aud_data;
/**< audio storage */ /**< audio storage */
} DRXJData_t, *pDRXJData_t; } drxj_data_t, *pdrxj_data_t;
/*------------------------------------------------------------------------- /*-------------------------------------------------------------------------
Access MACROS Access MACROS
@ -591,7 +591,7 @@ Access MACROS
*/ */
#define DRXJ_ATTR_BTSC_DETECT(d) \ #define DRXJ_ATTR_BTSC_DETECT(d) \
(((pDRXJData_t)(d)->myExtAttr)->audData.btscDetect) (((pdrxj_data_t)(d)->my_ext_attr)->aud_data.btsc_detect)
/** /**
* \brief Actual access macros * \brief Actual access macros
@ -723,20 +723,20 @@ STRUCTS
Exported FUNCTIONS Exported FUNCTIONS
-------------------------------------------------------------------------*/ -------------------------------------------------------------------------*/
extern int DRXJ_Open(pDRXDemodInstance_t demod); extern int drxj_open(pdrx_demod_instance_t demod);
extern int DRXJ_Close(pDRXDemodInstance_t demod); extern int drxj_close(pdrx_demod_instance_t demod);
extern int DRXJ_Ctrl(pDRXDemodInstance_t demod, extern int drxj_ctrl(pdrx_demod_instance_t demod,
u32 ctrl, void *ctrlData); u32 ctrl, void *ctrl_data);
/*------------------------------------------------------------------------- /*-------------------------------------------------------------------------
Exported GLOBAL VARIABLES Exported GLOBAL VARIABLES
-------------------------------------------------------------------------*/ -------------------------------------------------------------------------*/
extern DRXAccessFunc_t drxDapDRXJFunct_g; extern drx_access_func_t drx_dap_drxj_funct_g;
extern DRXDemodFunc_t DRXJFunctions_g; extern drx_demod_func_t drxj_functions_g;
extern DRXJData_t DRXJData_g; extern drxj_data_t drxj_data_g;
extern struct i2c_device_addr DRXJDefaultAddr_g; extern struct i2c_device_addr drxj_default_addr_g;
extern DRXCommonAttr_t DRXJDefaultCommAttr_g; extern drx_common_attr_t drxj_default_comm_attr_g;
extern DRXDemodInstance_t DRXJDefaultDemod_g; extern drx_demod_instance_t drxj_default_demod_g;
/*------------------------------------------------------------------------- /*-------------------------------------------------------------------------
THE END THE END

4
drivers/media/dvb-frontends/drx39xyj/drxj_map.h
View File

@ -53,8 +53,8 @@ extern "C" {
#ifdef _REGISTERTABLE_ #ifdef _REGISTERTABLE_
#include <registertable.h> #include <registertable.h>
extern RegisterTable_t drxj_map[]; extern register_table_t drxj_map[];
extern RegisterTableInfo_t drxj_map_info[]; extern register_table_info_t drxj_map_info[];
#endif #endif
#define ATV_COMM_EXEC__A 0xC00000 #define ATV_COMM_EXEC__A 0xC00000