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drm/i915: Store dbuf slice mask in device info

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Let's just store the dbuf slice information as a bitmask
in the device info. Makes life a little easier later.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210416171011.19012-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä 2021-04-16 20:10:06 +03:00
parent 77531b0ef6
commit 578e6edec4
5 changed files with 16 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/display/intel_display_power.c
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@ -4777,7 +4777,7 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices) u8 req_slices)
{ {
int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices; int num_slices = intel_dbuf_num_slices(dev_priv);
struct i915_power_domains *power_domains = &dev_priv->power_domains; struct i915_power_domains *power_domains = &dev_priv->power_domains;
enum dbuf_slice slice; enum dbuf_slice slice;
@ -4825,7 +4825,7 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv) static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
{ {
int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices; int num_slices = intel_dbuf_num_slices(dev_priv);
enum dbuf_slice slice; enum dbuf_slice slice;
for (slice = DBUF_S1; slice < (DBUF_S1 + num_slices); slice++) for (slice = DBUF_S1; slice < (DBUF_S1 + num_slices); slice++)

6
drivers/gpu/drm/i915/i915_pci.c
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@ -648,7 +648,7 @@ static const struct intel_device_info chv_info = {
.display.has_hdcp = 1, \ .display.has_hdcp = 1, \
.display.has_ipc = 1, \ .display.has_ipc = 1, \
.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
.dbuf.num_slices = 1 .dbuf.slice_mask = BIT(DBUF_S1)
#define SKL_PLATFORM \ #define SKL_PLATFORM \
GEN9_FEATURES, \ GEN9_FEATURES, \
@ -683,7 +683,7 @@ static const struct intel_device_info skl_gt4_info = {
#define GEN9_LP_FEATURES \ #define GEN9_LP_FEATURES \
GEN(9), \ GEN(9), \
.is_lp = 1, \ .is_lp = 1, \
.dbuf.num_slices = 1, \ .dbuf.slice_mask = BIT(DBUF_S1), \
.display.has_hotplug = 1, \ .display.has_hotplug = 1, \
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
@ -831,7 +831,7 @@ static const struct intel_device_info cnl_info = {
}, \ }, \
GEN(11), \ GEN(11), \
.dbuf.size = 2048, \ .dbuf.size = 2048, \
.dbuf.num_slices = 2, \ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
.has_logical_ring_elsq = 1, \ .has_logical_ring_elsq = 1, \
.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 } .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }

2
drivers/gpu/drm/i915/intel_device_info.h
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@ -198,7 +198,7 @@ struct intel_device_info {
struct { struct {
u16 size; /* in blocks */ u16 size; /* in blocks */
u8 num_slices; u8 slice_mask;
} dbuf; } dbuf;
/* Register offsets for the various display pipes and transcoders */ /* Register offsets for the various display pipes and transcoders */

13
drivers/gpu/drm/i915/intel_pm.c
View File

@ -3637,7 +3637,7 @@ bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv) u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
{ {
int i; int i;
int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices; int num_slices = intel_dbuf_num_slices(dev_priv);
u8 enabled_slices_mask = 0; u8 enabled_slices_mask = 0;
for (i = 0; i < num_slices; i++) { for (i = 0; i < num_slices; i++) {
@ -4033,10 +4033,15 @@ static int intel_dbuf_size(struct drm_i915_private *dev_priv)
return INTEL_INFO(dev_priv)->dbuf.size; return INTEL_INFO(dev_priv)->dbuf.size;
} }
int intel_dbuf_num_slices(struct drm_i915_private *dev_priv)
{
return hweight8(INTEL_INFO(dev_priv)->dbuf.slice_mask);
}
static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv) static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
{ {
return intel_dbuf_size(dev_priv) / return intel_dbuf_size(dev_priv) /
INTEL_INFO(dev_priv)->dbuf.num_slices; intel_dbuf_num_slices(dev_priv);
} }
static void static void
@ -4063,7 +4068,7 @@ u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
{ {
u32 slice_mask = 0; u32 slice_mask = 0;
u16 ddb_size = intel_dbuf_size(dev_priv); u16 ddb_size = intel_dbuf_size(dev_priv);
int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices; int num_slices = intel_dbuf_num_slices(dev_priv);
u16 slice_size = ddb_size / num_slices; u16 slice_size = ddb_size / num_slices;
u16 start_slice; u16 start_slice;
u16 end_slice; u16 end_slice;
@ -5821,7 +5826,7 @@ skl_compute_ddb(struct intel_atomic_state *state)
"Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n", "Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n",
old_dbuf_state->enabled_slices, old_dbuf_state->enabled_slices,
new_dbuf_state->enabled_slices, new_dbuf_state->enabled_slices,
INTEL_INFO(dev_priv)->dbuf.num_slices); intel_dbuf_num_slices(dev_priv));
} }
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {

1
drivers/gpu/drm/i915/intel_pm.h
View File

@ -38,6 +38,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv); void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv); void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv); u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
int intel_dbuf_num_slices(struct drm_i915_private *dev_priv);
void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
struct skl_ddb_entry *ddb_y, struct skl_ddb_entry *ddb_y,
struct skl_ddb_entry *ddb_uv); struct skl_ddb_entry *ddb_uv);