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drm/i915/uc: Make GuC/HuC fw fetch and loading functions/file structure symmetric
GuC load function is named intel_guc_fw_upload() and HuC load function is
named intel_huc_init_hw(). Make them consistent intel_*_fw_upload. Also
move HuC fw loading functions and declarations to separate files
intel_huc_fw.c|h like GuC.
While at this, do below changes
1. Update kernel-doc comment for intel_*_fw_upload() functions
2. s/huc_ucode_xfer/huc_fw_xfer
3. Introduce intel_huc_fw_init_early()
v2: Changed patch to update HuC functions instead of changing
guc_fw_upload and update file structure. (Michal Wajdeczko)
v3: Added SPDX License identifier to huc_fw.c|h. (Michal Wajdeczko)
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Michal Winiarski <michal.winiarski@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/1519922745-25441-1-git-send-email-sagar.a.kamble@intel.com
This commit is contained in:
Sagar Arun Kamble
Chris Wilson
parent
8c58f73c48
commit
57312eaacd
@ -89,7 +89,8 @@ i915-y += intel_uc.o \
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intel_guc_fw.o \
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intel_guc_log.o \
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intel_guc_submission.o \
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intel_huc.o
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intel_huc.o \
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intel_huc_fw.o
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# autogenerated null render state
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i915-y += intel_renderstate_gen6.o \
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@ -269,15 +269,15 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw, struct i915_vma *vma)
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}
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/**
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* intel_guc_fw_upload() - finish preparing the GuC for activity
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* intel_guc_fw_upload() - load GuC uCode to device
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* @guc: intel_guc structure
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*
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* Called during driver loading and also after a GPU reset.
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* Called from intel_uc_init_hw() during driver load, resume from sleep and
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* after a GPU reset.
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*
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* The main action required here it to load the GuC uCode into the device.
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* The firmware image should have already been fetched into memory by the
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* earlier call to intel_guc_init(), so here we need only check that
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* worked, and then transfer the image to the h/w.
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* earlier call to intel_uc_init_fw(), so here we need to only check that
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* fetch succeeded, and then transfer the image to the h/w.
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*
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* Return: non-zero code on error
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*/
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@ -27,161 +27,9 @@
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#include "intel_huc.h"
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#include "i915_drv.h"
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/**
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* DOC: HuC Firmware
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*
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* Motivation:
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* GEN9 introduces a new dedicated firmware for usage in media HEVC (High
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* Efficiency Video Coding) operations. Userspace can use the firmware
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* capabilities by adding HuC specific commands to batch buffers.
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*
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* Implementation:
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* The same firmware loader is used as the GuC. However, the actual
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* loading to HW is deferred until GEM initialization is done.
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*
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* Note that HuC firmware loading must be done before GuC loading.
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*/
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#define BXT_HUC_FW_MAJOR 01
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#define BXT_HUC_FW_MINOR 07
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#define BXT_BLD_NUM 1398
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#define SKL_HUC_FW_MAJOR 01
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#define SKL_HUC_FW_MINOR 07
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#define SKL_BLD_NUM 1398
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#define KBL_HUC_FW_MAJOR 02
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#define KBL_HUC_FW_MINOR 00
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#define KBL_BLD_NUM 1810
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#define HUC_FW_PATH(platform, major, minor, bld_num) \
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"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
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__stringify(minor) "_" __stringify(bld_num) ".bin"
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#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
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SKL_HUC_FW_MINOR, SKL_BLD_NUM)
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MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
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#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
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BXT_HUC_FW_MINOR, BXT_BLD_NUM)
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MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
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#define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
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KBL_HUC_FW_MINOR, KBL_BLD_NUM)
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MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
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static void huc_fw_select(struct intel_uc_fw *huc_fw)
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{
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struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
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struct drm_i915_private *dev_priv = huc_to_i915(huc);
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GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
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if (!HAS_HUC(dev_priv))
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return;
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if (i915_modparams.huc_firmware_path) {
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huc_fw->path = i915_modparams.huc_firmware_path;
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huc_fw->major_ver_wanted = 0;
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huc_fw->minor_ver_wanted = 0;
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} else if (IS_SKYLAKE(dev_priv)) {
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huc_fw->path = I915_SKL_HUC_UCODE;
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huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
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huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
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} else if (IS_BROXTON(dev_priv)) {
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huc_fw->path = I915_BXT_HUC_UCODE;
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huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
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huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
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} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
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huc_fw->path = I915_KBL_HUC_UCODE;
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huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
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huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
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} else {
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DRM_WARN("%s: No firmware known for this platform!\n",
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intel_uc_fw_type_repr(huc_fw->type));
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}
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}
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/**
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* intel_huc_init_early() - initializes HuC struct
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* @huc: intel_huc struct
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*
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* On platforms with HuC selects firmware for uploading
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*/
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void intel_huc_init_early(struct intel_huc *huc)
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{
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struct intel_uc_fw *huc_fw = &huc->fw;
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intel_uc_fw_init(huc_fw, INTEL_UC_FW_TYPE_HUC);
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huc_fw_select(huc_fw);
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}
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/**
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* huc_ucode_xfer() - DMA's the firmware
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* @huc_fw: the firmware descriptor
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* @vma: the firmware image (bound into the GGTT)
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*
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* Transfer the firmware image to RAM for execution by the microcontroller.
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*
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* Return: 0 on success, non-zero on failure
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*/
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static int huc_ucode_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
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{
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struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
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struct drm_i915_private *dev_priv = huc_to_i915(huc);
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unsigned long offset = 0;
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u32 size;
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int ret;
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GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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/* Set the source address for the uCode */
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offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
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I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
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I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
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/* Hardware doesn't look at destination address for HuC. Set it to 0,
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* but still program the correct address space.
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*/
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I915_WRITE(DMA_ADDR_1_LOW, 0);
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I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
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size = huc_fw->header_size + huc_fw->ucode_size;
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I915_WRITE(DMA_COPY_SIZE, size);
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/* Start the DMA */
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I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
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/* Wait for DMA to finish */
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ret = intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0, 100);
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DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
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/* Disable the bits once DMA is over */
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I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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return ret;
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}
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/**
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* intel_huc_init_hw() - load HuC uCode to device
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* @huc: intel_huc structure
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*
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* Called from intel_uc_init_hw() during driver loading and also after a GPU
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* reset. Be note that HuC loading must be done before GuC loading.
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*
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* The firmware image should have already been fetched into memory by the
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* earlier call to intel_uc_init_fw(), so here we need only check that
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* is succeeded, and then transfer the image to the h/w.
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*
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*/
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int intel_huc_init_hw(struct intel_huc *huc)
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{
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return intel_uc_fw_upload(&huc->fw, huc_ucode_xfer);
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intel_huc_fw_init_early(huc);
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}
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/**
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@ -26,6 +26,7 @@
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#define _INTEL_HUC_H_
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#include "intel_uc_fw.h"
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#include "intel_huc_fw.h"
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struct intel_huc {
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/* Generic uC firmware management */
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@ -35,7 +36,6 @@ struct intel_huc {
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};
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void intel_huc_init_early(struct intel_huc *huc);
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int intel_huc_init_hw(struct intel_huc *huc);
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int intel_huc_auth(struct intel_huc *huc);
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#endif
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166
drivers/gpu/drm/i915/intel_huc_fw.c
Normal file
166
drivers/gpu/drm/i915/intel_huc_fw.c
Normal file
@ -0,0 +1,166 @@
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/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2014-2018 Intel Corporation
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*/
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#include "intel_huc_fw.h"
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#include "i915_drv.h"
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/**
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* DOC: HuC Firmware
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*
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* Motivation:
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* GEN9 introduces a new dedicated firmware for usage in media HEVC (High
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* Efficiency Video Coding) operations. Userspace can use the firmware
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* capabilities by adding HuC specific commands to batch buffers.
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*
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* Implementation:
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* The same firmware loader is used as the GuC. However, the actual
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* loading to HW is deferred until GEM initialization is done.
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*
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* Note that HuC firmware loading must be done before GuC loading.
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*/
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#define BXT_HUC_FW_MAJOR 01
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#define BXT_HUC_FW_MINOR 07
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#define BXT_BLD_NUM 1398
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#define SKL_HUC_FW_MAJOR 01
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#define SKL_HUC_FW_MINOR 07
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#define SKL_BLD_NUM 1398
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#define KBL_HUC_FW_MAJOR 02
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#define KBL_HUC_FW_MINOR 00
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#define KBL_BLD_NUM 1810
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#define HUC_FW_PATH(platform, major, minor, bld_num) \
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"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
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__stringify(minor) "_" __stringify(bld_num) ".bin"
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#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
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SKL_HUC_FW_MINOR, SKL_BLD_NUM)
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MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
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#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
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BXT_HUC_FW_MINOR, BXT_BLD_NUM)
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MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
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#define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
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KBL_HUC_FW_MINOR, KBL_BLD_NUM)
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MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
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static void huc_fw_select(struct intel_uc_fw *huc_fw)
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{
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struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
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struct drm_i915_private *dev_priv = huc_to_i915(huc);
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GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
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if (!HAS_HUC(dev_priv))
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return;
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if (i915_modparams.huc_firmware_path) {
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huc_fw->path = i915_modparams.huc_firmware_path;
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huc_fw->major_ver_wanted = 0;
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huc_fw->minor_ver_wanted = 0;
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} else if (IS_SKYLAKE(dev_priv)) {
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huc_fw->path = I915_SKL_HUC_UCODE;
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huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
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huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
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} else if (IS_BROXTON(dev_priv)) {
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huc_fw->path = I915_BXT_HUC_UCODE;
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huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
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huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
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} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
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huc_fw->path = I915_KBL_HUC_UCODE;
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huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
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huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
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} else {
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DRM_WARN("%s: No firmware known for this platform!\n",
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intel_uc_fw_type_repr(huc_fw->type));
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}
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}
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/**
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* intel_huc_fw_init_early() - initializes HuC firmware struct
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* @huc: intel_huc struct
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*
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* On platforms with HuC selects firmware for uploading
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*/
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void intel_huc_fw_init_early(struct intel_huc *huc)
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{
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struct intel_uc_fw *huc_fw = &huc->fw;
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intel_uc_fw_init(huc_fw, INTEL_UC_FW_TYPE_HUC);
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huc_fw_select(huc_fw);
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}
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/**
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* huc_fw_xfer() - DMA's the firmware
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* @huc_fw: the firmware descriptor
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* @vma: the firmware image (bound into the GGTT)
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*
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* Transfer the firmware image to RAM for execution by the microcontroller.
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*
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* Return: 0 on success, non-zero on failure
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*/
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static int huc_fw_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
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{
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struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
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struct drm_i915_private *dev_priv = huc_to_i915(huc);
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unsigned long offset = 0;
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u32 size;
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int ret;
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GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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/* Set the source address for the uCode */
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offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
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I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
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I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
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/* Hardware doesn't look at destination address for HuC. Set it to 0,
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* but still program the correct address space.
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*/
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I915_WRITE(DMA_ADDR_1_LOW, 0);
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I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
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size = huc_fw->header_size + huc_fw->ucode_size;
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I915_WRITE(DMA_COPY_SIZE, size);
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/* Start the DMA */
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I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
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/* Wait for DMA to finish */
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ret = intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0, 100);
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DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
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/* Disable the bits once DMA is over */
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I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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return ret;
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}
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/**
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* intel_huc_fw_upload() - load HuC uCode to device
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* @huc: intel_huc structure
|
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*
|
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* Called from intel_uc_init_hw() during driver load, resume from sleep and
|
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* after a GPU reset. Note that HuC must be loaded before GuC.
|
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*
|
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* The firmware image should have already been fetched into memory by the
|
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* earlier call to intel_uc_init_fw(), so here we need to only check that
|
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* fetch succeeded, and then transfer the image to the h/w.
|
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*
|
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* Return: non-zero code on error
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*/
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int intel_huc_fw_upload(struct intel_huc *huc)
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{
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return intel_uc_fw_upload(&huc->fw, huc_fw_xfer);
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}
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15
drivers/gpu/drm/i915/intel_huc_fw.h
Normal file
15
drivers/gpu/drm/i915/intel_huc_fw.h
Normal file
@ -0,0 +1,15 @@
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/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2014-2018 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef _INTEL_HUC_FW_H_
|
||||
#define _INTEL_HUC_FW_H_
|
||||
|
||||
struct intel_huc;
|
||||
|
||||
void intel_huc_fw_init_early(struct intel_huc *huc);
|
||||
int intel_huc_fw_upload(struct intel_huc *huc);
|
||||
|
||||
#endif
|
||||
@ -361,7 +361,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
|
||||
goto err_out;
|
||||
|
||||
if (USES_HUC(dev_priv)) {
|
||||
ret = intel_huc_init_hw(huc);
|
||||
ret = intel_huc_fw_upload(huc);
|
||||
if (ret)
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user